1 /* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $ 26 */ 27 28 #include "opt_cpu.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/sysctl.h> 34 #include <sys/malloc.h> 35 #include <sys/memrange.h> 36 #include <sys/cons.h> /* cngetc() */ 37 #include <sys/machintr.h> 38 #include <sys/cpu_topology.h> 39 40 #include <sys/mplock2.h> 41 42 #include <vm/vm.h> 43 #include <vm/vm_param.h> 44 #include <vm/pmap.h> 45 #include <vm/vm_kern.h> 46 #include <vm/vm_extern.h> 47 #include <sys/lock.h> 48 #include <vm/vm_map.h> 49 #include <sys/user.h> 50 #ifdef GPROF 51 #include <sys/gmon.h> 52 #endif 53 54 #include <machine/smp.h> 55 #include <machine_base/apic/apicreg.h> 56 #include <machine/atomic.h> 57 #include <machine/cpufunc.h> 58 #include <machine/cputypes.h> 59 #include <machine_base/apic/lapic.h> 60 #include <machine_base/apic/ioapic.h> 61 #include <machine/psl.h> 62 #include <machine/segments.h> 63 #include <machine/tss.h> 64 #include <machine/specialreg.h> 65 #include <machine/globaldata.h> 66 #include <machine/pmap_inval.h> 67 68 #include <machine/md_var.h> /* setidt() */ 69 #include <machine_base/icu/icu.h> /* IPIs */ 70 #include <machine_base/icu/icu_var.h> 71 #include <machine_base/apic/ioapic_abi.h> 72 #include <machine/intr_machdep.h> /* IPIs */ 73 74 #define WARMBOOT_TARGET 0 75 #define WARMBOOT_OFF (KERNBASE + 0x0467) 76 #define WARMBOOT_SEG (KERNBASE + 0x0469) 77 78 #define CMOS_REG (0x70) 79 #define CMOS_DATA (0x71) 80 #define BIOS_RESET (0x0f) 81 #define BIOS_WARM (0x0a) 82 83 /* 84 * this code MUST be enabled here and in mpboot.s. 85 * it follows the very early stages of AP boot by placing values in CMOS ram. 86 * it NORMALLY will never be needed and thus the primitive method for enabling. 87 * 88 */ 89 #if defined(CHECK_POINTS) 90 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 91 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 92 93 #define CHECK_INIT(D); \ 94 CHECK_WRITE(0x34, (D)); \ 95 CHECK_WRITE(0x35, (D)); \ 96 CHECK_WRITE(0x36, (D)); \ 97 CHECK_WRITE(0x37, (D)); \ 98 CHECK_WRITE(0x38, (D)); \ 99 CHECK_WRITE(0x39, (D)); 100 101 #define CHECK_PRINT(S); \ 102 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \ 103 (S), \ 104 CHECK_READ(0x34), \ 105 CHECK_READ(0x35), \ 106 CHECK_READ(0x36), \ 107 CHECK_READ(0x37), \ 108 CHECK_READ(0x38), \ 109 CHECK_READ(0x39)); 110 111 #else /* CHECK_POINTS */ 112 113 #define CHECK_INIT(D) 114 #define CHECK_PRINT(S) 115 116 #endif /* CHECK_POINTS */ 117 118 /* 119 * Values to send to the POST hardware. 120 */ 121 #define MP_BOOTADDRESS_POST 0x10 122 #define MP_PROBE_POST 0x11 123 #define MPTABLE_PASS1_POST 0x12 124 125 #define MP_START_POST 0x13 126 #define MP_ENABLE_POST 0x14 127 #define MPTABLE_PASS2_POST 0x15 128 129 #define START_ALL_APS_POST 0x16 130 #define INSTALL_AP_TRAMP_POST 0x17 131 #define START_AP_POST 0x18 132 133 #define MP_ANNOUNCE_POST 0x19 134 135 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 136 int current_postcode; 137 138 /** XXX FIXME: what system files declare these??? */ 139 extern struct region_descriptor r_gdt; 140 141 extern int nkpt; 142 extern int naps; 143 144 int64_t tsc0_offset; 145 extern int64_t tsc_offsets[]; 146 147 /* AP uses this during bootstrap. Do not staticize. */ 148 char *bootSTK; 149 static int bootAP; 150 151 struct pcb stoppcbs[MAXCPU]; 152 153 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 154 155 /* 156 * Local data and functions. 157 */ 158 159 static u_int boot_address; 160 static int mp_finish; 161 static int mp_finish_lapic; 162 163 static int start_all_aps(u_int boot_addr); 164 #if 0 165 static void install_ap_tramp(u_int boot_addr); 166 #endif 167 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest); 168 static int smitest(void); 169 static void mp_bsp_simple_setup(void); 170 171 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */ 172 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */ 173 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */ 174 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, ""); 175 static u_int bootMP_size; 176 177 /* Local data for detecting CPU TOPOLOGY */ 178 static int core_bits = 0; 179 static int logical_CPU_bits = 0; 180 181 182 /* 183 * Calculate usable address in base memory for AP trampoline code. 184 */ 185 u_int 186 mp_bootaddress(u_int basemem) 187 { 188 POSTCODE(MP_BOOTADDRESS_POST); 189 190 bootMP_size = mptramp_end - mptramp_start; 191 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 192 if (((basemem * 1024) - boot_address) < bootMP_size) 193 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 194 /* 3 levels of page table pages */ 195 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 196 197 return mptramp_pagetables; 198 } 199 200 /* 201 * Print various information about the SMP system hardware and setup. 202 */ 203 void 204 mp_announce(void) 205 { 206 int x; 207 208 POSTCODE(MP_ANNOUNCE_POST); 209 210 kprintf("DragonFly/MP: Multiprocessor motherboard\n"); 211 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0)); 212 for (x = 1; x <= naps; ++x) 213 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x)); 214 215 if (!ioapic_enable) 216 kprintf(" Warning: APIC I/O disabled\n"); 217 } 218 219 /* 220 * AP cpu's call this to sync up protected mode. 221 * 222 * WARNING! %gs is not set up on entry. This routine sets up %gs. 223 */ 224 void 225 init_secondary(void) 226 { 227 int gsel_tss; 228 int x, myid = bootAP; 229 u_int64_t msr, cr0; 230 struct mdglobaldata *md; 231 struct privatespace *ps; 232 233 ps = &CPU_prvspace[myid]; 234 235 gdt_segs[GPROC0_SEL].ssd_base = 236 (long) &ps->mdglobaldata.gd_common_tss; 237 ps->mdglobaldata.mi.gd_prvspace = ps; 238 239 /* We fill the 32-bit segment descriptors */ 240 for (x = 0; x < NGDT; x++) { 241 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 242 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]); 243 } 244 /* And now a 64-bit one */ 245 ssdtosyssd(&gdt_segs[GPROC0_SEL], 246 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]); 247 248 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 249 r_gdt.rd_base = (long) &gdt[myid * NGDT]; 250 lgdt(&r_gdt); /* does magic intra-segment return */ 251 252 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */ 253 wrmsr(MSR_FSBASE, 0); /* User value */ 254 wrmsr(MSR_GSBASE, (u_int64_t)ps); 255 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */ 256 257 lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]); 258 259 #if 0 260 lldt(_default_ldt); 261 mdcpu->gd_currentldt = _default_ldt; 262 #endif 263 264 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 265 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS; 266 267 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/ 268 269 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */ 270 #if 0 /* JG XXX */ 271 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16; 272 #endif 273 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL]; 274 md->gd_common_tssd = *md->gd_tss_gdt; 275 276 /* double fault stack */ 277 md->gd_common_tss.tss_ist1 = 278 (long)&md->mi.gd_prvspace->idlestack[ 279 sizeof(md->mi.gd_prvspace->idlestack)]; 280 281 ltr(gsel_tss); 282 283 /* 284 * Set to a known state: 285 * Set by mpboot.s: CR0_PG, CR0_PE 286 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 287 */ 288 cr0 = rcr0(); 289 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 290 load_cr0(cr0); 291 292 /* Set up the fast syscall stuff */ 293 msr = rdmsr(MSR_EFER) | EFER_SCE; 294 wrmsr(MSR_EFER, msr); 295 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 296 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 297 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 298 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 299 wrmsr(MSR_STAR, msr); 300 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 301 302 pmap_set_opt(); /* PSE/4MB pages, etc */ 303 pmap_init_pat(); /* Page Attribute Table */ 304 305 /* set up CPU registers and state */ 306 cpu_setregs(); 307 308 /* set up SSE/NX registers */ 309 initializecpu(myid); 310 311 /* set up FPU state on the AP */ 312 npxinit(); 313 314 /* disable the APIC, just to be SURE */ 315 lapic->svr &= ~APIC_SVR_ENABLE; 316 } 317 318 /******************************************************************* 319 * local functions and data 320 */ 321 322 /* 323 * Start the SMP system 324 */ 325 static void 326 mp_start_aps(void *dummy __unused) 327 { 328 if (lapic_enable) { 329 /* start each Application Processor */ 330 start_all_aps(boot_address); 331 } else { 332 mp_bsp_simple_setup(); 333 } 334 } 335 SYSINIT(startaps, SI_BOOT2_START_APS, SI_ORDER_FIRST, mp_start_aps, NULL) 336 337 /* 338 * start each AP in our list 339 */ 340 static int 341 start_all_aps(u_int boot_addr) 342 { 343 vm_offset_t va = boot_address + KERNBASE; 344 u_int64_t *pt4, *pt3, *pt2; 345 int x, i; 346 int shift; 347 int smicount; 348 int smibest; 349 int smilast; 350 u_char mpbiosreason; 351 u_long mpbioswarmvec; 352 struct mdglobaldata *gd; 353 struct privatespace *ps; 354 355 POSTCODE(START_ALL_APS_POST); 356 357 /* install the AP 1st level boot code */ 358 pmap_kenter(va, boot_address); 359 cpu_invlpg((void *)va); /* JG XXX */ 360 bcopy(mptramp_start, (void *)va, bootMP_size); 361 362 /* Locate the page tables, they'll be below the trampoline */ 363 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 364 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 365 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 366 367 /* Create the initial 1GB replicated page tables */ 368 for (i = 0; i < 512; i++) { 369 /* Each slot of the level 4 pages points to the same level 3 page */ 370 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 371 pt4[i] |= kernel_pmap.pmap_bits[PG_V_IDX] | 372 kernel_pmap.pmap_bits[PG_RW_IDX] | 373 kernel_pmap.pmap_bits[PG_U_IDX]; 374 375 /* Each slot of the level 3 pages points to the same level 2 page */ 376 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 377 pt3[i] |= kernel_pmap.pmap_bits[PG_V_IDX] | 378 kernel_pmap.pmap_bits[PG_RW_IDX] | 379 kernel_pmap.pmap_bits[PG_U_IDX]; 380 381 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 382 pt2[i] = i * (2 * 1024 * 1024); 383 pt2[i] |= kernel_pmap.pmap_bits[PG_V_IDX] | 384 kernel_pmap.pmap_bits[PG_RW_IDX] | 385 kernel_pmap.pmap_bits[PG_PS_IDX] | 386 kernel_pmap.pmap_bits[PG_U_IDX]; 387 } 388 389 /* save the current value of the warm-start vector */ 390 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 391 outb(CMOS_REG, BIOS_RESET); 392 mpbiosreason = inb(CMOS_DATA); 393 394 /* setup a vector to our boot code */ 395 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 396 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 397 outb(CMOS_REG, BIOS_RESET); 398 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 399 400 /* 401 * If we have a TSC we can figure out the SMI interrupt rate. 402 * The SMI does not necessarily use a constant rate. Spend 403 * up to 250ms trying to figure it out. 404 */ 405 smibest = 0; 406 if (cpu_feature & CPUID_TSC) { 407 set_apic_timer(275000); 408 smilast = read_apic_timer(); 409 for (x = 0; x < 20 && read_apic_timer(); ++x) { 410 smicount = smitest(); 411 if (smibest == 0 || smilast - smicount < smibest) 412 smibest = smilast - smicount; 413 smilast = smicount; 414 } 415 if (smibest > 250000) 416 smibest = 0; 417 if (smibest) { 418 smibest = smibest * (int64_t)1000000 / 419 get_apic_timer_frequency(); 420 } 421 } 422 if (smibest) 423 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n", 424 1000000 / smibest, smibest); 425 426 /* start each AP */ 427 for (x = 1; x <= naps; ++x) { 428 429 /* This is a bit verbose, it will go away soon. */ 430 431 /* allocate new private data page(s) */ 432 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map, 433 MDGLOBALDATA_BASEALLOC_SIZE); 434 435 gd = &CPU_prvspace[x].mdglobaldata; /* official location */ 436 bzero(gd, sizeof(*gd)); 437 gd->mi.gd_prvspace = ps = &CPU_prvspace[x]; 438 439 /* prime data page for it to use */ 440 mi_gdinit(&gd->mi, x); 441 cpu_gdinit(gd, x); 442 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (naps + 1)); 443 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (naps + 1)); 444 445 /* setup a vector to our boot code */ 446 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 447 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 448 outb(CMOS_REG, BIOS_RESET); 449 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 450 451 /* 452 * Setup the AP boot stack 453 */ 454 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2]; 455 bootAP = x; 456 457 /* attempt to start the Application Processor */ 458 CHECK_INIT(99); /* setup checkpoints */ 459 if (!start_ap(gd, boot_addr, smibest)) { 460 kprintf("\nAP #%d (PHY# %d) failed!\n", 461 x, CPUID_TO_APICID(x)); 462 CHECK_PRINT("trace"); /* show checkpoints */ 463 /* better panic as the AP may be running loose */ 464 kprintf("panic y/n? [y] "); 465 if (cngetc() != 'n') 466 panic("bye-bye"); 467 } 468 CHECK_PRINT("trace"); /* show checkpoints */ 469 } 470 471 /* set ncpus to 1 + highest logical cpu. Not all may have come up */ 472 ncpus = x; 473 474 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */ 475 for (shift = 0; (1 << shift) <= ncpus; ++shift) 476 ; 477 --shift; 478 ncpus2_shift = shift; 479 ncpus2 = 1 << shift; 480 ncpus2_mask = ncpus2 - 1; 481 482 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */ 483 if ((1 << shift) < ncpus) 484 ++shift; 485 ncpus_fit = 1 << shift; 486 ncpus_fit_mask = ncpus_fit - 1; 487 488 /* build our map of 'other' CPUs */ 489 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 490 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus); 491 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus); 492 493 /* restore the warmstart vector */ 494 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 495 outb(CMOS_REG, BIOS_RESET); 496 outb(CMOS_DATA, mpbiosreason); 497 498 /* 499 * NOTE! The idlestack for the BSP was setup by locore. Finish 500 * up, clean out the P==V mapping we did earlier. 501 */ 502 pmap_set_opt(); 503 504 /* 505 * Wait all APs to finish initializing LAPIC 506 */ 507 mp_finish_lapic = 1; 508 if (bootverbose) 509 kprintf("SMP: Waiting APs LAPIC initialization\n"); 510 if (cpu_feature & CPUID_TSC) 511 tsc0_offset = rdtsc(); 512 tsc_offsets[0] = 0; 513 rel_mplock(); 514 while (smp_lapic_mask != smp_startup_mask) { 515 cpu_lfence(); 516 if (cpu_feature & CPUID_TSC) 517 tsc0_offset = rdtsc(); 518 } 519 while (try_mplock() == 0) 520 ; 521 522 /* number of APs actually started */ 523 return ncpus - 1; 524 } 525 526 527 /* 528 * load the 1st level AP boot code into base memory. 529 */ 530 531 /* targets for relocation */ 532 extern void bigJump(void); 533 extern void bootCodeSeg(void); 534 extern void bootDataSeg(void); 535 extern void MPentry(void); 536 extern u_int MP_GDT; 537 extern u_int mp_gdtbase; 538 539 #if 0 540 541 static void 542 install_ap_tramp(u_int boot_addr) 543 { 544 int x; 545 int size = *(int *) ((u_long) & bootMP_size); 546 u_char *src = (u_char *) ((u_long) bootMP); 547 u_char *dst = (u_char *) boot_addr + KERNBASE; 548 u_int boot_base = (u_int) bootMP; 549 u_int8_t *dst8; 550 u_int16_t *dst16; 551 u_int32_t *dst32; 552 553 POSTCODE(INSTALL_AP_TRAMP_POST); 554 555 for (x = 0; x < size; ++x) 556 *dst++ = *src++; 557 558 /* 559 * modify addresses in code we just moved to basemem. unfortunately we 560 * need fairly detailed info about mpboot.s for this to work. changes 561 * to mpboot.s might require changes here. 562 */ 563 564 /* boot code is located in KERNEL space */ 565 dst = (u_char *) boot_addr + KERNBASE; 566 567 /* modify the lgdt arg */ 568 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 569 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 570 571 /* modify the ljmp target for MPentry() */ 572 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 573 *dst32 = ((u_int) MPentry - KERNBASE); 574 575 /* modify the target for boot code segment */ 576 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 577 dst8 = (u_int8_t *) (dst16 + 1); 578 *dst16 = (u_int) boot_addr & 0xffff; 579 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 580 581 /* modify the target for boot data segment */ 582 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 583 dst8 = (u_int8_t *) (dst16 + 1); 584 *dst16 = (u_int) boot_addr & 0xffff; 585 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 586 } 587 588 #endif 589 590 /* 591 * This function starts the AP (application processor) identified 592 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 593 * to accomplish this. This is necessary because of the nuances 594 * of the different hardware we might encounter. It ain't pretty, 595 * but it seems to work. 596 * 597 * NOTE: eventually an AP gets to ap_init(), which is called just 598 * before the AP goes into the LWKT scheduler's idle loop. 599 */ 600 static int 601 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest) 602 { 603 int physical_cpu; 604 int vector; 605 u_long icr_lo, icr_hi; 606 607 POSTCODE(START_AP_POST); 608 609 /* get the PHYSICAL APIC ID# */ 610 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid); 611 612 /* calculate the vector */ 613 vector = (boot_addr >> 12) & 0xff; 614 615 /* We don't want anything interfering */ 616 cpu_disable_intr(); 617 618 /* Make sure the target cpu sees everything */ 619 wbinvd(); 620 621 /* 622 * Try to detect when a SMI has occurred, wait up to 200ms. 623 * 624 * If a SMI occurs during an AP reset but before we issue 625 * the STARTUP command, the AP may brick. To work around 626 * this problem we hold off doing the AP startup until 627 * after we have detected the SMI. Hopefully another SMI 628 * will not occur before we finish the AP startup. 629 * 630 * Retries don't seem to help. SMIs have a window of opportunity 631 * and if USB->legacy keyboard emulation is enabled in the BIOS 632 * the interrupt rate can be quite high. 633 * 634 * NOTE: Don't worry about the L1 cache load, it might bloat 635 * ldelta a little but ndelta will be so huge when the SMI 636 * occurs the detection logic will still work fine. 637 */ 638 if (smibest) { 639 set_apic_timer(200000); 640 smitest(); 641 } 642 643 /* 644 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 645 * and running the target CPU. OR this INIT IPI might be latched (P5 646 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 647 * ignored. 648 * 649 * see apic/apicreg.h for icr bit definitions. 650 * 651 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH. 652 */ 653 654 /* 655 * Setup the address for the target AP. We can setup 656 * icr_hi once and then just trigger operations with 657 * icr_lo. 658 */ 659 icr_hi = lapic->icr_hi & ~APIC_ID_MASK; 660 icr_hi |= (physical_cpu << 24); 661 icr_lo = lapic->icr_lo & 0xfff00000; 662 lapic->icr_hi = icr_hi; 663 664 /* 665 * Do an INIT IPI: assert RESET 666 * 667 * Use edge triggered mode to assert INIT 668 */ 669 lapic->icr_lo = icr_lo | 0x00004500; 670 while (lapic->icr_lo & APIC_DELSTAT_MASK) 671 /* spin */ ; 672 673 /* 674 * The spec calls for a 10ms delay but we may have to use a 675 * MUCH lower delay to avoid bricking an AP due to a fast SMI 676 * interrupt. We have other loops here too and dividing by 2 677 * doesn't seem to be enough even after subtracting 350us, 678 * so we divide by 4. 679 * 680 * Our minimum delay is 150uS, maximum is 10ms. If no SMI 681 * interrupt was detected we use the full 10ms. 682 */ 683 if (smibest == 0) 684 u_sleep(10000); 685 else if (smibest < 150 * 4 + 350) 686 u_sleep(150); 687 else if ((smibest - 350) / 4 < 10000) 688 u_sleep((smibest - 350) / 4); 689 else 690 u_sleep(10000); 691 692 /* 693 * Do an INIT IPI: deassert RESET 694 * 695 * Use level triggered mode to deassert. It is unclear 696 * why we need to do this. 697 */ 698 lapic->icr_lo = icr_lo | 0x00008500; 699 while (lapic->icr_lo & APIC_DELSTAT_MASK) 700 /* spin */ ; 701 u_sleep(150); /* wait 150us */ 702 703 /* 704 * Next we do a STARTUP IPI: the previous INIT IPI might still be 705 * latched, (P5 bug) this 1st STARTUP would then terminate 706 * immediately, and the previously started INIT IPI would continue. OR 707 * the previous INIT IPI has already run. and this STARTUP IPI will 708 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 709 * will run. 710 */ 711 lapic->icr_lo = icr_lo | 0x00000600 | vector; 712 while (lapic->icr_lo & APIC_DELSTAT_MASK) 713 /* spin */ ; 714 u_sleep(200); /* wait ~200uS */ 715 716 /* 717 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 718 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 719 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 720 * recognized after hardware RESET or INIT IPI. 721 */ 722 lapic->icr_lo = icr_lo | 0x00000600 | vector; 723 while (lapic->icr_lo & APIC_DELSTAT_MASK) 724 /* spin */ ; 725 726 /* Resume normal operation */ 727 cpu_enable_intr(); 728 729 /* wait for it to start, see ap_init() */ 730 set_apic_timer(5000000);/* == 5 seconds */ 731 while (read_apic_timer()) { 732 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid)) 733 return 1; /* return SUCCESS */ 734 } 735 736 return 0; /* return FAILURE */ 737 } 738 739 static 740 int 741 smitest(void) 742 { 743 int64_t ltsc; 744 int64_t ntsc; 745 int64_t ldelta; 746 int64_t ndelta; 747 int count; 748 749 ldelta = 0; 750 ndelta = 0; 751 while (read_apic_timer()) { 752 ltsc = rdtsc(); 753 for (count = 0; count < 100; ++count) 754 ntsc = rdtsc(); /* force loop to occur */ 755 if (ldelta) { 756 ndelta = ntsc - ltsc; 757 if (ldelta > ndelta) 758 ldelta = ndelta; 759 if (ndelta > ldelta * 2) 760 break; 761 } else { 762 ldelta = ntsc - ltsc; 763 } 764 } 765 return(read_apic_timer()); 766 } 767 768 /* 769 * Synchronously flush the TLB on all other CPU's. The current cpu's 770 * TLB is not flushed. If the caller wishes to flush the current cpu's 771 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb(). 772 * 773 * NOTE: If for some reason we were unable to start all cpus we cannot 774 * safely use broadcast IPIs. 775 */ 776 777 static cpumask_t smp_invltlb_req; 778 779 #define SMP_INVLTLB_DEBUG 780 781 void 782 smp_invltlb(void) 783 { 784 struct mdglobaldata *md = mdcpu; 785 #ifdef SMP_INVLTLB_DEBUG 786 long count = 0; 787 long xcount = 0; 788 #endif 789 790 crit_enter_gd(&md->mi); 791 md->gd_invltlb_ret = 0; 792 ++md->mi.gd_cnt.v_smpinvltlb; 793 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask); 794 #ifdef SMP_INVLTLB_DEBUG 795 again: 796 #endif 797 if (smp_startup_mask == smp_active_mask) { 798 all_but_self_ipi(XINVLTLB_OFFSET); 799 } else { 800 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask, 801 XINVLTLB_OFFSET, APIC_DELMODE_FIXED); 802 } 803 804 #ifdef SMP_INVLTLB_DEBUG 805 if (xcount) 806 kprintf("smp_invltlb: ipi sent\n"); 807 #endif 808 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) != 809 (smp_active_mask & ~md->mi.gd_cpumask)) { 810 cpu_mfence(); 811 cpu_pause(); 812 #ifdef SMP_INVLTLB_DEBUG 813 /* DEBUGGING */ 814 if (++count == 400000000) { 815 print_backtrace(-1); 816 kprintf("smp_invltlb: endless loop %08lx %08lx, " 817 "rflags %016jx retry", 818 (long)md->gd_invltlb_ret, 819 (long)smp_invltlb_req, 820 (intmax_t)read_rflags()); 821 __asm __volatile ("sti"); 822 ++xcount; 823 if (xcount > 2) 824 lwkt_process_ipiq(); 825 if (xcount > 3) { 826 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret & 827 ~md->mi.gd_cpumask & 828 smp_active_mask); 829 globaldata_t xgd; 830 831 kprintf("bcpu %d\n", bcpu); 832 xgd = globaldata_find(bcpu); 833 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm); 834 } 835 if (xcount > 5) 836 Debugger("giving up"); 837 count = 0; 838 goto again; 839 } 840 #endif 841 } 842 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask); 843 crit_exit_gd(&md->mi); 844 } 845 846 /* 847 * Called from Xinvltlb assembly with interrupts disabled. We didn't 848 * bother to bump the critical section count or nested interrupt count 849 * so only do very low level operations here. 850 */ 851 void 852 smp_invltlb_intr(void) 853 { 854 struct mdglobaldata *md = mdcpu; 855 struct mdglobaldata *omd; 856 cpumask_t mask; 857 int cpu; 858 859 cpu_mfence(); 860 mask = smp_invltlb_req; 861 cpu_invltlb(); 862 while (mask) { 863 cpu = BSFCPUMASK(mask); 864 mask &= ~CPUMASK(cpu); 865 omd = (struct mdglobaldata *)globaldata_find(cpu); 866 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask); 867 } 868 } 869 870 void 871 cpu_wbinvd_on_all_cpus_callback(void *arg) 872 { 873 wbinvd(); 874 } 875 876 void 877 smp_invlpg_range_cpusync(void *arg) 878 { 879 vm_offset_t eva, sva, addr; 880 sva = ((struct smp_invlpg_range_cpusync_arg *)arg)->sva; 881 eva = ((struct smp_invlpg_range_cpusync_arg *)arg)->eva; 882 883 for (addr = sva; addr < eva; addr += PAGE_SIZE) { 884 cpu_invlpg((void *)addr); 885 } 886 } 887 888 /* 889 * When called the executing CPU will send an IPI to all other CPUs 890 * requesting that they halt execution. 891 * 892 * Usually (but not necessarily) called with 'other_cpus' as its arg. 893 * 894 * - Signals all CPUs in map to stop. 895 * - Waits for each to stop. 896 * 897 * Returns: 898 * -1: error 899 * 0: NA 900 * 1: ok 901 * 902 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 903 * from executing at same time. 904 */ 905 int 906 stop_cpus(cpumask_t map) 907 { 908 map &= smp_active_mask; 909 910 /* send the Xcpustop IPI to all CPUs in map */ 911 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 912 913 while ((stopped_cpus & map) != map) 914 /* spin */ ; 915 916 return 1; 917 } 918 919 920 /* 921 * Called by a CPU to restart stopped CPUs. 922 * 923 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 924 * 925 * - Signals all CPUs in map to restart. 926 * - Waits for each to restart. 927 * 928 * Returns: 929 * -1: error 930 * 0: NA 931 * 1: ok 932 */ 933 int 934 restart_cpus(cpumask_t map) 935 { 936 /* signal other cpus to restart */ 937 started_cpus = map & smp_active_mask; 938 939 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */ 940 /* spin */ ; 941 942 return 1; 943 } 944 945 /* 946 * This is called once the mpboot code has gotten us properly relocated 947 * and the MMU turned on, etc. ap_init() is actually the idle thread, 948 * and when it returns the scheduler will call the real cpu_idle() main 949 * loop for the idlethread. Interrupts are disabled on entry and should 950 * remain disabled at return. 951 */ 952 void 953 ap_init(void) 954 { 955 int cpu_id; 956 957 /* 958 * Adjust smp_startup_mask to signal the BSP that we have started 959 * up successfully. Note that we do not yet hold the BGL. The BSP 960 * is waiting for our signal. 961 * 962 * We can't set our bit in smp_active_mask yet because we are holding 963 * interrupts physically disabled and remote cpus could deadlock 964 * trying to send us an IPI. 965 */ 966 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid); 967 cpu_mfence(); 968 969 /* 970 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is 971 * non-zero, then get the MP lock. 972 * 973 * Note: We are in a critical section. 974 * 975 * Note: we are the idle thread, we can only spin. 976 * 977 * Note: The load fence is memory volatile and prevents the compiler 978 * from improperly caching mp_finish_lapic, and the cpu from improperly 979 * caching it. 980 */ 981 while (mp_finish_lapic == 0) 982 cpu_lfence(); 983 while (try_mplock() == 0) 984 ; 985 986 if (cpu_feature & CPUID_TSC) { 987 /* 988 * The BSP is constantly updating tsc0_offset, figure out 989 * the relative difference to synchronize ktrdump. 990 */ 991 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset; 992 } 993 994 /* BSP may have changed PTD while we're waiting for the lock */ 995 cpu_invltlb(); 996 997 /* Build our map of 'other' CPUs. */ 998 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 999 1000 /* A quick check from sanity claus */ 1001 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24); 1002 if (mycpu->gd_cpuid != cpu_id) { 1003 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid); 1004 kprintf("SMP: actual cpuid = %d lapicid %d\n", 1005 cpu_id, (lapic->id & 0xff000000) >> 24); 1006 #if JGXXX 1007 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 1008 #endif 1009 panic("cpuid mismatch! boom!!"); 1010 } 1011 1012 /* Initialize AP's local APIC for irq's */ 1013 lapic_init(FALSE); 1014 1015 /* LAPIC initialization is done */ 1016 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid); 1017 cpu_mfence(); 1018 1019 /* Let BSP move onto the next initialization stage */ 1020 rel_mplock(); 1021 1022 /* 1023 * Interlock for finalization. Wait until mp_finish is non-zero, 1024 * then get the MP lock. 1025 * 1026 * Note: We are in a critical section. 1027 * 1028 * Note: we are the idle thread, we can only spin. 1029 * 1030 * Note: The load fence is memory volatile and prevents the compiler 1031 * from improperly caching mp_finish, and the cpu from improperly 1032 * caching it. 1033 */ 1034 while (mp_finish == 0) 1035 cpu_lfence(); 1036 while (try_mplock() == 0) 1037 ; 1038 1039 /* BSP may have changed PTD while we're waiting for the lock */ 1040 cpu_invltlb(); 1041 1042 /* Set memory range attributes for this CPU to match the BSP */ 1043 mem_range_AP_init(); 1044 1045 /* 1046 * Once we go active we must process any IPIQ messages that may 1047 * have been queued, because no actual IPI will occur until we 1048 * set our bit in the smp_active_mask. If we don't the IPI 1049 * message interlock could be left set which would also prevent 1050 * further IPIs. 1051 * 1052 * The idle loop doesn't expect the BGL to be held and while 1053 * lwkt_switch() normally cleans things up this is a special case 1054 * because we returning almost directly into the idle loop. 1055 * 1056 * The idle thread is never placed on the runq, make sure 1057 * nothing we've done put it there. 1058 */ 1059 KKASSERT(get_mplock_count(curthread) == 1); 1060 smp_active_mask |= CPUMASK(mycpu->gd_cpuid); 1061 1062 /* 1063 * Enable interrupts here. idle_restore will also do it, but 1064 * doing it here lets us clean up any strays that got posted to 1065 * the CPU during the AP boot while we are still in a critical 1066 * section. 1067 */ 1068 __asm __volatile("sti; pause; pause"::); 1069 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 1070 1071 initclocks_pcpu(); /* clock interrupts (via IPIs) */ 1072 lwkt_process_ipiq(); 1073 1074 /* 1075 * Releasing the mp lock lets the BSP finish up the SMP init 1076 */ 1077 rel_mplock(); 1078 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0); 1079 } 1080 1081 /* 1082 * Get SMP fully working before we start initializing devices. 1083 */ 1084 static 1085 void 1086 ap_finish(void) 1087 { 1088 mp_finish = 1; 1089 if (bootverbose) 1090 kprintf("Finish MP startup\n"); 1091 rel_mplock(); 1092 while (smp_active_mask != smp_startup_mask) 1093 cpu_lfence(); 1094 while (try_mplock() == 0) 1095 ; 1096 if (bootverbose) { 1097 kprintf("Active CPU Mask: %016jx\n", 1098 (uintmax_t)smp_active_mask); 1099 } 1100 } 1101 1102 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL) 1103 1104 void 1105 cpu_send_ipiq(int dcpu) 1106 { 1107 if (CPUMASK(dcpu) & smp_active_mask) 1108 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED); 1109 } 1110 1111 #if 0 /* single_apic_ipi_passive() not working yet */ 1112 /* 1113 * Returns 0 on failure, 1 on success 1114 */ 1115 int 1116 cpu_send_ipiq_passive(int dcpu) 1117 { 1118 int r = 0; 1119 if (CPUMASK(dcpu) & smp_active_mask) { 1120 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET, 1121 APIC_DELMODE_FIXED); 1122 } 1123 return(r); 1124 } 1125 #endif 1126 1127 static void 1128 mp_bsp_simple_setup(void) 1129 { 1130 /* build our map of 'other' CPUs */ 1131 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 1132 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus); 1133 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus); 1134 1135 pmap_set_opt(); 1136 1137 if (cpu_feature & CPUID_TSC) 1138 tsc0_offset = rdtsc(); 1139 } 1140 1141 1142 /* 1143 * CPU TOPOLOGY DETECTION FUNCTIONS 1144 */ 1145 1146 /* Detect intel topology using CPUID 1147 * Ref: http://www.intel.com/Assets/PDF/appnote/241618.pdf, pg 41 1148 */ 1149 static void 1150 detect_intel_topology(int count_htt_cores) 1151 { 1152 int shift = 0; 1153 int ecx_index = 0; 1154 int core_plus_logical_bits = 0; 1155 int cores_per_package; 1156 int logical_per_package; 1157 int logical_per_core; 1158 unsigned int p[4]; 1159 1160 if (cpu_high >= 0xb) { 1161 goto FUNC_B; 1162 1163 } else if (cpu_high >= 0x4) { 1164 goto FUNC_4; 1165 1166 } else { 1167 core_bits = 0; 1168 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1169 ; 1170 logical_CPU_bits = 1 << shift; 1171 return; 1172 } 1173 1174 FUNC_B: 1175 cpuid_count(0xb, FUNC_B_THREAD_LEVEL, p); 1176 1177 /* if 0xb not supported - fallback to 0x4 */ 1178 if (p[1] == 0 || (FUNC_B_TYPE(p[2]) != FUNC_B_THREAD_TYPE)) { 1179 goto FUNC_4; 1180 } 1181 1182 logical_CPU_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1183 1184 ecx_index = FUNC_B_THREAD_LEVEL + 1; 1185 do { 1186 cpuid_count(0xb, ecx_index, p); 1187 1188 /* Check for the Core type in the implemented sub leaves. */ 1189 if (FUNC_B_TYPE(p[2]) == FUNC_B_CORE_TYPE) { 1190 core_plus_logical_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1191 break; 1192 } 1193 1194 ecx_index++; 1195 1196 } while (FUNC_B_TYPE(p[2]) != FUNC_B_INVALID_TYPE); 1197 1198 core_bits = core_plus_logical_bits - logical_CPU_bits; 1199 1200 return; 1201 1202 FUNC_4: 1203 cpuid_count(0x4, 0, p); 1204 cores_per_package = FUNC_4_MAX_CORE_NO(p[0]) + 1; 1205 1206 logical_per_package = count_htt_cores; 1207 logical_per_core = logical_per_package / cores_per_package; 1208 1209 for (shift = 0; (1 << shift) < logical_per_core; ++shift) 1210 ; 1211 logical_CPU_bits = shift; 1212 1213 for (shift = 0; (1 << shift) < cores_per_package; ++shift) 1214 ; 1215 core_bits = shift; 1216 1217 return; 1218 } 1219 1220 /* Detect AMD topology using CPUID 1221 * Ref: http://support.amd.com/us/Embedded_TechDocs/25481.pdf, last page 1222 */ 1223 static void 1224 detect_amd_topology(int count_htt_cores) 1225 { 1226 int shift = 0; 1227 if ((cpu_feature & CPUID_HTT) 1228 && (amd_feature2 & AMDID2_CMP)) { 1229 1230 if (cpu_procinfo2 & AMDID_COREID_SIZE) { 1231 core_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) 1232 >> AMDID_COREID_SIZE_SHIFT; 1233 } else { 1234 core_bits = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 1235 for (shift = 0; (1 << shift) < core_bits; ++shift) 1236 ; 1237 core_bits = shift; 1238 } 1239 1240 logical_CPU_bits = count_htt_cores >> core_bits; 1241 for (shift = 0; (1 << shift) < logical_CPU_bits; ++shift) 1242 ; 1243 logical_CPU_bits = shift; 1244 } else { 1245 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1246 ; 1247 core_bits = shift; 1248 logical_CPU_bits = 0; 1249 } 1250 } 1251 1252 static void 1253 amd_get_compute_unit_id(void *arg) 1254 { 1255 u_int regs[4]; 1256 1257 do_cpuid(0x8000001e, regs); 1258 cpu_node_t * mynode = get_cpu_node_by_cpuid(mycpuid); 1259 /* 1260 * AMD - CPUID Specification September 2010 1261 * page 34 - //ComputeUnitID = ebx[0:7]// 1262 */ 1263 mynode->compute_unit_id = regs[1] & 0xff; 1264 } 1265 1266 int 1267 fix_amd_topology(void) 1268 { 1269 if (cpu_vendor_id != CPU_VENDOR_AMD) 1270 return -1; 1271 if ((amd_feature2 & AMDID2_TOPOEXT) == 0) 1272 return -1; 1273 1274 lwkt_cpusync_simple(-1, amd_get_compute_unit_id, NULL); 1275 1276 kprintf("Compute unit iDS:\n"); 1277 int i; 1278 for (i = 0; i < ncpus; i++) 1279 kprintf("%d-%d; \n", i, get_cpu_node_by_cpuid(i)->compute_unit_id); 1280 1281 return 0; 1282 } 1283 1284 /* Calculate 1285 * - logical_CPU_bits 1286 * - core_bits 1287 * With the values above (for AMD or INTEL) we are able to generally 1288 * detect the CPU topology (number of cores for each level): 1289 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1290 * Ref: http://www.multicoreinfo.com/research/papers/whitepapers/Intel-detect-topology.pdf 1291 */ 1292 void 1293 detect_cpu_topology(void) 1294 { 1295 static int topology_detected = 0; 1296 int count = 0; 1297 1298 if (topology_detected) { 1299 goto OUT; 1300 } 1301 1302 if ((cpu_feature & CPUID_HTT) == 0) { 1303 core_bits = 0; 1304 logical_CPU_bits = 0; 1305 goto OUT; 1306 } else { 1307 count = (cpu_procinfo & CPUID_HTT_CORES) 1308 >> CPUID_HTT_CORE_SHIFT; 1309 } 1310 1311 if (cpu_vendor_id == CPU_VENDOR_INTEL) { 1312 detect_intel_topology(count); 1313 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 1314 detect_amd_topology(count); 1315 } 1316 1317 OUT: 1318 if (bootverbose) 1319 kprintf("Bits within APICID: logical_CPU_bits: %d; core_bits: %d\n", 1320 logical_CPU_bits, core_bits); 1321 1322 topology_detected = 1; 1323 } 1324 1325 /* Interface functions to calculate chip_ID, 1326 * core_number and logical_number 1327 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1328 */ 1329 int 1330 get_chip_ID(int cpuid) 1331 { 1332 return get_apicid_from_cpuid(cpuid) >> 1333 (logical_CPU_bits + core_bits); 1334 } 1335 1336 int 1337 get_core_number_within_chip(int cpuid) 1338 { 1339 return (get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) & 1340 ( (1 << core_bits) -1); 1341 } 1342 1343 int 1344 get_logical_CPU_number_within_core(int cpuid) 1345 { 1346 return get_apicid_from_cpuid(cpuid) & 1347 ( (1 << logical_CPU_bits) -1); 1348 } 1349