1 /* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $ 26 */ 27 28 #include "opt_cpu.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/sysctl.h> 34 #include <sys/malloc.h> 35 #include <sys/memrange.h> 36 #include <sys/cons.h> /* cngetc() */ 37 #include <sys/machintr.h> 38 39 #include <sys/mplock2.h> 40 41 #include <vm/vm.h> 42 #include <vm/vm_param.h> 43 #include <vm/pmap.h> 44 #include <vm/vm_kern.h> 45 #include <vm/vm_extern.h> 46 #include <sys/lock.h> 47 #include <vm/vm_map.h> 48 #include <sys/user.h> 49 #ifdef GPROF 50 #include <sys/gmon.h> 51 #endif 52 53 #include <machine/smp.h> 54 #include <machine_base/apic/apicreg.h> 55 #include <machine/atomic.h> 56 #include <machine/cpufunc.h> 57 #include <machine/cputypes.h> 58 #include <machine_base/apic/lapic.h> 59 #include <machine_base/apic/ioapic.h> 60 #include <machine/psl.h> 61 #include <machine/segments.h> 62 #include <machine/tss.h> 63 #include <machine/specialreg.h> 64 #include <machine/globaldata.h> 65 #include <machine/pmap_inval.h> 66 67 #include <machine/md_var.h> /* setidt() */ 68 #include <machine_base/icu/icu.h> /* IPIs */ 69 #include <machine_base/icu/icu_var.h> 70 #include <machine_base/apic/ioapic_abi.h> 71 #include <machine/intr_machdep.h> /* IPIs */ 72 73 #define WARMBOOT_TARGET 0 74 #define WARMBOOT_OFF (KERNBASE + 0x0467) 75 #define WARMBOOT_SEG (KERNBASE + 0x0469) 76 77 #define CMOS_REG (0x70) 78 #define CMOS_DATA (0x71) 79 #define BIOS_RESET (0x0f) 80 #define BIOS_WARM (0x0a) 81 82 /* 83 * this code MUST be enabled here and in mpboot.s. 84 * it follows the very early stages of AP boot by placing values in CMOS ram. 85 * it NORMALLY will never be needed and thus the primitive method for enabling. 86 * 87 */ 88 #if defined(CHECK_POINTS) 89 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 90 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 91 92 #define CHECK_INIT(D); \ 93 CHECK_WRITE(0x34, (D)); \ 94 CHECK_WRITE(0x35, (D)); \ 95 CHECK_WRITE(0x36, (D)); \ 96 CHECK_WRITE(0x37, (D)); \ 97 CHECK_WRITE(0x38, (D)); \ 98 CHECK_WRITE(0x39, (D)); 99 100 #define CHECK_PRINT(S); \ 101 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \ 102 (S), \ 103 CHECK_READ(0x34), \ 104 CHECK_READ(0x35), \ 105 CHECK_READ(0x36), \ 106 CHECK_READ(0x37), \ 107 CHECK_READ(0x38), \ 108 CHECK_READ(0x39)); 109 110 #else /* CHECK_POINTS */ 111 112 #define CHECK_INIT(D) 113 #define CHECK_PRINT(S) 114 115 #endif /* CHECK_POINTS */ 116 117 /* 118 * Values to send to the POST hardware. 119 */ 120 #define MP_BOOTADDRESS_POST 0x10 121 #define MP_PROBE_POST 0x11 122 #define MPTABLE_PASS1_POST 0x12 123 124 #define MP_START_POST 0x13 125 #define MP_ENABLE_POST 0x14 126 #define MPTABLE_PASS2_POST 0x15 127 128 #define START_ALL_APS_POST 0x16 129 #define INSTALL_AP_TRAMP_POST 0x17 130 #define START_AP_POST 0x18 131 132 #define MP_ANNOUNCE_POST 0x19 133 134 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 135 int current_postcode; 136 137 /** XXX FIXME: what system files declare these??? */ 138 extern struct region_descriptor r_gdt; 139 140 extern int nkpt; 141 extern int naps; 142 143 int64_t tsc0_offset; 144 extern int64_t tsc_offsets[]; 145 146 /* AP uses this during bootstrap. Do not staticize. */ 147 char *bootSTK; 148 static int bootAP; 149 150 struct pcb stoppcbs[MAXCPU]; 151 152 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 153 154 /* 155 * Local data and functions. 156 */ 157 158 static u_int boot_address; 159 static int mp_finish; 160 static int mp_finish_lapic; 161 162 static int start_all_aps(u_int boot_addr); 163 #if 0 164 static void install_ap_tramp(u_int boot_addr); 165 #endif 166 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest); 167 static int smitest(void); 168 static void mp_bsp_simple_setup(void); 169 170 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */ 171 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */ 172 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */ 173 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, ""); 174 static u_int bootMP_size; 175 176 /* Local data for detecting CPU TOPOLOGY */ 177 static int core_bits = 0; 178 static int logical_CPU_bits = 0; 179 180 181 /* 182 * Calculate usable address in base memory for AP trampoline code. 183 */ 184 u_int 185 mp_bootaddress(u_int basemem) 186 { 187 POSTCODE(MP_BOOTADDRESS_POST); 188 189 bootMP_size = mptramp_end - mptramp_start; 190 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 191 if (((basemem * 1024) - boot_address) < bootMP_size) 192 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 193 /* 3 levels of page table pages */ 194 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 195 196 return mptramp_pagetables; 197 } 198 199 /* 200 * Print various information about the SMP system hardware and setup. 201 */ 202 void 203 mp_announce(void) 204 { 205 int x; 206 207 POSTCODE(MP_ANNOUNCE_POST); 208 209 kprintf("DragonFly/MP: Multiprocessor motherboard\n"); 210 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0)); 211 for (x = 1; x <= naps; ++x) 212 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x)); 213 214 if (!ioapic_enable) 215 kprintf(" Warning: APIC I/O disabled\n"); 216 } 217 218 /* 219 * AP cpu's call this to sync up protected mode. 220 * 221 * WARNING! %gs is not set up on entry. This routine sets up %gs. 222 */ 223 void 224 init_secondary(void) 225 { 226 int gsel_tss; 227 int x, myid = bootAP; 228 u_int64_t msr, cr0; 229 struct mdglobaldata *md; 230 struct privatespace *ps; 231 232 ps = &CPU_prvspace[myid]; 233 234 gdt_segs[GPROC0_SEL].ssd_base = 235 (long) &ps->mdglobaldata.gd_common_tss; 236 ps->mdglobaldata.mi.gd_prvspace = ps; 237 238 /* We fill the 32-bit segment descriptors */ 239 for (x = 0; x < NGDT; x++) { 240 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 241 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]); 242 } 243 /* And now a 64-bit one */ 244 ssdtosyssd(&gdt_segs[GPROC0_SEL], 245 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]); 246 247 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 248 r_gdt.rd_base = (long) &gdt[myid * NGDT]; 249 lgdt(&r_gdt); /* does magic intra-segment return */ 250 251 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */ 252 wrmsr(MSR_FSBASE, 0); /* User value */ 253 wrmsr(MSR_GSBASE, (u_int64_t)ps); 254 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */ 255 256 lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]); 257 258 #if 0 259 lldt(_default_ldt); 260 mdcpu->gd_currentldt = _default_ldt; 261 #endif 262 263 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 264 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS; 265 266 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/ 267 268 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */ 269 #if 0 /* JG XXX */ 270 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16; 271 #endif 272 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL]; 273 md->gd_common_tssd = *md->gd_tss_gdt; 274 275 /* double fault stack */ 276 md->gd_common_tss.tss_ist1 = 277 (long)&md->mi.gd_prvspace->idlestack[ 278 sizeof(md->mi.gd_prvspace->idlestack)]; 279 280 ltr(gsel_tss); 281 282 /* 283 * Set to a known state: 284 * Set by mpboot.s: CR0_PG, CR0_PE 285 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 286 */ 287 cr0 = rcr0(); 288 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 289 load_cr0(cr0); 290 291 /* Set up the fast syscall stuff */ 292 msr = rdmsr(MSR_EFER) | EFER_SCE; 293 wrmsr(MSR_EFER, msr); 294 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 295 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 296 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 297 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 298 wrmsr(MSR_STAR, msr); 299 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 300 301 pmap_set_opt(); /* PSE/4MB pages, etc */ 302 #if JGXXX 303 /* Initialize the PAT MSR. */ 304 pmap_init_pat(); 305 #endif 306 307 /* set up CPU registers and state */ 308 cpu_setregs(); 309 310 /* set up SSE/NX registers */ 311 initializecpu(); 312 313 /* set up FPU state on the AP */ 314 npxinit(__INITIAL_FPUCW__); 315 316 /* disable the APIC, just to be SURE */ 317 lapic->svr &= ~APIC_SVR_ENABLE; 318 } 319 320 /******************************************************************* 321 * local functions and data 322 */ 323 324 /* 325 * Start the SMP system 326 */ 327 static void 328 mp_start_aps(void *dummy __unused) 329 { 330 if (lapic_enable) { 331 /* start each Application Processor */ 332 start_all_aps(boot_address); 333 } else { 334 mp_bsp_simple_setup(); 335 } 336 } 337 SYSINIT(startaps, SI_BOOT2_START_APS, SI_ORDER_FIRST, mp_start_aps, NULL) 338 339 /* 340 * start each AP in our list 341 */ 342 static int 343 start_all_aps(u_int boot_addr) 344 { 345 vm_offset_t va = boot_address + KERNBASE; 346 u_int64_t *pt4, *pt3, *pt2; 347 int x, i; 348 int shift; 349 int smicount; 350 int smibest; 351 int smilast; 352 u_char mpbiosreason; 353 u_long mpbioswarmvec; 354 struct mdglobaldata *gd; 355 struct privatespace *ps; 356 357 POSTCODE(START_ALL_APS_POST); 358 359 /* install the AP 1st level boot code */ 360 pmap_kenter(va, boot_address); 361 cpu_invlpg((void *)va); /* JG XXX */ 362 bcopy(mptramp_start, (void *)va, bootMP_size); 363 364 /* Locate the page tables, they'll be below the trampoline */ 365 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 366 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 367 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 368 369 /* Create the initial 1GB replicated page tables */ 370 for (i = 0; i < 512; i++) { 371 /* Each slot of the level 4 pages points to the same level 3 page */ 372 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 373 pt4[i] |= PG_V | PG_RW | PG_U; 374 375 /* Each slot of the level 3 pages points to the same level 2 page */ 376 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 377 pt3[i] |= PG_V | PG_RW | PG_U; 378 379 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 380 pt2[i] = i * (2 * 1024 * 1024); 381 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U; 382 } 383 384 /* save the current value of the warm-start vector */ 385 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 386 outb(CMOS_REG, BIOS_RESET); 387 mpbiosreason = inb(CMOS_DATA); 388 389 /* setup a vector to our boot code */ 390 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 391 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 392 outb(CMOS_REG, BIOS_RESET); 393 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 394 395 /* 396 * If we have a TSC we can figure out the SMI interrupt rate. 397 * The SMI does not necessarily use a constant rate. Spend 398 * up to 250ms trying to figure it out. 399 */ 400 smibest = 0; 401 if (cpu_feature & CPUID_TSC) { 402 set_apic_timer(275000); 403 smilast = read_apic_timer(); 404 for (x = 0; x < 20 && read_apic_timer(); ++x) { 405 smicount = smitest(); 406 if (smibest == 0 || smilast - smicount < smibest) 407 smibest = smilast - smicount; 408 smilast = smicount; 409 } 410 if (smibest > 250000) 411 smibest = 0; 412 if (smibest) { 413 smibest = smibest * (int64_t)1000000 / 414 get_apic_timer_frequency(); 415 } 416 } 417 if (smibest) 418 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n", 419 1000000 / smibest, smibest); 420 421 /* start each AP */ 422 for (x = 1; x <= naps; ++x) { 423 424 /* This is a bit verbose, it will go away soon. */ 425 426 /* allocate new private data page(s) */ 427 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map, 428 MDGLOBALDATA_BASEALLOC_SIZE); 429 430 gd = &CPU_prvspace[x].mdglobaldata; /* official location */ 431 bzero(gd, sizeof(*gd)); 432 gd->mi.gd_prvspace = ps = &CPU_prvspace[x]; 433 434 /* prime data page for it to use */ 435 mi_gdinit(&gd->mi, x); 436 cpu_gdinit(gd, x); 437 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (naps + 1)); 438 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (naps + 1)); 439 440 /* setup a vector to our boot code */ 441 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 442 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 443 outb(CMOS_REG, BIOS_RESET); 444 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 445 446 /* 447 * Setup the AP boot stack 448 */ 449 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2]; 450 bootAP = x; 451 452 /* attempt to start the Application Processor */ 453 CHECK_INIT(99); /* setup checkpoints */ 454 if (!start_ap(gd, boot_addr, smibest)) { 455 kprintf("\nAP #%d (PHY# %d) failed!\n", 456 x, CPUID_TO_APICID(x)); 457 CHECK_PRINT("trace"); /* show checkpoints */ 458 /* better panic as the AP may be running loose */ 459 kprintf("panic y/n? [y] "); 460 if (cngetc() != 'n') 461 panic("bye-bye"); 462 } 463 CHECK_PRINT("trace"); /* show checkpoints */ 464 } 465 466 /* set ncpus to 1 + highest logical cpu. Not all may have come up */ 467 ncpus = x; 468 469 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */ 470 for (shift = 0; (1 << shift) <= ncpus; ++shift) 471 ; 472 --shift; 473 ncpus2_shift = shift; 474 ncpus2 = 1 << shift; 475 ncpus2_mask = ncpus2 - 1; 476 477 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */ 478 if ((1 << shift) < ncpus) 479 ++shift; 480 ncpus_fit = 1 << shift; 481 ncpus_fit_mask = ncpus_fit - 1; 482 483 /* build our map of 'other' CPUs */ 484 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 485 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus); 486 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus); 487 488 /* restore the warmstart vector */ 489 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 490 outb(CMOS_REG, BIOS_RESET); 491 outb(CMOS_DATA, mpbiosreason); 492 493 /* 494 * NOTE! The idlestack for the BSP was setup by locore. Finish 495 * up, clean out the P==V mapping we did earlier. 496 */ 497 pmap_set_opt(); 498 499 /* 500 * Wait all APs to finish initializing LAPIC 501 */ 502 mp_finish_lapic = 1; 503 if (bootverbose) 504 kprintf("SMP: Waiting APs LAPIC initialization\n"); 505 if (cpu_feature & CPUID_TSC) 506 tsc0_offset = rdtsc(); 507 tsc_offsets[0] = 0; 508 rel_mplock(); 509 while (smp_lapic_mask != smp_startup_mask) { 510 cpu_lfence(); 511 if (cpu_feature & CPUID_TSC) 512 tsc0_offset = rdtsc(); 513 } 514 while (try_mplock() == 0) 515 ; 516 517 /* number of APs actually started */ 518 return ncpus - 1; 519 } 520 521 522 /* 523 * load the 1st level AP boot code into base memory. 524 */ 525 526 /* targets for relocation */ 527 extern void bigJump(void); 528 extern void bootCodeSeg(void); 529 extern void bootDataSeg(void); 530 extern void MPentry(void); 531 extern u_int MP_GDT; 532 extern u_int mp_gdtbase; 533 534 #if 0 535 536 static void 537 install_ap_tramp(u_int boot_addr) 538 { 539 int x; 540 int size = *(int *) ((u_long) & bootMP_size); 541 u_char *src = (u_char *) ((u_long) bootMP); 542 u_char *dst = (u_char *) boot_addr + KERNBASE; 543 u_int boot_base = (u_int) bootMP; 544 u_int8_t *dst8; 545 u_int16_t *dst16; 546 u_int32_t *dst32; 547 548 POSTCODE(INSTALL_AP_TRAMP_POST); 549 550 for (x = 0; x < size; ++x) 551 *dst++ = *src++; 552 553 /* 554 * modify addresses in code we just moved to basemem. unfortunately we 555 * need fairly detailed info about mpboot.s for this to work. changes 556 * to mpboot.s might require changes here. 557 */ 558 559 /* boot code is located in KERNEL space */ 560 dst = (u_char *) boot_addr + KERNBASE; 561 562 /* modify the lgdt arg */ 563 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 564 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 565 566 /* modify the ljmp target for MPentry() */ 567 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 568 *dst32 = ((u_int) MPentry - KERNBASE); 569 570 /* modify the target for boot code segment */ 571 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 572 dst8 = (u_int8_t *) (dst16 + 1); 573 *dst16 = (u_int) boot_addr & 0xffff; 574 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 575 576 /* modify the target for boot data segment */ 577 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 578 dst8 = (u_int8_t *) (dst16 + 1); 579 *dst16 = (u_int) boot_addr & 0xffff; 580 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 581 } 582 583 #endif 584 585 /* 586 * This function starts the AP (application processor) identified 587 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 588 * to accomplish this. This is necessary because of the nuances 589 * of the different hardware we might encounter. It ain't pretty, 590 * but it seems to work. 591 * 592 * NOTE: eventually an AP gets to ap_init(), which is called just 593 * before the AP goes into the LWKT scheduler's idle loop. 594 */ 595 static int 596 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest) 597 { 598 int physical_cpu; 599 int vector; 600 u_long icr_lo, icr_hi; 601 602 POSTCODE(START_AP_POST); 603 604 /* get the PHYSICAL APIC ID# */ 605 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid); 606 607 /* calculate the vector */ 608 vector = (boot_addr >> 12) & 0xff; 609 610 /* We don't want anything interfering */ 611 cpu_disable_intr(); 612 613 /* Make sure the target cpu sees everything */ 614 wbinvd(); 615 616 /* 617 * Try to detect when a SMI has occurred, wait up to 200ms. 618 * 619 * If a SMI occurs during an AP reset but before we issue 620 * the STARTUP command, the AP may brick. To work around 621 * this problem we hold off doing the AP startup until 622 * after we have detected the SMI. Hopefully another SMI 623 * will not occur before we finish the AP startup. 624 * 625 * Retries don't seem to help. SMIs have a window of opportunity 626 * and if USB->legacy keyboard emulation is enabled in the BIOS 627 * the interrupt rate can be quite high. 628 * 629 * NOTE: Don't worry about the L1 cache load, it might bloat 630 * ldelta a little but ndelta will be so huge when the SMI 631 * occurs the detection logic will still work fine. 632 */ 633 if (smibest) { 634 set_apic_timer(200000); 635 smitest(); 636 } 637 638 /* 639 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 640 * and running the target CPU. OR this INIT IPI might be latched (P5 641 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 642 * ignored. 643 * 644 * see apic/apicreg.h for icr bit definitions. 645 * 646 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH. 647 */ 648 649 /* 650 * Setup the address for the target AP. We can setup 651 * icr_hi once and then just trigger operations with 652 * icr_lo. 653 */ 654 icr_hi = lapic->icr_hi & ~APIC_ID_MASK; 655 icr_hi |= (physical_cpu << 24); 656 icr_lo = lapic->icr_lo & 0xfff00000; 657 lapic->icr_hi = icr_hi; 658 659 /* 660 * Do an INIT IPI: assert RESET 661 * 662 * Use edge triggered mode to assert INIT 663 */ 664 lapic->icr_lo = icr_lo | 0x00004500; 665 while (lapic->icr_lo & APIC_DELSTAT_MASK) 666 /* spin */ ; 667 668 /* 669 * The spec calls for a 10ms delay but we may have to use a 670 * MUCH lower delay to avoid bricking an AP due to a fast SMI 671 * interrupt. We have other loops here too and dividing by 2 672 * doesn't seem to be enough even after subtracting 350us, 673 * so we divide by 4. 674 * 675 * Our minimum delay is 150uS, maximum is 10ms. If no SMI 676 * interrupt was detected we use the full 10ms. 677 */ 678 if (smibest == 0) 679 u_sleep(10000); 680 else if (smibest < 150 * 4 + 350) 681 u_sleep(150); 682 else if ((smibest - 350) / 4 < 10000) 683 u_sleep((smibest - 350) / 4); 684 else 685 u_sleep(10000); 686 687 /* 688 * Do an INIT IPI: deassert RESET 689 * 690 * Use level triggered mode to deassert. It is unclear 691 * why we need to do this. 692 */ 693 lapic->icr_lo = icr_lo | 0x00008500; 694 while (lapic->icr_lo & APIC_DELSTAT_MASK) 695 /* spin */ ; 696 u_sleep(150); /* wait 150us */ 697 698 /* 699 * Next we do a STARTUP IPI: the previous INIT IPI might still be 700 * latched, (P5 bug) this 1st STARTUP would then terminate 701 * immediately, and the previously started INIT IPI would continue. OR 702 * the previous INIT IPI has already run. and this STARTUP IPI will 703 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 704 * will run. 705 */ 706 lapic->icr_lo = icr_lo | 0x00000600 | vector; 707 while (lapic->icr_lo & APIC_DELSTAT_MASK) 708 /* spin */ ; 709 u_sleep(200); /* wait ~200uS */ 710 711 /* 712 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 713 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 714 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 715 * recognized after hardware RESET or INIT IPI. 716 */ 717 lapic->icr_lo = icr_lo | 0x00000600 | vector; 718 while (lapic->icr_lo & APIC_DELSTAT_MASK) 719 /* spin */ ; 720 721 /* Resume normal operation */ 722 cpu_enable_intr(); 723 724 /* wait for it to start, see ap_init() */ 725 set_apic_timer(5000000);/* == 5 seconds */ 726 while (read_apic_timer()) { 727 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid)) 728 return 1; /* return SUCCESS */ 729 } 730 731 return 0; /* return FAILURE */ 732 } 733 734 static 735 int 736 smitest(void) 737 { 738 int64_t ltsc; 739 int64_t ntsc; 740 int64_t ldelta; 741 int64_t ndelta; 742 int count; 743 744 ldelta = 0; 745 ndelta = 0; 746 while (read_apic_timer()) { 747 ltsc = rdtsc(); 748 for (count = 0; count < 100; ++count) 749 ntsc = rdtsc(); /* force loop to occur */ 750 if (ldelta) { 751 ndelta = ntsc - ltsc; 752 if (ldelta > ndelta) 753 ldelta = ndelta; 754 if (ndelta > ldelta * 2) 755 break; 756 } else { 757 ldelta = ntsc - ltsc; 758 } 759 } 760 return(read_apic_timer()); 761 } 762 763 /* 764 * Synchronously flush the TLB on all other CPU's. The current cpu's 765 * TLB is not flushed. If the caller wishes to flush the current cpu's 766 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb(). 767 * 768 * NOTE: If for some reason we were unable to start all cpus we cannot 769 * safely use broadcast IPIs. 770 */ 771 772 static cpumask_t smp_invltlb_req; 773 774 #define SMP_INVLTLB_DEBUG 775 776 void 777 smp_invltlb(void) 778 { 779 struct mdglobaldata *md = mdcpu; 780 #ifdef SMP_INVLTLB_DEBUG 781 long count = 0; 782 long xcount = 0; 783 #endif 784 785 crit_enter_gd(&md->mi); 786 md->gd_invltlb_ret = 0; 787 ++md->mi.gd_cnt.v_smpinvltlb; 788 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask); 789 #ifdef SMP_INVLTLB_DEBUG 790 again: 791 #endif 792 if (smp_startup_mask == smp_active_mask) { 793 all_but_self_ipi(XINVLTLB_OFFSET); 794 } else { 795 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask, 796 XINVLTLB_OFFSET, APIC_DELMODE_FIXED); 797 } 798 799 #ifdef SMP_INVLTLB_DEBUG 800 if (xcount) 801 kprintf("smp_invltlb: ipi sent\n"); 802 #endif 803 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) != 804 (smp_active_mask & ~md->mi.gd_cpumask)) { 805 cpu_mfence(); 806 cpu_pause(); 807 #ifdef SMP_INVLTLB_DEBUG 808 /* DEBUGGING */ 809 if (++count == 400000000) { 810 print_backtrace(-1); 811 kprintf("smp_invltlb: endless loop %08lx %08lx, " 812 "rflags %016jx retry", 813 (long)md->gd_invltlb_ret, 814 (long)smp_invltlb_req, 815 (intmax_t)read_rflags()); 816 __asm __volatile ("sti"); 817 ++xcount; 818 if (xcount > 2) 819 lwkt_process_ipiq(); 820 if (xcount > 3) { 821 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret & 822 ~md->mi.gd_cpumask & 823 smp_active_mask); 824 globaldata_t xgd; 825 826 kprintf("bcpu %d\n", bcpu); 827 xgd = globaldata_find(bcpu); 828 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm); 829 } 830 if (xcount > 5) 831 Debugger("giving up"); 832 count = 0; 833 goto again; 834 } 835 #endif 836 } 837 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask); 838 crit_exit_gd(&md->mi); 839 } 840 841 /* 842 * Called from Xinvltlb assembly with interrupts disabled. We didn't 843 * bother to bump the critical section count or nested interrupt count 844 * so only do very low level operations here. 845 */ 846 void 847 smp_invltlb_intr(void) 848 { 849 struct mdglobaldata *md = mdcpu; 850 struct mdglobaldata *omd; 851 cpumask_t mask; 852 int cpu; 853 854 cpu_mfence(); 855 mask = smp_invltlb_req; 856 cpu_invltlb(); 857 while (mask) { 858 cpu = BSFCPUMASK(mask); 859 mask &= ~CPUMASK(cpu); 860 omd = (struct mdglobaldata *)globaldata_find(cpu); 861 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask); 862 } 863 } 864 865 void 866 cpu_wbinvd_on_all_cpus_callback(void *arg) 867 { 868 wbinvd(); 869 } 870 871 /* 872 * When called the executing CPU will send an IPI to all other CPUs 873 * requesting that they halt execution. 874 * 875 * Usually (but not necessarily) called with 'other_cpus' as its arg. 876 * 877 * - Signals all CPUs in map to stop. 878 * - Waits for each to stop. 879 * 880 * Returns: 881 * -1: error 882 * 0: NA 883 * 1: ok 884 * 885 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 886 * from executing at same time. 887 */ 888 int 889 stop_cpus(cpumask_t map) 890 { 891 map &= smp_active_mask; 892 893 /* send the Xcpustop IPI to all CPUs in map */ 894 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 895 896 while ((stopped_cpus & map) != map) 897 /* spin */ ; 898 899 return 1; 900 } 901 902 903 /* 904 * Called by a CPU to restart stopped CPUs. 905 * 906 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 907 * 908 * - Signals all CPUs in map to restart. 909 * - Waits for each to restart. 910 * 911 * Returns: 912 * -1: error 913 * 0: NA 914 * 1: ok 915 */ 916 int 917 restart_cpus(cpumask_t map) 918 { 919 /* signal other cpus to restart */ 920 started_cpus = map & smp_active_mask; 921 922 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */ 923 /* spin */ ; 924 925 return 1; 926 } 927 928 /* 929 * This is called once the mpboot code has gotten us properly relocated 930 * and the MMU turned on, etc. ap_init() is actually the idle thread, 931 * and when it returns the scheduler will call the real cpu_idle() main 932 * loop for the idlethread. Interrupts are disabled on entry and should 933 * remain disabled at return. 934 */ 935 void 936 ap_init(void) 937 { 938 int cpu_id; 939 940 /* 941 * Adjust smp_startup_mask to signal the BSP that we have started 942 * up successfully. Note that we do not yet hold the BGL. The BSP 943 * is waiting for our signal. 944 * 945 * We can't set our bit in smp_active_mask yet because we are holding 946 * interrupts physically disabled and remote cpus could deadlock 947 * trying to send us an IPI. 948 */ 949 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid); 950 cpu_mfence(); 951 952 /* 953 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is 954 * non-zero, then get the MP lock. 955 * 956 * Note: We are in a critical section. 957 * 958 * Note: we are the idle thread, we can only spin. 959 * 960 * Note: The load fence is memory volatile and prevents the compiler 961 * from improperly caching mp_finish_lapic, and the cpu from improperly 962 * caching it. 963 */ 964 while (mp_finish_lapic == 0) 965 cpu_lfence(); 966 while (try_mplock() == 0) 967 ; 968 969 if (cpu_feature & CPUID_TSC) { 970 /* 971 * The BSP is constantly updating tsc0_offset, figure out 972 * the relative difference to synchronize ktrdump. 973 */ 974 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset; 975 } 976 977 /* BSP may have changed PTD while we're waiting for the lock */ 978 cpu_invltlb(); 979 980 /* Build our map of 'other' CPUs. */ 981 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 982 983 /* A quick check from sanity claus */ 984 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24); 985 if (mycpu->gd_cpuid != cpu_id) { 986 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid); 987 kprintf("SMP: actual cpuid = %d lapicid %d\n", 988 cpu_id, (lapic->id & 0xff000000) >> 24); 989 #if JGXXX 990 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 991 #endif 992 panic("cpuid mismatch! boom!!"); 993 } 994 995 /* Initialize AP's local APIC for irq's */ 996 lapic_init(FALSE); 997 998 /* LAPIC initialization is done */ 999 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid); 1000 cpu_mfence(); 1001 1002 /* Let BSP move onto the next initialization stage */ 1003 rel_mplock(); 1004 1005 /* 1006 * Interlock for finalization. Wait until mp_finish is non-zero, 1007 * then get the MP lock. 1008 * 1009 * Note: We are in a critical section. 1010 * 1011 * Note: we are the idle thread, we can only spin. 1012 * 1013 * Note: The load fence is memory volatile and prevents the compiler 1014 * from improperly caching mp_finish, and the cpu from improperly 1015 * caching it. 1016 */ 1017 while (mp_finish == 0) 1018 cpu_lfence(); 1019 while (try_mplock() == 0) 1020 ; 1021 1022 /* BSP may have changed PTD while we're waiting for the lock */ 1023 cpu_invltlb(); 1024 1025 /* Set memory range attributes for this CPU to match the BSP */ 1026 mem_range_AP_init(); 1027 1028 /* 1029 * Once we go active we must process any IPIQ messages that may 1030 * have been queued, because no actual IPI will occur until we 1031 * set our bit in the smp_active_mask. If we don't the IPI 1032 * message interlock could be left set which would also prevent 1033 * further IPIs. 1034 * 1035 * The idle loop doesn't expect the BGL to be held and while 1036 * lwkt_switch() normally cleans things up this is a special case 1037 * because we returning almost directly into the idle loop. 1038 * 1039 * The idle thread is never placed on the runq, make sure 1040 * nothing we've done put it there. 1041 */ 1042 KKASSERT(get_mplock_count(curthread) == 1); 1043 smp_active_mask |= CPUMASK(mycpu->gd_cpuid); 1044 1045 /* 1046 * Enable interrupts here. idle_restore will also do it, but 1047 * doing it here lets us clean up any strays that got posted to 1048 * the CPU during the AP boot while we are still in a critical 1049 * section. 1050 */ 1051 __asm __volatile("sti; pause; pause"::); 1052 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 1053 1054 initclocks_pcpu(); /* clock interrupts (via IPIs) */ 1055 lwkt_process_ipiq(); 1056 1057 /* 1058 * Releasing the mp lock lets the BSP finish up the SMP init 1059 */ 1060 rel_mplock(); 1061 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0); 1062 } 1063 1064 /* 1065 * Get SMP fully working before we start initializing devices. 1066 */ 1067 static 1068 void 1069 ap_finish(void) 1070 { 1071 mp_finish = 1; 1072 if (bootverbose) 1073 kprintf("Finish MP startup\n"); 1074 rel_mplock(); 1075 while (smp_active_mask != smp_startup_mask) 1076 cpu_lfence(); 1077 while (try_mplock() == 0) 1078 ; 1079 if (bootverbose) { 1080 kprintf("Active CPU Mask: %016jx\n", 1081 (uintmax_t)smp_active_mask); 1082 } 1083 } 1084 1085 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL) 1086 1087 void 1088 cpu_send_ipiq(int dcpu) 1089 { 1090 if (CPUMASK(dcpu) & smp_active_mask) 1091 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED); 1092 } 1093 1094 #if 0 /* single_apic_ipi_passive() not working yet */ 1095 /* 1096 * Returns 0 on failure, 1 on success 1097 */ 1098 int 1099 cpu_send_ipiq_passive(int dcpu) 1100 { 1101 int r = 0; 1102 if (CPUMASK(dcpu) & smp_active_mask) { 1103 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET, 1104 APIC_DELMODE_FIXED); 1105 } 1106 return(r); 1107 } 1108 #endif 1109 1110 static void 1111 mp_bsp_simple_setup(void) 1112 { 1113 /* build our map of 'other' CPUs */ 1114 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid); 1115 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus); 1116 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus); 1117 1118 pmap_set_opt(); 1119 1120 if (cpu_feature & CPUID_TSC) 1121 tsc0_offset = rdtsc(); 1122 } 1123 1124 1125 /* 1126 * CPU TOPOLOGY DETECTION FUNCTIONS 1127 */ 1128 1129 /* Detect intel topology using CPUID 1130 * Ref: http://www.intel.com/Assets/PDF/appnote/241618.pdf, pg 41 1131 */ 1132 static void 1133 detect_intel_topology(int count_htt_cores) 1134 { 1135 int shift = 0; 1136 int ecx_index = 0; 1137 int core_plus_logical_bits = 0; 1138 int cores_per_package; 1139 int logical_per_package; 1140 int logical_per_core; 1141 unsigned int p[4]; 1142 1143 if (cpu_high >= 0xb) { 1144 goto FUNC_B; 1145 1146 } else if (cpu_high >= 0x4) { 1147 goto FUNC_4; 1148 1149 } else { 1150 core_bits = 0; 1151 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1152 ; 1153 logical_CPU_bits = 1 << shift; 1154 return; 1155 } 1156 1157 FUNC_B: 1158 cpuid_count(0xb, FUNC_B_THREAD_LEVEL, p); 1159 1160 /* if 0xb not supported - fallback to 0x4 */ 1161 if (p[1] == 0 || (FUNC_B_TYPE(p[2]) != FUNC_B_THREAD_TYPE)) { 1162 goto FUNC_4; 1163 } 1164 1165 logical_CPU_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1166 1167 ecx_index = FUNC_B_THREAD_LEVEL + 1; 1168 do { 1169 cpuid_count(0xb, ecx_index, p); 1170 1171 /* Check for the Core type in the implemented sub leaves. */ 1172 if (FUNC_B_TYPE(p[2]) == FUNC_B_CORE_TYPE) { 1173 core_plus_logical_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1174 break; 1175 } 1176 1177 ecx_index++; 1178 1179 } while (FUNC_B_TYPE(p[2]) != FUNC_B_INVALID_TYPE); 1180 1181 core_bits = core_plus_logical_bits - logical_CPU_bits; 1182 1183 return; 1184 1185 FUNC_4: 1186 cpuid_count(0x4, 0, p); 1187 cores_per_package = FUNC_4_MAX_CORE_NO(p[0]) + 1; 1188 1189 logical_per_package = count_htt_cores; 1190 logical_per_core = logical_per_package / cores_per_package; 1191 1192 for (shift = 0; (1 << shift) < logical_per_core; ++shift) 1193 ; 1194 logical_CPU_bits = shift; 1195 1196 for (shift = 0; (1 << shift) < cores_per_package; ++shift) 1197 ; 1198 core_bits = shift; 1199 1200 return; 1201 } 1202 1203 /* Detect AMD topology using CPUID 1204 * Ref: http://support.amd.com/us/Embedded_TechDocs/25481.pdf, last page 1205 */ 1206 static void 1207 detect_amd_topology(int count_htt_cores) 1208 { 1209 int shift = 0; 1210 if ((cpu_feature & CPUID_HTT) 1211 && (amd_feature2 & AMDID2_CMP)) { 1212 1213 if (cpu_procinfo2 & AMDID_COREID_SIZE) { 1214 core_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) 1215 >> AMDID_COREID_SIZE_SHIFT; 1216 } else { 1217 core_bits = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 1218 for (shift = 0; (1 << shift) < core_bits; ++shift) 1219 ; 1220 core_bits = shift; 1221 } 1222 1223 logical_CPU_bits = count_htt_cores >> core_bits; 1224 for (shift = 0; (1 << shift) < logical_CPU_bits; ++shift) 1225 ; 1226 logical_CPU_bits = shift; 1227 } else { 1228 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1229 ; 1230 core_bits = shift; 1231 logical_CPU_bits = 0; 1232 } 1233 } 1234 1235 /* Calculate 1236 * - logical_CPU_bits 1237 * - core_bits 1238 * With the values above (for AMD or INTEL) we are able to generally 1239 * detect the CPU topology (number of cores for each level): 1240 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1241 * Ref: http://www.multicoreinfo.com/research/papers/whitepapers/Intel-detect-topology.pdf 1242 */ 1243 void 1244 detect_cpu_topology(void) 1245 { 1246 static int topology_detected = 0; 1247 int count = 0; 1248 1249 if (topology_detected) { 1250 goto OUT; 1251 } 1252 1253 if ((cpu_feature & CPUID_HTT) == 0) { 1254 core_bits = 0; 1255 logical_CPU_bits = 0; 1256 goto OUT; 1257 } else { 1258 count = (cpu_procinfo & CPUID_HTT_CORES) 1259 >> CPUID_HTT_CORE_SHIFT; 1260 } 1261 1262 if (cpu_vendor_id == CPU_VENDOR_INTEL) { 1263 detect_intel_topology(count); 1264 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 1265 detect_amd_topology(count); 1266 } 1267 1268 OUT: 1269 if (bootverbose) 1270 kprintf("Bits within APICID: logical_CPU_bits: %d; core_bits: %d\n", 1271 logical_CPU_bits, core_bits); 1272 1273 topology_detected = 1; 1274 } 1275 1276 /* Interface functions to calculate chip_ID, 1277 * core_number and logical_number 1278 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1279 */ 1280 int 1281 get_chip_ID(int cpuid) 1282 { 1283 return get_apicid_from_cpuid(cpuid) >> 1284 (logical_CPU_bits + core_bits); 1285 } 1286 1287 int 1288 get_core_number_within_chip(int cpuid) 1289 { 1290 return (get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) & 1291 ( (1 << core_bits) -1); 1292 } 1293 1294 int 1295 get_logical_CPU_number_within_core(int cpuid) 1296 { 1297 return get_apicid_from_cpuid(cpuid) & 1298 ( (1 << logical_CPU_bits) -1); 1299 } 1300