1 /* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $ 26 */ 27 28 #include "opt_cpu.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/sysctl.h> 34 #include <sys/malloc.h> 35 #include <sys/memrange.h> 36 #include <sys/cons.h> /* cngetc() */ 37 #include <sys/machintr.h> 38 #include <sys/cpu_topology.h> 39 40 #include <sys/mplock2.h> 41 42 #include <vm/vm.h> 43 #include <vm/vm_param.h> 44 #include <vm/pmap.h> 45 #include <vm/vm_kern.h> 46 #include <vm/vm_extern.h> 47 #include <sys/lock.h> 48 #include <vm/vm_map.h> 49 #include <sys/user.h> 50 #ifdef GPROF 51 #include <sys/gmon.h> 52 #endif 53 54 #include <machine/smp.h> 55 #include <machine_base/apic/apicreg.h> 56 #include <machine/atomic.h> 57 #include <machine/cpufunc.h> 58 #include <machine/cputypes.h> 59 #include <machine_base/apic/lapic.h> 60 #include <machine_base/apic/ioapic.h> 61 #include <machine_base/acpica/acpi_md_cpu.h> 62 #include <machine/psl.h> 63 #include <machine/segments.h> 64 #include <machine/tss.h> 65 #include <machine/specialreg.h> 66 #include <machine/globaldata.h> 67 #include <machine/pmap_inval.h> 68 #include <machine/clock.h> 69 70 #include <machine/md_var.h> /* setidt() */ 71 #include <machine_base/icu/icu.h> /* IPIs */ 72 #include <machine_base/icu/icu_var.h> 73 #include <machine_base/apic/ioapic_abi.h> 74 #include <machine/intr_machdep.h> /* IPIs */ 75 76 #define WARMBOOT_TARGET 0 77 #define WARMBOOT_OFF (KERNBASE + 0x0467) 78 #define WARMBOOT_SEG (KERNBASE + 0x0469) 79 80 #define CMOS_REG (0x70) 81 #define CMOS_DATA (0x71) 82 #define BIOS_RESET (0x0f) 83 #define BIOS_WARM (0x0a) 84 85 /* 86 * this code MUST be enabled here and in mpboot.s. 87 * it follows the very early stages of AP boot by placing values in CMOS ram. 88 * it NORMALLY will never be needed and thus the primitive method for enabling. 89 * 90 */ 91 #if defined(CHECK_POINTS) 92 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 93 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 94 95 #define CHECK_INIT(D); \ 96 CHECK_WRITE(0x34, (D)); \ 97 CHECK_WRITE(0x35, (D)); \ 98 CHECK_WRITE(0x36, (D)); \ 99 CHECK_WRITE(0x37, (D)); \ 100 CHECK_WRITE(0x38, (D)); \ 101 CHECK_WRITE(0x39, (D)); 102 103 #define CHECK_PRINT(S); \ 104 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \ 105 (S), \ 106 CHECK_READ(0x34), \ 107 CHECK_READ(0x35), \ 108 CHECK_READ(0x36), \ 109 CHECK_READ(0x37), \ 110 CHECK_READ(0x38), \ 111 CHECK_READ(0x39)); 112 113 #else /* CHECK_POINTS */ 114 115 #define CHECK_INIT(D) 116 #define CHECK_PRINT(S) 117 118 #endif /* CHECK_POINTS */ 119 120 /* 121 * Values to send to the POST hardware. 122 */ 123 #define MP_BOOTADDRESS_POST 0x10 124 #define MP_PROBE_POST 0x11 125 #define MPTABLE_PASS1_POST 0x12 126 127 #define MP_START_POST 0x13 128 #define MP_ENABLE_POST 0x14 129 #define MPTABLE_PASS2_POST 0x15 130 131 #define START_ALL_APS_POST 0x16 132 #define INSTALL_AP_TRAMP_POST 0x17 133 #define START_AP_POST 0x18 134 135 #define MP_ANNOUNCE_POST 0x19 136 137 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 138 int current_postcode; 139 140 /** XXX FIXME: what system files declare these??? */ 141 extern struct region_descriptor r_gdt; 142 143 extern int nkpt; 144 extern int naps; 145 146 int64_t tsc0_offset; 147 extern int64_t tsc_offsets[]; 148 149 /* AP uses this during bootstrap. Do not staticize. */ 150 char *bootSTK; 151 static int bootAP; 152 153 struct pcb stoppcbs[MAXCPU]; 154 155 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 156 157 /* 158 * Local data and functions. 159 */ 160 161 static u_int boot_address; 162 static int mp_finish; 163 static int mp_finish_lapic; 164 165 static int start_all_aps(u_int boot_addr); 166 #if 0 167 static void install_ap_tramp(u_int boot_addr); 168 #endif 169 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest); 170 static int smitest(void); 171 static void mp_bsp_simple_setup(void); 172 173 /* which cpus have been started */ 174 static cpumask_t smp_startup_mask = CPUMASK_INITIALIZER_ONLYONE; 175 /* which cpus have lapic been inited */ 176 static cpumask_t smp_lapic_mask = CPUMASK_INITIALIZER_ONLYONE; 177 /* which cpus are ready for IPIs etc? */ 178 cpumask_t smp_active_mask = CPUMASK_INITIALIZER_ONLYONE; 179 cpumask_t smp_finalize_mask = CPUMASK_INITIALIZER_ONLYONE; 180 181 SYSCTL_OPAQUE(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, 182 &smp_active_mask, sizeof(smp_active_mask), "LU", ""); 183 static u_int bootMP_size; 184 static u_int report_invlpg_src; 185 SYSCTL_INT(_machdep, OID_AUTO, report_invlpg_src, CTLFLAG_RW, 186 &report_invlpg_src, 0, ""); 187 static u_int report_invltlb_src; 188 SYSCTL_INT(_machdep, OID_AUTO, report_invltlb_src, CTLFLAG_RW, 189 &report_invltlb_src, 0, ""); 190 static int optimized_invltlb; 191 SYSCTL_INT(_machdep, OID_AUTO, optimized_invltlb, CTLFLAG_RW, 192 &optimized_invltlb, 0, ""); 193 static int all_but_self_ipi_enable = 1; 194 SYSCTL_INT(_machdep, OID_AUTO, all_but_self_ipi_enable, CTLFLAG_RW, 195 &all_but_self_ipi_enable, 0, ""); 196 197 /* Local data for detecting CPU TOPOLOGY */ 198 static int core_bits = 0; 199 static int logical_CPU_bits = 0; 200 201 202 /* 203 * Calculate usable address in base memory for AP trampoline code. 204 */ 205 u_int 206 mp_bootaddress(u_int basemem) 207 { 208 POSTCODE(MP_BOOTADDRESS_POST); 209 210 bootMP_size = mptramp_end - mptramp_start; 211 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */ 212 if (((basemem * 1024) - boot_address) < bootMP_size) 213 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 214 /* 3 levels of page table pages */ 215 mptramp_pagetables = boot_address - (PAGE_SIZE * 3); 216 217 return mptramp_pagetables; 218 } 219 220 /* 221 * Print various information about the SMP system hardware and setup. 222 */ 223 void 224 mp_announce(void) 225 { 226 int x; 227 228 POSTCODE(MP_ANNOUNCE_POST); 229 230 kprintf("DragonFly/MP: Multiprocessor motherboard\n"); 231 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0)); 232 for (x = 1; x <= naps; ++x) 233 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x)); 234 235 if (!ioapic_enable) 236 kprintf(" Warning: APIC I/O disabled\n"); 237 } 238 239 /* 240 * AP cpu's call this to sync up protected mode. 241 * 242 * WARNING! %gs is not set up on entry. This routine sets up %gs. 243 */ 244 void 245 init_secondary(void) 246 { 247 int gsel_tss; 248 int x, myid = bootAP; 249 u_int64_t msr, cr0; 250 struct mdglobaldata *md; 251 struct privatespace *ps; 252 253 ps = CPU_prvspace[myid]; 254 255 gdt_segs[GPROC0_SEL].ssd_base = 256 (long) &ps->mdglobaldata.gd_common_tss; 257 ps->mdglobaldata.mi.gd_prvspace = ps; 258 259 /* We fill the 32-bit segment descriptors */ 260 for (x = 0; x < NGDT; x++) { 261 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 262 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]); 263 } 264 /* And now a 64-bit one */ 265 ssdtosyssd(&gdt_segs[GPROC0_SEL], 266 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]); 267 268 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 269 r_gdt.rd_base = (long) &gdt[myid * NGDT]; 270 lgdt(&r_gdt); /* does magic intra-segment return */ 271 272 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */ 273 wrmsr(MSR_FSBASE, 0); /* User value */ 274 wrmsr(MSR_GSBASE, (u_int64_t)ps); 275 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */ 276 277 lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]); 278 279 #if 0 280 lldt(_default_ldt); 281 mdcpu->gd_currentldt = _default_ldt; 282 #endif 283 284 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 285 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS; 286 287 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/ 288 289 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */ 290 #if 0 /* JG XXX */ 291 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16; 292 #endif 293 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL]; 294 md->gd_common_tssd = *md->gd_tss_gdt; 295 296 /* double fault stack */ 297 md->gd_common_tss.tss_ist1 = 298 (long)&md->mi.gd_prvspace->idlestack[ 299 sizeof(md->mi.gd_prvspace->idlestack)]; 300 301 ltr(gsel_tss); 302 303 /* 304 * Set to a known state: 305 * Set by mpboot.s: CR0_PG, CR0_PE 306 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 307 */ 308 cr0 = rcr0(); 309 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 310 load_cr0(cr0); 311 312 /* Set up the fast syscall stuff */ 313 msr = rdmsr(MSR_EFER) | EFER_SCE; 314 wrmsr(MSR_EFER, msr); 315 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 316 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 317 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 318 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 319 wrmsr(MSR_STAR, msr); 320 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL); 321 322 pmap_set_opt(); /* PSE/4MB pages, etc */ 323 pmap_init_pat(); /* Page Attribute Table */ 324 325 /* set up CPU registers and state */ 326 cpu_setregs(); 327 328 /* set up SSE/NX registers */ 329 initializecpu(myid); 330 331 /* set up FPU state on the AP */ 332 npxinit(); 333 334 /* disable the APIC, just to be SURE */ 335 lapic->svr &= ~APIC_SVR_ENABLE; 336 } 337 338 /******************************************************************* 339 * local functions and data 340 */ 341 342 /* 343 * Start the SMP system 344 */ 345 static void 346 mp_start_aps(void *dummy __unused) 347 { 348 if (lapic_enable) { 349 /* start each Application Processor */ 350 start_all_aps(boot_address); 351 } else { 352 mp_bsp_simple_setup(); 353 } 354 } 355 SYSINIT(startaps, SI_BOOT2_START_APS, SI_ORDER_FIRST, mp_start_aps, NULL); 356 357 /* 358 * start each AP in our list 359 */ 360 static int 361 start_all_aps(u_int boot_addr) 362 { 363 vm_offset_t va = boot_address + KERNBASE; 364 u_int64_t *pt4, *pt3, *pt2; 365 int pssize; 366 int x, i; 367 int shift; 368 int smicount; 369 int smibest; 370 int smilast; 371 u_char mpbiosreason; 372 u_long mpbioswarmvec; 373 struct mdglobaldata *gd; 374 struct privatespace *ps; 375 size_t ipiq_size; 376 377 POSTCODE(START_ALL_APS_POST); 378 379 /* install the AP 1st level boot code */ 380 pmap_kenter(va, boot_address); 381 cpu_invlpg((void *)va); /* JG XXX */ 382 bcopy(mptramp_start, (void *)va, bootMP_size); 383 384 /* Locate the page tables, they'll be below the trampoline */ 385 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE); 386 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t); 387 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t); 388 389 /* Create the initial 1GB replicated page tables */ 390 for (i = 0; i < 512; i++) { 391 /* Each slot of the level 4 pages points to the same level 3 page */ 392 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE); 393 pt4[i] |= kernel_pmap.pmap_bits[PG_V_IDX] | 394 kernel_pmap.pmap_bits[PG_RW_IDX] | 395 kernel_pmap.pmap_bits[PG_U_IDX]; 396 397 /* Each slot of the level 3 pages points to the same level 2 page */ 398 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE)); 399 pt3[i] |= kernel_pmap.pmap_bits[PG_V_IDX] | 400 kernel_pmap.pmap_bits[PG_RW_IDX] | 401 kernel_pmap.pmap_bits[PG_U_IDX]; 402 403 /* The level 2 page slots are mapped with 2MB pages for 1GB. */ 404 pt2[i] = i * (2 * 1024 * 1024); 405 pt2[i] |= kernel_pmap.pmap_bits[PG_V_IDX] | 406 kernel_pmap.pmap_bits[PG_RW_IDX] | 407 kernel_pmap.pmap_bits[PG_PS_IDX] | 408 kernel_pmap.pmap_bits[PG_U_IDX]; 409 } 410 411 /* save the current value of the warm-start vector */ 412 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 413 outb(CMOS_REG, BIOS_RESET); 414 mpbiosreason = inb(CMOS_DATA); 415 416 /* setup a vector to our boot code */ 417 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 418 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 419 outb(CMOS_REG, BIOS_RESET); 420 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 421 422 /* 423 * If we have a TSC we can figure out the SMI interrupt rate. 424 * The SMI does not necessarily use a constant rate. Spend 425 * up to 250ms trying to figure it out. 426 */ 427 smibest = 0; 428 if (cpu_feature & CPUID_TSC) { 429 set_apic_timer(275000); 430 smilast = read_apic_timer(); 431 for (x = 0; x < 20 && read_apic_timer(); ++x) { 432 smicount = smitest(); 433 if (smibest == 0 || smilast - smicount < smibest) 434 smibest = smilast - smicount; 435 smilast = smicount; 436 } 437 if (smibest > 250000) 438 smibest = 0; 439 } 440 if (smibest) 441 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n", 442 1000000 / smibest, smibest); 443 444 /* start each AP */ 445 for (x = 1; x <= naps; ++x) { 446 /* This is a bit verbose, it will go away soon. */ 447 448 pssize = sizeof(struct privatespace); 449 ps = (void *)kmem_alloc3(&kernel_map, pssize, VM_SUBSYS_GD, 450 KM_CPU(x)); 451 CPU_prvspace[x] = ps; 452 #if 0 453 kprintf("ps %d %p %d\n", x, ps, pssize); 454 #endif 455 bzero(ps, pssize); 456 gd = &ps->mdglobaldata; 457 gd->mi.gd_prvspace = ps; 458 459 /* prime data page for it to use */ 460 mi_gdinit(&gd->mi, x); 461 cpu_gdinit(gd, x); 462 ipiq_size = sizeof(struct lwkt_ipiq) * (naps + 1); 463 gd->mi.gd_ipiq = (void *)kmem_alloc3(&kernel_map, ipiq_size, 464 VM_SUBSYS_IPIQ, KM_CPU(x)); 465 bzero(gd->mi.gd_ipiq, ipiq_size); 466 467 gd->gd_acpi_id = CPUID_TO_ACPIID(gd->mi.gd_cpuid); 468 469 /* initialize arc4random. */ 470 arc4_init_pcpu(x); 471 472 /* setup a vector to our boot code */ 473 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 474 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 475 outb(CMOS_REG, BIOS_RESET); 476 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 477 478 /* 479 * Setup the AP boot stack 480 */ 481 bootSTK = &ps->idlestack[UPAGES * PAGE_SIZE - PAGE_SIZE]; 482 bootAP = x; 483 484 /* attempt to start the Application Processor */ 485 CHECK_INIT(99); /* setup checkpoints */ 486 if (!start_ap(gd, boot_addr, smibest)) { 487 kprintf("\nAP #%d (PHY# %d) failed!\n", 488 x, CPUID_TO_APICID(x)); 489 CHECK_PRINT("trace"); /* show checkpoints */ 490 /* better panic as the AP may be running loose */ 491 kprintf("panic y/n? [y] "); 492 cnpoll(TRUE); 493 if (cngetc() != 'n') 494 panic("bye-bye"); 495 cnpoll(FALSE); 496 } 497 CHECK_PRINT("trace"); /* show checkpoints */ 498 } 499 500 /* set ncpus to 1 + highest logical cpu. Not all may have come up */ 501 ncpus = x; 502 503 for (shift = 0; (1 << shift) <= ncpus; ++shift) 504 ; 505 --shift; 506 507 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */ 508 if ((1 << shift) < ncpus) 509 ++shift; 510 ncpus_fit = 1 << shift; 511 ncpus_fit_mask = ncpus_fit - 1; 512 513 /* build our map of 'other' CPUs */ 514 mycpu->gd_other_cpus = smp_startup_mask; 515 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid); 516 517 gd = (struct mdglobaldata *)mycpu; 518 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid); 519 520 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus; 521 mycpu->gd_ipiq = (void *)kmem_alloc3(&kernel_map, ipiq_size, 522 VM_SUBSYS_IPIQ, KM_CPU(0)); 523 bzero(mycpu->gd_ipiq, ipiq_size); 524 525 /* initialize arc4random. */ 526 arc4_init_pcpu(0); 527 528 /* restore the warmstart vector */ 529 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 530 outb(CMOS_REG, BIOS_RESET); 531 outb(CMOS_DATA, mpbiosreason); 532 533 /* 534 * NOTE! The idlestack for the BSP was setup by locore. Finish 535 * up, clean out the P==V mapping we did earlier. 536 */ 537 pmap_set_opt(); 538 539 /* 540 * Wait all APs to finish initializing LAPIC 541 */ 542 if (bootverbose) 543 kprintf("SMP: Waiting APs LAPIC initialization\n"); 544 if (cpu_feature & CPUID_TSC) 545 tsc0_offset = rdtsc(); 546 tsc_offsets[0] = 0; 547 mp_finish_lapic = 1; 548 rel_mplock(); 549 550 while (CPUMASK_CMPMASKNEQ(smp_lapic_mask, smp_startup_mask)) { 551 cpu_pause(); 552 cpu_lfence(); 553 if (cpu_feature & CPUID_TSC) 554 tsc0_offset = rdtsc(); 555 } 556 while (try_mplock() == 0) { 557 cpu_pause(); 558 cpu_lfence(); 559 } 560 561 /* number of APs actually started */ 562 return ncpus - 1; 563 } 564 565 566 /* 567 * load the 1st level AP boot code into base memory. 568 */ 569 570 /* targets for relocation */ 571 extern void bigJump(void); 572 extern void bootCodeSeg(void); 573 extern void bootDataSeg(void); 574 extern void MPentry(void); 575 extern u_int MP_GDT; 576 extern u_int mp_gdtbase; 577 578 #if 0 579 580 static void 581 install_ap_tramp(u_int boot_addr) 582 { 583 int x; 584 int size = *(int *) ((u_long) & bootMP_size); 585 u_char *src = (u_char *) ((u_long) bootMP); 586 u_char *dst = (u_char *) boot_addr + KERNBASE; 587 u_int boot_base = (u_int) bootMP; 588 u_int8_t *dst8; 589 u_int16_t *dst16; 590 u_int32_t *dst32; 591 592 POSTCODE(INSTALL_AP_TRAMP_POST); 593 594 for (x = 0; x < size; ++x) 595 *dst++ = *src++; 596 597 /* 598 * modify addresses in code we just moved to basemem. unfortunately we 599 * need fairly detailed info about mpboot.s for this to work. changes 600 * to mpboot.s might require changes here. 601 */ 602 603 /* boot code is located in KERNEL space */ 604 dst = (u_char *) boot_addr + KERNBASE; 605 606 /* modify the lgdt arg */ 607 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 608 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 609 610 /* modify the ljmp target for MPentry() */ 611 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 612 *dst32 = ((u_int) MPentry - KERNBASE); 613 614 /* modify the target for boot code segment */ 615 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 616 dst8 = (u_int8_t *) (dst16 + 1); 617 *dst16 = (u_int) boot_addr & 0xffff; 618 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 619 620 /* modify the target for boot data segment */ 621 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 622 dst8 = (u_int8_t *) (dst16 + 1); 623 *dst16 = (u_int) boot_addr & 0xffff; 624 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 625 } 626 627 #endif 628 629 /* 630 * This function starts the AP (application processor) identified 631 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 632 * to accomplish this. This is necessary because of the nuances 633 * of the different hardware we might encounter. It ain't pretty, 634 * but it seems to work. 635 * 636 * NOTE: eventually an AP gets to ap_init(), which is called just 637 * before the AP goes into the LWKT scheduler's idle loop. 638 */ 639 static int 640 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest) 641 { 642 int physical_cpu; 643 int vector; 644 u_long icr_lo, icr_hi; 645 646 POSTCODE(START_AP_POST); 647 648 /* get the PHYSICAL APIC ID# */ 649 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid); 650 651 /* calculate the vector */ 652 vector = (boot_addr >> 12) & 0xff; 653 654 /* We don't want anything interfering */ 655 cpu_disable_intr(); 656 657 /* Make sure the target cpu sees everything */ 658 wbinvd(); 659 660 /* 661 * Try to detect when a SMI has occurred, wait up to 200ms. 662 * 663 * If a SMI occurs during an AP reset but before we issue 664 * the STARTUP command, the AP may brick. To work around 665 * this problem we hold off doing the AP startup until 666 * after we have detected the SMI. Hopefully another SMI 667 * will not occur before we finish the AP startup. 668 * 669 * Retries don't seem to help. SMIs have a window of opportunity 670 * and if USB->legacy keyboard emulation is enabled in the BIOS 671 * the interrupt rate can be quite high. 672 * 673 * NOTE: Don't worry about the L1 cache load, it might bloat 674 * ldelta a little but ndelta will be so huge when the SMI 675 * occurs the detection logic will still work fine. 676 */ 677 if (smibest) { 678 set_apic_timer(200000); 679 smitest(); 680 } 681 682 /* 683 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 684 * and running the target CPU. OR this INIT IPI might be latched (P5 685 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 686 * ignored. 687 * 688 * see apic/apicreg.h for icr bit definitions. 689 * 690 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH. 691 */ 692 693 /* 694 * Setup the address for the target AP. We can setup 695 * icr_hi once and then just trigger operations with 696 * icr_lo. 697 */ 698 icr_hi = lapic->icr_hi & ~APIC_ID_MASK; 699 icr_hi |= (physical_cpu << 24); 700 icr_lo = lapic->icr_lo & 0xfff00000; 701 lapic->icr_hi = icr_hi; 702 703 /* 704 * Do an INIT IPI: assert RESET 705 * 706 * Use edge triggered mode to assert INIT 707 */ 708 lapic->icr_lo = icr_lo | 0x00004500; 709 while (lapic->icr_lo & APIC_DELSTAT_MASK) 710 /* spin */ ; 711 712 /* 713 * The spec calls for a 10ms delay but we may have to use a 714 * MUCH lower delay to avoid bricking an AP due to a fast SMI 715 * interrupt. We have other loops here too and dividing by 2 716 * doesn't seem to be enough even after subtracting 350us, 717 * so we divide by 4. 718 * 719 * Our minimum delay is 150uS, maximum is 10ms. If no SMI 720 * interrupt was detected we use the full 10ms. 721 */ 722 if (smibest == 0) 723 u_sleep(10000); 724 else if (smibest < 150 * 4 + 350) 725 u_sleep(150); 726 else if ((smibest - 350) / 4 < 10000) 727 u_sleep((smibest - 350) / 4); 728 else 729 u_sleep(10000); 730 731 /* 732 * Do an INIT IPI: deassert RESET 733 * 734 * Use level triggered mode to deassert. It is unclear 735 * why we need to do this. 736 */ 737 lapic->icr_lo = icr_lo | 0x00008500; 738 while (lapic->icr_lo & APIC_DELSTAT_MASK) 739 /* spin */ ; 740 u_sleep(150); /* wait 150us */ 741 742 /* 743 * Next we do a STARTUP IPI: the previous INIT IPI might still be 744 * latched, (P5 bug) this 1st STARTUP would then terminate 745 * immediately, and the previously started INIT IPI would continue. OR 746 * the previous INIT IPI has already run. and this STARTUP IPI will 747 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 748 * will run. 749 */ 750 lapic->icr_lo = icr_lo | 0x00000600 | vector; 751 while (lapic->icr_lo & APIC_DELSTAT_MASK) 752 /* spin */ ; 753 u_sleep(200); /* wait ~200uS */ 754 755 /* 756 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 757 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 758 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 759 * recognized after hardware RESET or INIT IPI. 760 */ 761 lapic->icr_lo = icr_lo | 0x00000600 | vector; 762 while (lapic->icr_lo & APIC_DELSTAT_MASK) 763 /* spin */ ; 764 765 /* Resume normal operation */ 766 cpu_enable_intr(); 767 768 /* wait for it to start, see ap_init() */ 769 set_apic_timer(5000000);/* == 5 seconds */ 770 while (read_apic_timer()) { 771 if (CPUMASK_TESTBIT(smp_startup_mask, gd->mi.gd_cpuid)) 772 return 1; /* return SUCCESS */ 773 } 774 775 return 0; /* return FAILURE */ 776 } 777 778 static 779 int 780 smitest(void) 781 { 782 int64_t ltsc; 783 int64_t ntsc; 784 int64_t ldelta; 785 int64_t ndelta; 786 int count; 787 788 ldelta = 0; 789 ndelta = 0; 790 while (read_apic_timer()) { 791 ltsc = rdtsc(); 792 for (count = 0; count < 100; ++count) 793 ntsc = rdtsc(); /* force loop to occur */ 794 if (ldelta) { 795 ndelta = ntsc - ltsc; 796 if (ldelta > ndelta) 797 ldelta = ndelta; 798 if (ndelta > ldelta * 2) 799 break; 800 } else { 801 ldelta = ntsc - ltsc; 802 } 803 } 804 return(read_apic_timer()); 805 } 806 807 /* 808 * Synchronously flush the TLB on all other CPU's. The current cpu's 809 * TLB is not flushed. If the caller wishes to flush the current cpu's 810 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb(). 811 * 812 * This routine may be called concurrently from multiple cpus. When this 813 * happens, smp_invltlb() can wind up sticking around in the confirmation 814 * while() loop at the end as additional cpus are added to the global 815 * cpumask, until they are acknowledged by another IPI. 816 * 817 * NOTE: If for some reason we were unable to start all cpus we cannot 818 * safely use broadcast IPIs. 819 */ 820 821 cpumask_t smp_smurf_mask; 822 static cpumask_t smp_invltlb_mask; 823 #define LOOPRECOVER 824 #define LOOPMASK_IN 825 #ifdef LOOPMASK_IN 826 cpumask_t smp_in_mask; 827 #endif 828 cpumask_t smp_invmask; 829 extern cpumask_t smp_idleinvl_mask; 830 extern cpumask_t smp_idleinvl_reqs; 831 832 /* 833 * Atomically OR bits in *mask to smp_smurf_mask. Adjust *mask to remove 834 * bits that do not need to be IPId. These bits are still part of the command, 835 * but the target cpus have already been signalled and do not need to be 836 * sigalled again. 837 */ 838 #include <sys/spinlock.h> 839 #include <sys/spinlock2.h> 840 841 static __noinline 842 void 843 smp_smurf_fetchset(cpumask_t *mask) 844 { 845 cpumask_t omask; 846 int i; 847 __uint64_t obits; 848 __uint64_t nbits; 849 850 i = 0; 851 while (i < CPUMASK_ELEMENTS) { 852 obits = smp_smurf_mask.ary[i]; 853 cpu_ccfence(); 854 nbits = obits | mask->ary[i]; 855 if (atomic_cmpset_long(&smp_smurf_mask.ary[i], obits, nbits)) { 856 omask.ary[i] = obits; 857 ++i; 858 } 859 } 860 CPUMASK_NANDMASK(*mask, omask); 861 } 862 863 /* 864 * This is a mechanism which guarantees that cpu_invltlb() will be executed 865 * on idle cpus without having to signal or wake them up. The invltlb will be 866 * executed when they wake up, prior to any scheduling or interrupt thread. 867 * 868 * (*mask) is modified to remove the cpus we successfully negotiate this 869 * function with. This function may only be used with semi-synchronous 870 * commands (typically invltlb's or semi-synchronous invalidations which 871 * are usually associated only with kernel memory). 872 */ 873 void 874 smp_smurf_idleinvlclr(cpumask_t *mask) 875 { 876 if (optimized_invltlb) { 877 ATOMIC_CPUMASK_ORMASK(smp_idleinvl_reqs, *mask); 878 /* cpu_lfence() not needed */ 879 CPUMASK_NANDMASK(*mask, smp_idleinvl_mask); 880 } 881 } 882 883 /* 884 * Issue cpu_invltlb() across all cpus except the current cpu. 885 * 886 * This function will arrange to avoid idle cpus, but still gurantee that 887 * invltlb is run on them when they wake up prior to any scheduling or 888 * nominal interrupt. 889 */ 890 void 891 smp_invltlb(void) 892 { 893 struct mdglobaldata *md = mdcpu; 894 cpumask_t mask; 895 unsigned long rflags; 896 #ifdef LOOPRECOVER 897 tsc_uclock_t tsc_base = rdtsc(); 898 int repeats = 0; 899 #endif 900 901 if (report_invltlb_src > 0) { 902 if (--report_invltlb_src <= 0) 903 print_backtrace(8); 904 } 905 906 /* 907 * Disallow normal interrupts, set all active cpus except our own 908 * in the global smp_invltlb_mask. 909 */ 910 ++md->mi.gd_cnt.v_smpinvltlb; 911 crit_enter_gd(&md->mi); 912 913 /* 914 * Bits we want to set in smp_invltlb_mask. We do not want to signal 915 * our own cpu. Also try to remove bits associated with idle cpus 916 * that we can flag for auto-invltlb. 917 */ 918 mask = smp_active_mask; 919 CPUMASK_NANDBIT(mask, md->mi.gd_cpuid); 920 smp_smurf_idleinvlclr(&mask); 921 922 rflags = read_rflags(); 923 cpu_disable_intr(); 924 ATOMIC_CPUMASK_ORMASK(smp_invltlb_mask, mask); 925 926 /* 927 * IPI non-idle cpus represented by mask. The omask calculation 928 * removes cpus from the mask which already have a Xinvltlb IPI 929 * pending (avoid double-queueing the IPI). 930 * 931 * We must disable real interrupts when setting the smurf flags or 932 * we might race a XINVLTLB before we manage to send the ipi's for 933 * the bits we set. 934 * 935 * NOTE: We are not signalling ourselves, mask already does NOT 936 * include our own cpu. 937 */ 938 smp_smurf_fetchset(&mask); 939 940 /* 941 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of 942 * the critical section count on the target cpus. 943 */ 944 CPUMASK_ORMASK(mask, md->mi.gd_cpumask); 945 if (all_but_self_ipi_enable && 946 (all_but_self_ipi_enable >= 2 || 947 CPUMASK_CMPMASKEQ(smp_startup_mask, mask))) { 948 all_but_self_ipi(XINVLTLB_OFFSET); 949 } else { 950 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask); 951 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED); 952 } 953 954 /* 955 * Wait for acknowledgement by all cpus. smp_inval_intr() will 956 * temporarily enable interrupts to avoid deadlocking the lapic, 957 * and will also handle running cpu_invltlb() and remote invlpg 958 * command son our cpu if some other cpu requests it of us. 959 * 960 * WARNING! I originally tried to implement this as a hard loop 961 * checking only smp_invltlb_mask (and issuing a local 962 * cpu_invltlb() if requested), with interrupts enabled 963 * and without calling smp_inval_intr(). This DID NOT WORK. 964 * It resulted in weird races where smurf bits would get 965 * cleared without any action being taken. 966 */ 967 smp_inval_intr(); 968 CPUMASK_ASSZERO(mask); 969 while (CPUMASK_CMPMASKNEQ(smp_invltlb_mask, mask)) { 970 smp_inval_intr(); 971 cpu_pause(); 972 #ifdef LOOPRECOVER 973 if (tsc_frequency && rdtsc() - tsc_base > tsc_frequency) { 974 /* 975 * cpuid - cpu doing the waiting 976 * invltlb_mask - IPI in progress 977 */ 978 kprintf("smp_invltlb %d: waited too long inv=%08jx " 979 "smurf=%08jx " 980 #ifdef LOOPMASK_IN 981 "in=%08jx " 982 #endif 983 "idle=%08jx/%08jx\n", 984 md->mi.gd_cpuid, 985 smp_invltlb_mask.ary[0], 986 smp_smurf_mask.ary[0], 987 #ifdef LOOPMASK_IN 988 smp_in_mask.ary[0], 989 #endif 990 smp_idleinvl_mask.ary[0], 991 smp_idleinvl_reqs.ary[0]); 992 mdcpu->gd_xinvaltlb = 0; 993 ATOMIC_CPUMASK_NANDMASK(smp_smurf_mask, 994 smp_invltlb_mask); 995 smp_invlpg(&smp_active_mask); 996 tsc_base = rdtsc(); 997 if (++repeats > 10) { 998 kprintf("smp_invltlb: giving up\n"); 999 CPUMASK_ASSZERO(smp_invltlb_mask); 1000 } 1001 } 1002 #endif 1003 } 1004 write_rflags(rflags); 1005 crit_exit_gd(&md->mi); 1006 } 1007 1008 /* 1009 * Called from a critical section with interrupts hard-disabled. 1010 * This function issues an XINVLTLB IPI and then executes any pending 1011 * command on the current cpu before returning. 1012 */ 1013 void 1014 smp_invlpg(cpumask_t *cmdmask) 1015 { 1016 struct mdglobaldata *md = mdcpu; 1017 cpumask_t mask; 1018 1019 if (report_invlpg_src > 0) { 1020 if (--report_invlpg_src <= 0) 1021 print_backtrace(8); 1022 } 1023 1024 /* 1025 * Disallow normal interrupts, set all active cpus in the pmap, 1026 * plus our own for completion processing (it might or might not 1027 * be part of the set). 1028 */ 1029 mask = smp_active_mask; 1030 CPUMASK_ANDMASK(mask, *cmdmask); 1031 CPUMASK_ORMASK(mask, md->mi.gd_cpumask); 1032 1033 /* 1034 * Avoid double-queuing IPIs, which can deadlock us. We must disable 1035 * real interrupts when setting the smurf flags or we might race a 1036 * XINVLTLB before we manage to send the ipi's for the bits we set. 1037 * 1038 * NOTE: We might be including our own cpu in the smurf mask. 1039 */ 1040 smp_smurf_fetchset(&mask); 1041 1042 /* 1043 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of 1044 * the critical section count on the target cpus. 1045 * 1046 * We do not include our own cpu when issuing the IPI. 1047 */ 1048 if (all_but_self_ipi_enable && 1049 (all_but_self_ipi_enable >= 2 || 1050 CPUMASK_CMPMASKEQ(smp_startup_mask, mask))) { 1051 all_but_self_ipi(XINVLTLB_OFFSET); 1052 } else { 1053 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask); 1054 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED); 1055 } 1056 1057 /* 1058 * This will synchronously wait for our command to complete, 1059 * as well as process commands from other cpus. It also handles 1060 * reentrancy. 1061 * 1062 * (interrupts are disabled and we are in a critical section here) 1063 */ 1064 smp_inval_intr(); 1065 } 1066 1067 void 1068 smp_sniff(void) 1069 { 1070 globaldata_t gd = mycpu; 1071 int dummy; 1072 register_t rflags; 1073 1074 /* 1075 * Ignore all_but_self_ipi_enable here and just use it. 1076 */ 1077 rflags = read_rflags(); 1078 cpu_disable_intr(); 1079 all_but_self_ipi(XSNIFF_OFFSET); 1080 gd->gd_sample_pc = smp_sniff; 1081 gd->gd_sample_sp = &dummy; 1082 write_rflags(rflags); 1083 } 1084 1085 void 1086 cpu_sniff(int dcpu) 1087 { 1088 globaldata_t rgd = globaldata_find(dcpu); 1089 register_t rflags; 1090 int dummy; 1091 1092 /* 1093 * Ignore all_but_self_ipi_enable here and just use it. 1094 */ 1095 rflags = read_rflags(); 1096 cpu_disable_intr(); 1097 single_apic_ipi(dcpu, XSNIFF_OFFSET, APIC_DELMODE_FIXED); 1098 rgd->gd_sample_pc = cpu_sniff; 1099 rgd->gd_sample_sp = &dummy; 1100 write_rflags(rflags); 1101 } 1102 1103 /* 1104 * Called from Xinvltlb assembly with interrupts hard-disabled and in a 1105 * critical section. gd_intr_nesting_level may or may not be bumped 1106 * depending on entry. 1107 * 1108 * THIS CODE IS INTENDED TO EXPLICITLY IGNORE THE CRITICAL SECTION COUNT. 1109 * THAT IS, THE INTERRUPT IS INTENDED TO FUNCTION EVEN WHEN MAINLINE CODE 1110 * IS IN A CRITICAL SECTION. 1111 */ 1112 void 1113 smp_inval_intr(void) 1114 { 1115 struct mdglobaldata *md = mdcpu; 1116 cpumask_t cpumask; 1117 #ifdef LOOPRECOVER 1118 tsc_uclock_t tsc_base = rdtsc(); 1119 #endif 1120 1121 #if 0 1122 /* 1123 * The idle code is in a critical section, but that doesn't stop 1124 * Xinvltlb from executing, so deal with the race which can occur 1125 * in that situation. Otherwise r-m-w operations by pmap_inval_intr() 1126 * may have problems. 1127 */ 1128 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, md->mi.gd_cpuid)) { 1129 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask, md->mi.gd_cpuid); 1130 cpu_invltlb(); 1131 cpu_mfence(); 1132 } 1133 #endif 1134 1135 /* 1136 * This is a real mess. I'd like to just leave interrupts disabled 1137 * but it can cause the lapic to deadlock if too many interrupts queue 1138 * to it, due to the idiotic design of the lapic. So instead we have 1139 * to enter a critical section so normal interrupts are made pending 1140 * and track whether this one was reentered. 1141 */ 1142 if (md->gd_xinvaltlb) { /* reentrant on cpu */ 1143 md->gd_xinvaltlb = 2; 1144 return; 1145 } 1146 md->gd_xinvaltlb = 1; 1147 1148 /* 1149 * Check only those cpus with active Xinvl* commands pending. 1150 * 1151 * We are going to enable interrupts so make sure we are in a 1152 * critical section. This is necessary to avoid deadlocking 1153 * the lapic and to ensure that we execute our commands prior to 1154 * any nominal interrupt or preemption. 1155 * 1156 * WARNING! It is very important that we only clear out but in 1157 * smp_smurf_mask once for each interrupt we take. In 1158 * this case, we clear it on initial entry and only loop 1159 * on the reentrancy detect (caused by another interrupt). 1160 */ 1161 cpumask = smp_invmask; 1162 #ifdef LOOPMASK_IN 1163 ATOMIC_CPUMASK_ORBIT(smp_in_mask, md->mi.gd_cpuid); 1164 #endif 1165 loop: 1166 cpu_enable_intr(); 1167 ATOMIC_CPUMASK_NANDBIT(smp_smurf_mask, md->mi.gd_cpuid); 1168 1169 /* 1170 * Specific page request(s), and we can't return until all bits 1171 * are zero. 1172 */ 1173 for (;;) { 1174 int toolong; 1175 1176 /* 1177 * Also execute any pending full invalidation request in 1178 * this loop. 1179 */ 1180 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) { 1181 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask, 1182 md->mi.gd_cpuid); 1183 cpu_invltlb(); 1184 cpu_mfence(); 1185 } 1186 1187 #ifdef LOOPRECOVER 1188 if (tsc_frequency && rdtsc() - tsc_base > tsc_frequency) { 1189 /* 1190 * cpuid - cpu doing the waiting 1191 * invmask - IPI in progress 1192 * invltlb_mask - which ones are TLB invalidations? 1193 */ 1194 kprintf("smp_inval_intr %d inv=%08jx tlbm=%08jx " 1195 "smurf=%08jx " 1196 #ifdef LOOPMASK_IN 1197 "in=%08jx " 1198 #endif 1199 "idle=%08jx/%08jx\n", 1200 md->mi.gd_cpuid, 1201 smp_invmask.ary[0], 1202 smp_invltlb_mask.ary[0], 1203 smp_smurf_mask.ary[0], 1204 #ifdef LOOPMASK_IN 1205 smp_in_mask.ary[0], 1206 #endif 1207 smp_idleinvl_mask.ary[0], 1208 smp_idleinvl_reqs.ary[0]); 1209 tsc_base = rdtsc(); 1210 toolong = 1; 1211 } else { 1212 toolong = 0; 1213 } 1214 #else 1215 toolong = 0; 1216 #endif 1217 1218 /* 1219 * We can only add bits to the cpumask to test during the 1220 * loop because the smp_invmask bit is cleared once the 1221 * originator completes the command (the targets may still 1222 * be cycling their own completions in this loop, afterwords). 1223 * 1224 * lfence required prior to all tests as this Xinvltlb 1225 * interrupt could race the originator (already be in progress 1226 * wnen the originator decides to issue, due to an issue by 1227 * another cpu). 1228 */ 1229 cpu_lfence(); 1230 CPUMASK_ORMASK(cpumask, smp_invmask); 1231 /*cpumask = smp_active_mask;*/ /* XXX */ 1232 cpu_lfence(); 1233 1234 if (pmap_inval_intr(&cpumask, toolong) == 0) { 1235 /* 1236 * Clear our smurf mask to allow new IPIs, but deal 1237 * with potential races. 1238 */ 1239 break; 1240 } 1241 1242 /* 1243 * Test if someone sent us another invalidation IPI, break 1244 * out so we can take it to avoid deadlocking the lapic 1245 * interrupt queue (? stupid intel, amd). 1246 */ 1247 if (md->gd_xinvaltlb == 2) 1248 break; 1249 /* 1250 if (CPUMASK_TESTBIT(smp_smurf_mask, md->mi.gd_cpuid)) 1251 break; 1252 */ 1253 } 1254 1255 /* 1256 * Full invalidation request 1257 */ 1258 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) { 1259 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask, 1260 md->mi.gd_cpuid); 1261 cpu_invltlb(); 1262 cpu_mfence(); 1263 } 1264 1265 /* 1266 * Check to see if another Xinvltlb interrupt occurred and loop up 1267 * if it did. 1268 */ 1269 cpu_disable_intr(); 1270 if (md->gd_xinvaltlb == 2) { 1271 md->gd_xinvaltlb = 1; 1272 goto loop; 1273 } 1274 #ifdef LOOPMASK_IN 1275 ATOMIC_CPUMASK_NANDBIT(smp_in_mask, md->mi.gd_cpuid); 1276 #endif 1277 md->gd_xinvaltlb = 0; 1278 } 1279 1280 void 1281 cpu_wbinvd_on_all_cpus_callback(void *arg) 1282 { 1283 wbinvd(); 1284 } 1285 1286 /* 1287 * When called the executing CPU will send an IPI to all other CPUs 1288 * requesting that they halt execution. 1289 * 1290 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1291 * 1292 * - Signals all CPUs in map to stop. 1293 * - Waits for each to stop. 1294 * 1295 * Returns: 1296 * -1: error 1297 * 0: NA 1298 * 1: ok 1299 * 1300 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1301 * from executing at same time. 1302 */ 1303 int 1304 stop_cpus(cpumask_t map) 1305 { 1306 cpumask_t mask; 1307 1308 CPUMASK_ANDMASK(map, smp_active_mask); 1309 1310 /* send the Xcpustop IPI to all CPUs in map */ 1311 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1312 1313 do { 1314 mask = stopped_cpus; 1315 CPUMASK_ANDMASK(mask, map); 1316 /* spin */ 1317 } while (CPUMASK_CMPMASKNEQ(mask, map)); 1318 1319 return 1; 1320 } 1321 1322 1323 /* 1324 * Called by a CPU to restart stopped CPUs. 1325 * 1326 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1327 * 1328 * - Signals all CPUs in map to restart. 1329 * - Waits for each to restart. 1330 * 1331 * Returns: 1332 * -1: error 1333 * 0: NA 1334 * 1: ok 1335 */ 1336 int 1337 restart_cpus(cpumask_t map) 1338 { 1339 cpumask_t mask; 1340 1341 /* signal other cpus to restart */ 1342 mask = map; 1343 CPUMASK_ANDMASK(mask, smp_active_mask); 1344 cpu_ccfence(); 1345 started_cpus = mask; 1346 cpu_ccfence(); 1347 1348 /* wait for each to clear its bit */ 1349 while (CPUMASK_CMPMASKNEQ(stopped_cpus, map)) 1350 cpu_pause(); 1351 1352 return 1; 1353 } 1354 1355 /* 1356 * This is called once the mpboot code has gotten us properly relocated 1357 * and the MMU turned on, etc. ap_init() is actually the idle thread, 1358 * and when it returns the scheduler will call the real cpu_idle() main 1359 * loop for the idlethread. Interrupts are disabled on entry and should 1360 * remain disabled at return. 1361 */ 1362 void 1363 ap_init(void) 1364 { 1365 int cpu_id; 1366 1367 /* 1368 * Adjust smp_startup_mask to signal the BSP that we have started 1369 * up successfully. Note that we do not yet hold the BGL. The BSP 1370 * is waiting for our signal. 1371 * 1372 * We can't set our bit in smp_active_mask yet because we are holding 1373 * interrupts physically disabled and remote cpus could deadlock 1374 * trying to send us an IPI. 1375 */ 1376 ATOMIC_CPUMASK_ORBIT(smp_startup_mask, mycpu->gd_cpuid); 1377 cpu_mfence(); 1378 1379 /* 1380 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is 1381 * non-zero, then get the MP lock. 1382 * 1383 * Note: We are in a critical section. 1384 * 1385 * Note: we are the idle thread, we can only spin. 1386 * 1387 * Note: The load fence is memory volatile and prevents the compiler 1388 * from improperly caching mp_finish_lapic, and the cpu from improperly 1389 * caching it. 1390 */ 1391 while (mp_finish_lapic == 0) { 1392 cpu_pause(); 1393 cpu_lfence(); 1394 } 1395 #if 0 1396 while (try_mplock() == 0) { 1397 cpu_pause(); 1398 cpu_lfence(); 1399 } 1400 #endif 1401 1402 if (cpu_feature & CPUID_TSC) { 1403 /* 1404 * The BSP is constantly updating tsc0_offset, figure out 1405 * the relative difference to synchronize ktrdump. 1406 */ 1407 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset; 1408 } 1409 1410 /* BSP may have changed PTD while we're waiting for the lock */ 1411 cpu_invltlb(); 1412 1413 /* Build our map of 'other' CPUs. */ 1414 mycpu->gd_other_cpus = smp_startup_mask; 1415 ATOMIC_CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid); 1416 1417 /* A quick check from sanity claus */ 1418 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24); 1419 if (mycpu->gd_cpuid != cpu_id) { 1420 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid); 1421 kprintf("SMP: actual cpuid = %d lapicid %d\n", 1422 cpu_id, (lapic->id & 0xff000000) >> 24); 1423 #if 0 /* JGXXX */ 1424 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]); 1425 #endif 1426 panic("cpuid mismatch! boom!!"); 1427 } 1428 1429 /* Initialize AP's local APIC for irq's */ 1430 lapic_init(FALSE); 1431 1432 /* LAPIC initialization is done */ 1433 ATOMIC_CPUMASK_ORBIT(smp_lapic_mask, mycpu->gd_cpuid); 1434 cpu_mfence(); 1435 1436 #if 0 1437 /* Let BSP move onto the next initialization stage */ 1438 rel_mplock(); 1439 #endif 1440 1441 /* 1442 * Interlock for finalization. Wait until mp_finish is non-zero, 1443 * then get the MP lock. 1444 * 1445 * Note: We are in a critical section. 1446 * 1447 * Note: we are the idle thread, we can only spin. 1448 * 1449 * Note: The load fence is memory volatile and prevents the compiler 1450 * from improperly caching mp_finish, and the cpu from improperly 1451 * caching it. 1452 */ 1453 while (mp_finish == 0) { 1454 cpu_pause(); 1455 cpu_lfence(); 1456 } 1457 1458 /* BSP may have changed PTD while we're waiting for the lock */ 1459 cpu_invltlb(); 1460 1461 /* Set memory range attributes for this CPU to match the BSP */ 1462 mem_range_AP_init(); 1463 1464 /* 1465 * Once we go active we must process any IPIQ messages that may 1466 * have been queued, because no actual IPI will occur until we 1467 * set our bit in the smp_active_mask. If we don't the IPI 1468 * message interlock could be left set which would also prevent 1469 * further IPIs. 1470 * 1471 * The idle loop doesn't expect the BGL to be held and while 1472 * lwkt_switch() normally cleans things up this is a special case 1473 * because we returning almost directly into the idle loop. 1474 * 1475 * The idle thread is never placed on the runq, make sure 1476 * nothing we've done put it there. 1477 */ 1478 1479 /* 1480 * Hold a critical section and allow real interrupts to occur. Zero 1481 * any spurious interrupts which have accumulated, then set our 1482 * smp_active_mask indicating that we are fully operational. 1483 */ 1484 crit_enter(); 1485 __asm __volatile("sti; pause; pause"::); 1486 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); 1487 ATOMIC_CPUMASK_ORBIT(smp_active_mask, mycpu->gd_cpuid); 1488 1489 /* 1490 * Wait until all cpus have set their smp_active_mask and have fully 1491 * operational interrupts before proceeding. 1492 * 1493 * We need a final cpu_invltlb() because we would not have received 1494 * any until we set our bit in smp_active_mask. 1495 */ 1496 while (mp_finish == 1) { 1497 cpu_pause(); 1498 cpu_lfence(); 1499 } 1500 cpu_invltlb(); 1501 1502 /* 1503 * Initialize per-cpu clocks and do other per-cpu initialization. 1504 * At this point code is expected to be able to use the full kernel 1505 * API. 1506 */ 1507 initclocks_pcpu(); /* clock interrupts (via IPIs) */ 1508 1509 /* 1510 * Since we may have cleaned up the interrupt triggers, manually 1511 * process any pending IPIs before exiting our critical section. 1512 * Once the critical section has exited, normal interrupt processing 1513 * may occur. 1514 */ 1515 atomic_swap_int(&mycpu->gd_npoll, 0); 1516 lwkt_process_ipiq(); 1517 crit_exit(); 1518 1519 /* 1520 * Final final, allow the waiting BSP to resume the boot process, 1521 * return 'into' the idle thread bootstrap. 1522 */ 1523 ATOMIC_CPUMASK_ORBIT(smp_finalize_mask, mycpu->gd_cpuid); 1524 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0); 1525 } 1526 1527 /* 1528 * Get SMP fully working before we start initializing devices. 1529 */ 1530 static 1531 void 1532 ap_finish(void) 1533 { 1534 if (bootverbose) 1535 kprintf("Finish MP startup\n"); 1536 rel_mplock(); 1537 1538 /* 1539 * Wait for the active mask to complete, after which all cpus will 1540 * be accepting interrupts. 1541 */ 1542 mp_finish = 1; 1543 while (CPUMASK_CMPMASKNEQ(smp_active_mask, smp_startup_mask)) { 1544 cpu_pause(); 1545 cpu_lfence(); 1546 } 1547 1548 /* 1549 * Wait for the finalization mask to complete, after which all cpus 1550 * have completely finished initializing and are entering or are in 1551 * their idle thread. 1552 * 1553 * BSP should have received all required invltlbs but do another 1554 * one just in case. 1555 */ 1556 cpu_invltlb(); 1557 mp_finish = 2; 1558 while (CPUMASK_CMPMASKNEQ(smp_finalize_mask, smp_startup_mask)) { 1559 cpu_pause(); 1560 cpu_lfence(); 1561 } 1562 1563 while (try_mplock() == 0) { 1564 cpu_pause(); 1565 cpu_lfence(); 1566 } 1567 1568 if (bootverbose) { 1569 kprintf("Active CPU Mask: %016jx\n", 1570 (uintmax_t)CPUMASK_LOWMASK(smp_active_mask)); 1571 } 1572 } 1573 1574 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL); 1575 1576 /* 1577 * Interrupts must be hard-disabled by caller 1578 */ 1579 void 1580 cpu_send_ipiq(int dcpu) 1581 { 1582 if (CPUMASK_TESTBIT(smp_active_mask, dcpu)) 1583 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED); 1584 } 1585 1586 #if 0 /* single_apic_ipi_passive() not working yet */ 1587 /* 1588 * Returns 0 on failure, 1 on success 1589 */ 1590 int 1591 cpu_send_ipiq_passive(int dcpu) 1592 { 1593 int r = 0; 1594 if (CPUMASK_TESTBIT(smp_active_mask, dcpu)) { 1595 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET, 1596 APIC_DELMODE_FIXED); 1597 } 1598 return(r); 1599 } 1600 #endif 1601 1602 static void 1603 mp_bsp_simple_setup(void) 1604 { 1605 struct mdglobaldata *gd; 1606 size_t ipiq_size; 1607 1608 /* build our map of 'other' CPUs */ 1609 mycpu->gd_other_cpus = smp_startup_mask; 1610 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid); 1611 1612 gd = (struct mdglobaldata *)mycpu; 1613 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid); 1614 1615 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus; 1616 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size, 1617 VM_SUBSYS_IPIQ); 1618 bzero(mycpu->gd_ipiq, ipiq_size); 1619 1620 /* initialize arc4random. */ 1621 arc4_init_pcpu(0); 1622 1623 pmap_set_opt(); 1624 1625 if (cpu_feature & CPUID_TSC) 1626 tsc0_offset = rdtsc(); 1627 } 1628 1629 1630 /* 1631 * CPU TOPOLOGY DETECTION FUNCTIONS 1632 */ 1633 1634 /* Detect intel topology using CPUID 1635 * Ref: http://www.intel.com/Assets/PDF/appnote/241618.pdf, pg 41 1636 */ 1637 static void 1638 detect_intel_topology(int count_htt_cores) 1639 { 1640 int shift = 0; 1641 int ecx_index = 0; 1642 int core_plus_logical_bits = 0; 1643 int cores_per_package; 1644 int logical_per_package; 1645 int logical_per_core; 1646 unsigned int p[4]; 1647 1648 if (cpu_high >= 0xb) { 1649 goto FUNC_B; 1650 1651 } else if (cpu_high >= 0x4) { 1652 goto FUNC_4; 1653 1654 } else { 1655 core_bits = 0; 1656 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1657 ; 1658 logical_CPU_bits = 1 << shift; 1659 return; 1660 } 1661 1662 FUNC_B: 1663 cpuid_count(0xb, FUNC_B_THREAD_LEVEL, p); 1664 1665 /* if 0xb not supported - fallback to 0x4 */ 1666 if (p[1] == 0 || (FUNC_B_TYPE(p[2]) != FUNC_B_THREAD_TYPE)) { 1667 goto FUNC_4; 1668 } 1669 1670 logical_CPU_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1671 1672 ecx_index = FUNC_B_THREAD_LEVEL + 1; 1673 do { 1674 cpuid_count(0xb, ecx_index, p); 1675 1676 /* Check for the Core type in the implemented sub leaves. */ 1677 if (FUNC_B_TYPE(p[2]) == FUNC_B_CORE_TYPE) { 1678 core_plus_logical_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]); 1679 break; 1680 } 1681 1682 ecx_index++; 1683 1684 } while (FUNC_B_TYPE(p[2]) != FUNC_B_INVALID_TYPE); 1685 1686 core_bits = core_plus_logical_bits - logical_CPU_bits; 1687 1688 return; 1689 1690 FUNC_4: 1691 cpuid_count(0x4, 0, p); 1692 cores_per_package = FUNC_4_MAX_CORE_NO(p[0]) + 1; 1693 1694 logical_per_package = count_htt_cores; 1695 logical_per_core = logical_per_package / cores_per_package; 1696 1697 for (shift = 0; (1 << shift) < logical_per_core; ++shift) 1698 ; 1699 logical_CPU_bits = shift; 1700 1701 for (shift = 0; (1 << shift) < cores_per_package; ++shift) 1702 ; 1703 core_bits = shift; 1704 1705 return; 1706 } 1707 1708 /* Detect AMD topology using CPUID 1709 * Ref: http://support.amd.com/us/Embedded_TechDocs/25481.pdf, last page 1710 */ 1711 static void 1712 detect_amd_topology(int count_htt_cores) 1713 { 1714 int shift = 0; 1715 if ((cpu_feature & CPUID_HTT) && (amd_feature2 & AMDID2_CMP)) { 1716 if (cpu_procinfo2 & AMDID_COREID_SIZE) { 1717 core_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >> 1718 AMDID_COREID_SIZE_SHIFT; 1719 } else { 1720 core_bits = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 1721 for (shift = 0; (1 << shift) < core_bits; ++shift) 1722 ; 1723 core_bits = shift; 1724 } 1725 1726 if (amd_feature2 & AMDID2_TOPOEXT) { 1727 u_int p[4]; 1728 int i; 1729 int type; 1730 int level; 1731 int share_count; 1732 for (i = 0; i < 256; ++i) { 1733 cpuid_count(0x8000001d, i, p); 1734 type = p[0] & 0x1f; 1735 level = (p[0] >> 5) & 0x7; 1736 share_count = 1 + ((p[0] >> 14) & 0xfff); 1737 1738 if (type == 0) 1739 break; 1740 if (bootverbose) 1741 kprintf("Topology probe i=%2d type=%d level=%d share_count=%d\n", 1742 i, type, level, share_count); 1743 if (type == 1 && share_count) { /* CPUID_TYPE_SMT */ 1744 for (shift = 0; (1 << shift) < count_htt_cores / share_count; ++shift) 1745 ; 1746 core_bits = shift; 1747 break; 1748 } 1749 } 1750 } 1751 1752 logical_CPU_bits = count_htt_cores >> core_bits; 1753 for (shift = 0; (1 << shift) < logical_CPU_bits; ++shift) 1754 ; 1755 logical_CPU_bits = shift; 1756 } else { 1757 for (shift = 0; (1 << shift) < count_htt_cores; ++shift) 1758 ; 1759 core_bits = shift; 1760 logical_CPU_bits = 0; 1761 } 1762 } 1763 1764 static void 1765 amd_get_compute_unit_id(void *arg) 1766 { 1767 u_int regs[4]; 1768 1769 do_cpuid(0x8000001e, regs); 1770 cpu_node_t * mynode = get_cpu_node_by_cpuid(mycpuid); 1771 1772 /* 1773 * AMD - CPUID Specification September 2010 1774 * page 34 - //ComputeUnitID = ebx[0:7]// 1775 */ 1776 mynode->compute_unit_id = regs[1] & 0xff; 1777 } 1778 1779 int 1780 fix_amd_topology(void) 1781 { 1782 cpumask_t mask; 1783 1784 if (cpu_vendor_id != CPU_VENDOR_AMD) 1785 return -1; 1786 if ((amd_feature2 & AMDID2_TOPOEXT) == 0) 1787 return -1; 1788 1789 CPUMASK_ASSALLONES(mask); 1790 lwkt_cpusync_simple(mask, amd_get_compute_unit_id, NULL); 1791 1792 kprintf("Compute unit iDS:\n"); 1793 int i; 1794 for (i = 0; i < ncpus; i++) { 1795 kprintf("%d-%d; \n", 1796 i, get_cpu_node_by_cpuid(i)->compute_unit_id); 1797 } 1798 return 0; 1799 } 1800 1801 /* 1802 * Calculate 1803 * - logical_CPU_bits 1804 * - core_bits 1805 * With the values above (for AMD or INTEL) we are able to generally 1806 * detect the CPU topology (number of cores for each level): 1807 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1808 * Ref: http://www.multicoreinfo.com/research/papers/whitepapers/Intel-detect-topology.pdf 1809 */ 1810 void 1811 detect_cpu_topology(void) 1812 { 1813 static int topology_detected = 0; 1814 int count = 0; 1815 1816 if (topology_detected) 1817 goto OUT; 1818 if ((cpu_feature & CPUID_HTT) == 0) { 1819 core_bits = 0; 1820 logical_CPU_bits = 0; 1821 goto OUT; 1822 } 1823 count = (cpu_procinfo & CPUID_HTT_CORES) >> CPUID_HTT_CORE_SHIFT; 1824 1825 if (cpu_vendor_id == CPU_VENDOR_INTEL) 1826 detect_intel_topology(count); 1827 else if (cpu_vendor_id == CPU_VENDOR_AMD) 1828 detect_amd_topology(count); 1829 topology_detected = 1; 1830 1831 OUT: 1832 if (bootverbose) { 1833 kprintf("Bits within APICID: logical_CPU_bits: %d; " 1834 "core_bits: %d\n", 1835 logical_CPU_bits, core_bits); 1836 } 1837 } 1838 1839 /* 1840 * Interface functions to calculate chip_ID, 1841 * core_number and logical_number 1842 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86) 1843 */ 1844 int 1845 get_chip_ID(int cpuid) 1846 { 1847 return get_apicid_from_cpuid(cpuid) >> 1848 (logical_CPU_bits + core_bits); 1849 } 1850 1851 int 1852 get_chip_ID_from_APICID(int apicid) 1853 { 1854 return apicid >> (logical_CPU_bits + core_bits); 1855 } 1856 1857 int 1858 get_core_number_within_chip(int cpuid) 1859 { 1860 return ((get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) & 1861 ((1 << core_bits) - 1)); 1862 } 1863 1864 int 1865 get_logical_CPU_number_within_core(int cpuid) 1866 { 1867 return (get_apicid_from_cpuid(cpuid) & 1868 ((1 << logical_CPU_bits) - 1)); 1869 } 1870