1 /* 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * Copyright (c) 2006 The DragonFly Project. 5 * Copyright (c) 2006 Matthew Dillon. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 36 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 37 */ 38 39 #include "opt_debug_npx.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/sysctl.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #ifdef NPX_DEBUG 51 #include <sys/syslog.h> 52 #endif 53 #include <sys/signalvar.h> 54 55 #include <sys/thread2.h> 56 #include <sys/mplock2.h> 57 58 #include <machine/cputypes.h> 59 #include <machine/frame.h> 60 #include <machine/md_var.h> 61 #include <machine/pcb.h> 62 #include <machine/psl.h> 63 #include <machine/specialreg.h> 64 #include <machine/segments.h> 65 #include <machine/globaldata.h> 66 67 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 68 #define fnclex() __asm("fnclex") 69 #define fninit() __asm("fninit") 70 #define fnop() __asm("fnop") 71 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 72 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 73 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 74 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 75 #ifndef CPU_DISABLE_SSE 76 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 77 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 78 #endif 79 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 80 : : "n" (CR0_TS) : "ax") 81 #define stop_emulating() __asm("clts") 82 83 typedef u_char bool_t; 84 #ifndef CPU_DISABLE_SSE 85 static void fpu_clean_state(void); 86 #endif 87 88 static struct krate badfprate = { 1 }; 89 90 static void fpusave (union savefpu *); 91 static void fpurstor (union savefpu *); 92 93 /* 94 * Initialize the floating point unit. 95 */ 96 void 97 npxinit(u_short control) 98 { 99 static union savefpu dummy __aligned(16); 100 101 /* 102 * fninit has the same h/w bugs as fnsave. Use the detoxified 103 * fnsave to throw away any junk in the fpu. npxsave() initializes 104 * the fpu and sets npxthread = NULL as important side effects. 105 */ 106 npxsave(&dummy); 107 crit_enter(); 108 stop_emulating(); 109 fldcw(&control); 110 fpusave(curthread->td_savefpu); 111 mdcpu->gd_npxthread = NULL; 112 start_emulating(); 113 crit_exit(); 114 } 115 116 /* 117 * Free coprocessor (if we have it). 118 */ 119 void 120 npxexit(void) 121 { 122 if (curthread == mdcpu->gd_npxthread) 123 npxsave(curthread->td_savefpu); 124 } 125 126 #if 0 127 /* 128 * The following mechanism is used to ensure that the FPE_... value 129 * that is passed as a trapcode to the signal handler of the user 130 * process does not have more than one bit set. 131 * 132 * Multiple bits may be set if the user process modifies the control 133 * word while a status word bit is already set. While this is a sign 134 * of bad coding, we have no choise than to narrow them down to one 135 * bit, since we must not send a trapcode that is not exactly one of 136 * the FPE_ macros. 137 * 138 * The mechanism has a static table with 127 entries. Each combination 139 * of the 7 FPU status word exception bits directly translates to a 140 * position in this table, where a single FPE_... value is stored. 141 * This FPE_... value stored there is considered the "most important" 142 * of the exception bits and will be sent as the signal code. The 143 * precedence of the bits is based upon Intel Document "Numerical 144 * Applications", Chapter "Special Computational Situations". 145 * 146 * The macro to choose one of these values does these steps: 1) Throw 147 * away status word bits that cannot be masked. 2) Throw away the bits 148 * currently masked in the control word, assuming the user isn't 149 * interested in them anymore. 3) Reinsert status word bit 7 (stack 150 * fault) if it is set, which cannot be masked but must be presered. 151 * 4) Use the remaining bits to point into the trapcode table. 152 * 153 * The 6 maskable bits in order of their preference, as stated in the 154 * above referenced Intel manual: 155 * 1 Invalid operation (FP_X_INV) 156 * 1a Stack underflow 157 * 1b Stack overflow 158 * 1c Operand of unsupported format 159 * 1d SNaN operand. 160 * 2 QNaN operand (not an exception, irrelavant here) 161 * 3 Any other invalid-operation not mentioned above or zero divide 162 * (FP_X_INV, FP_X_DZ) 163 * 4 Denormal operand (FP_X_DNML) 164 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 165 * 6 Inexact result (FP_X_IMP) 166 */ 167 static char fpetable[128] = { 168 0, 169 FPE_FLTINV, /* 1 - INV */ 170 FPE_FLTUND, /* 2 - DNML */ 171 FPE_FLTINV, /* 3 - INV | DNML */ 172 FPE_FLTDIV, /* 4 - DZ */ 173 FPE_FLTINV, /* 5 - INV | DZ */ 174 FPE_FLTDIV, /* 6 - DNML | DZ */ 175 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 176 FPE_FLTOVF, /* 8 - OFL */ 177 FPE_FLTINV, /* 9 - INV | OFL */ 178 FPE_FLTUND, /* A - DNML | OFL */ 179 FPE_FLTINV, /* B - INV | DNML | OFL */ 180 FPE_FLTDIV, /* C - DZ | OFL */ 181 FPE_FLTINV, /* D - INV | DZ | OFL */ 182 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 183 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 184 FPE_FLTUND, /* 10 - UFL */ 185 FPE_FLTINV, /* 11 - INV | UFL */ 186 FPE_FLTUND, /* 12 - DNML | UFL */ 187 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 188 FPE_FLTDIV, /* 14 - DZ | UFL */ 189 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 190 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 191 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 192 FPE_FLTOVF, /* 18 - OFL | UFL */ 193 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 194 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 195 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 196 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 197 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 198 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 199 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 200 FPE_FLTRES, /* 20 - IMP */ 201 FPE_FLTINV, /* 21 - INV | IMP */ 202 FPE_FLTUND, /* 22 - DNML | IMP */ 203 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 204 FPE_FLTDIV, /* 24 - DZ | IMP */ 205 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 206 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 207 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 208 FPE_FLTOVF, /* 28 - OFL | IMP */ 209 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 210 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 211 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 212 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 213 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 214 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 215 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 216 FPE_FLTUND, /* 30 - UFL | IMP */ 217 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 218 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 219 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 220 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 221 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 222 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 223 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 224 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 225 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 226 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 227 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 228 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 229 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 230 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 231 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 232 FPE_FLTSUB, /* 40 - STK */ 233 FPE_FLTSUB, /* 41 - INV | STK */ 234 FPE_FLTUND, /* 42 - DNML | STK */ 235 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 236 FPE_FLTDIV, /* 44 - DZ | STK */ 237 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 238 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 239 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 240 FPE_FLTOVF, /* 48 - OFL | STK */ 241 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 242 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 243 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 244 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 245 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 246 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 247 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 248 FPE_FLTUND, /* 50 - UFL | STK */ 249 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 250 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 251 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 252 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 253 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 254 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 255 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 256 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 257 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 258 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 259 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 260 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 261 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 262 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 263 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 264 FPE_FLTRES, /* 60 - IMP | STK */ 265 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 266 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 267 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 268 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 269 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 270 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 271 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 272 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 273 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 274 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 275 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 276 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 277 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 278 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 279 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 280 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 281 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 282 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 283 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 284 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 285 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 286 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 287 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 288 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 289 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 290 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 291 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 292 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 293 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 294 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 295 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 296 }; 297 298 #endif 299 300 /* 301 * Implement the device not available (DNA) exception. gd_npxthread had 302 * better be NULL. Restore the current thread's FP state and set gd_npxthread 303 * to curthread. 304 * 305 * Interrupts are enabled and preemption can occur. Enter a critical 306 * section to stabilize the FP state. 307 */ 308 int 309 npxdna(void) 310 { 311 thread_t td = curthread; 312 int didinit = 0; 313 314 if (mdcpu->gd_npxthread != NULL) { 315 kprintf("npxdna: npxthread = %p, curthread = %p\n", 316 mdcpu->gd_npxthread, curthread); 317 panic("npxdna"); 318 } 319 320 /* 321 * Setup the initial saved state if the thread has never before 322 * used the FP unit. This also occurs when a thread pushes a 323 * signal handler and uses FP in the handler. 324 */ 325 crit_enter(); 326 if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) { 327 td->td_flags |= TDF_USINGFP; 328 npxinit(__INITIAL_FPUCW__); 329 didinit = 1; 330 } 331 332 /* 333 * The setting of gd_npxthread and the call to fpurstor() must not 334 * be preempted by an interrupt thread or we will take an npxdna 335 * trap and potentially save our current fpstate (which is garbage) 336 * and then restore the garbage rather then the originally saved 337 * fpstate. 338 */ 339 stop_emulating(); 340 /* 341 * Record new context early in case frstor causes an IRQ13. 342 */ 343 mdcpu->gd_npxthread = td; 344 /* 345 * The following frstor may cause an IRQ13 when the state being 346 * restored has a pending error. The error will appear to have been 347 * triggered by the current (npx) user instruction even when that 348 * instruction is a no-wait instruction that should not trigger an 349 * error (e.g., fnclex). On at least one 486 system all of the 350 * no-wait instructions are broken the same as frstor, so our 351 * treatment does not amplify the breakage. On at least one 352 * 386/Cyrix 387 system, fnclex works correctly while frstor and 353 * fnsave are broken, so our treatment breaks fnclex if it is the 354 * first FPU instruction after a context switch. 355 */ 356 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) 357 #ifndef CPU_DISABLE_SSE 358 && cpu_fxsr 359 #endif 360 ) { 361 krateprintf(&badfprate, 362 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n", 363 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit); 364 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 365 lwpsignal(curproc, curthread->td_lwp, SIGFPE); 366 } 367 fpurstor(td->td_savefpu); 368 crit_exit(); 369 370 return (1); 371 } 372 373 /* 374 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 375 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 376 * any IRQ13 to be handled immediately, and then ignore it. This routine is 377 * often called at splhigh so it must not use many system services. In 378 * particular, it's much easier to install a special handler than to 379 * guarantee that it's safe to use npxintr() and its supporting code. 380 * 381 * WARNING! This call is made during a switch and the MP lock will be 382 * setup for the new target thread rather then the current thread, so we 383 * cannot do anything here that depends on the *_mplock() functions as 384 * we may trip over their assertions. 385 * 386 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 387 * kernel will always assume that the FP state is 'safe' (will not cause 388 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 389 * setup a custom save area before actually using the FP unit, but it will 390 * not bother calling fninit. This greatly improves kernel performance when 391 * it wishes to use the FP unit. 392 */ 393 void 394 npxsave(union savefpu *addr) 395 { 396 crit_enter(); 397 stop_emulating(); 398 fpusave(addr); 399 mdcpu->gd_npxthread = NULL; 400 fninit(); 401 start_emulating(); 402 crit_exit(); 403 } 404 405 static void 406 fpusave(union savefpu *addr) 407 { 408 #ifndef CPU_DISABLE_SSE 409 if (cpu_fxsr) 410 fxsave(addr); 411 else 412 #endif 413 fnsave(addr); 414 } 415 416 /* 417 * Save the FP state to the mcontext structure. 418 * 419 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 420 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 421 */ 422 void 423 npxpush(mcontext_t *mctx) 424 { 425 thread_t td = curthread; 426 427 KKASSERT((td->td_flags & TDF_KERNELFP) == 0); 428 429 if (td->td_flags & TDF_USINGFP) { 430 if (mdcpu->gd_npxthread == td) { 431 /* 432 * XXX Note: This is a bit inefficient if the signal 433 * handler uses floating point, extra faults will 434 * occur. 435 */ 436 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 437 npxsave(td->td_savefpu); 438 } else { 439 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 440 } 441 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs)); 442 td->td_flags &= ~TDF_USINGFP; 443 mctx->mc_fpformat = 444 #ifndef CPU_DISABLE_SSE 445 (cpu_fxsr) ? _MC_FPFMT_XMM : 446 #endif 447 _MC_FPFMT_387; 448 } else { 449 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 450 mctx->mc_fpformat = _MC_FPFMT_NODEV; 451 } 452 } 453 454 /* 455 * Restore the FP state from the mcontext structure. 456 */ 457 void 458 npxpop(mcontext_t *mctx) 459 { 460 thread_t td = curthread; 461 462 switch(mctx->mc_ownedfp) { 463 case _MC_FPOWNED_NONE: 464 /* 465 * If the signal handler used the FP unit but the interrupted 466 * code did not, release the FP unit. Clear TDF_USINGFP will 467 * force the FP unit to reinit so the interrupted code sees 468 * a clean slate. 469 */ 470 if (td->td_flags & TDF_USINGFP) { 471 if (td == mdcpu->gd_npxthread) 472 npxsave(td->td_savefpu); 473 td->td_flags &= ~TDF_USINGFP; 474 } 475 break; 476 case _MC_FPOWNED_FPU: 477 case _MC_FPOWNED_PCB: 478 /* 479 * Clear ownership of the FP unit and restore our saved state. 480 * 481 * NOTE: The signal handler may have set-up some FP state and 482 * enabled the FP unit, so we have to restore no matter what. 483 * 484 * XXX: This is bit inefficient, if the code being returned 485 * to is actively using the FP this results in multiple 486 * kernel faults. 487 * 488 * WARNING: The saved state was exposed to userland and may 489 * have to be sanitized to avoid a GP fault in the kernel. 490 */ 491 if (td == mdcpu->gd_npxthread) 492 npxsave(td->td_savefpu); 493 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 494 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) 495 #ifndef CPU_DISABLE_SSE 496 && cpu_fxsr 497 #endif 498 ) { 499 krateprintf(&badfprate, 500 "pid %d (%s) signal return from user: " 501 "illegal FP MXCSR %08x\n", 502 td->td_proc->p_pid, 503 td->td_proc->p_comm, 504 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 505 } 506 td->td_flags |= TDF_USINGFP; 507 break; 508 } 509 } 510 511 512 #ifndef CPU_DISABLE_SSE 513 /* 514 * On AuthenticAMD processors, the fxrstor instruction does not restore 515 * the x87's stored last instruction pointer, last data pointer, and last 516 * opcode values, except in the rare case in which the exception summary 517 * (ES) bit in the x87 status word is set to 1. 518 * 519 * In order to avoid leaking this information across processes, we clean 520 * these values by performing a dummy load before executing fxrstor(). 521 */ 522 static double dummy_variable = 0.0; 523 static void 524 fpu_clean_state(void) 525 { 526 u_short status; 527 528 /* 529 * Clear the ES bit in the x87 status word if it is currently 530 * set, in order to avoid causing a fault in the upcoming load. 531 */ 532 fnstsw(&status); 533 if (status & 0x80) 534 fnclex(); 535 536 /* 537 * Load the dummy variable into the x87 stack. This mangles 538 * the x87 stack, but we don't care since we're about to call 539 * fxrstor() anyway. 540 */ 541 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 542 } 543 #endif /* CPU_DISABLE_SSE */ 544 545 static void 546 fpurstor(union savefpu *addr) 547 { 548 #ifndef CPU_DISABLE_SSE 549 if (cpu_fxsr) { 550 fpu_clean_state(); 551 fxrstor(addr); 552 } else { 553 frstor(addr); 554 } 555 #else 556 frstor(addr); 557 #endif 558 } 559 560