1 /* 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * Copyright (c) 2006 The DragonFly Project. 5 * Copyright (c) 2006 Matthew Dillon. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 36 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 37 */ 38 39 #include "opt_cpu.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/sysctl.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/signalvar.h> 51 52 #include <sys/thread2.h> 53 #include <sys/mplock2.h> 54 55 #include <machine/cputypes.h> 56 #include <machine/frame.h> 57 #include <machine/md_var.h> 58 #include <machine/pcb.h> 59 #include <machine/psl.h> 60 #include <machine/specialreg.h> 61 #include <machine/segments.h> 62 #include <machine/globaldata.h> 63 64 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 65 #define fnclex() __asm("fnclex") 66 #define fninit() __asm("fninit") 67 #define fnop() __asm("fnop") 68 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 69 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 70 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 71 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 72 #ifndef CPU_DISABLE_SSE 73 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 74 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 75 #endif 76 #ifndef CPU_DISABLE_AVX 77 #define xrstor(eax,edx,addr) __asm __volatile(".byte 0x0f,0xae,0x2f" : : "D" (addr), "a" (eax), "d" (edx)) 78 #define xsave(eax,edx,addr) __asm __volatile(".byte 0x0f,0xae,0x27" : : "D" (addr), "a" (eax), "d" (edx) : "memory") 79 #endif 80 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 81 : : "n" (CR0_TS) : "ax") 82 #define stop_emulating() __asm("clts") 83 84 typedef u_char bool_t; 85 #ifndef CPU_DISABLE_SSE 86 static void fpu_clean_state(void); 87 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 88 #endif 89 90 static struct krate badfprate = { 1 }; 91 92 static void fpusave (union savefpu *); 93 static void fpurstor (union savefpu *); 94 95 /* 96 * Initialize the floating point unit. 97 */ 98 void 99 npxinit(u_short control) 100 { 101 /*64-Byte alignment required for xsave*/ 102 static union savefpu dummy __aligned(64); 103 u_int mxcsr; 104 105 /* 106 * fninit has the same h/w bugs as fnsave. Use the detoxified 107 * fnsave to throw away any junk in the fpu. npxsave() initializes 108 * the fpu and sets npxthread = NULL as important side effects. 109 */ 110 npxsave(&dummy); 111 crit_enter(); 112 stop_emulating(); 113 fldcw(&control); 114 115 mxcsr = __INITIAL_MXCSR__; 116 ldmxcsr(mxcsr); 117 118 fpusave(curthread->td_savefpu); 119 mdcpu->gd_npxthread = NULL; 120 start_emulating(); 121 crit_exit(); 122 } 123 124 /* 125 * Free coprocessor (if we have it). 126 */ 127 void 128 npxexit(void) 129 { 130 if (curthread == mdcpu->gd_npxthread) 131 npxsave(curthread->td_savefpu); 132 } 133 134 #if 0 135 /* 136 * The following mechanism is used to ensure that the FPE_... value 137 * that is passed as a trapcode to the signal handler of the user 138 * process does not have more than one bit set. 139 * 140 * Multiple bits may be set if the user process modifies the control 141 * word while a status word bit is already set. While this is a sign 142 * of bad coding, we have no choise than to narrow them down to one 143 * bit, since we must not send a trapcode that is not exactly one of 144 * the FPE_ macros. 145 * 146 * The mechanism has a static table with 127 entries. Each combination 147 * of the 7 FPU status word exception bits directly translates to a 148 * position in this table, where a single FPE_... value is stored. 149 * This FPE_... value stored there is considered the "most important" 150 * of the exception bits and will be sent as the signal code. The 151 * precedence of the bits is based upon Intel Document "Numerical 152 * Applications", Chapter "Special Computational Situations". 153 * 154 * The macro to choose one of these values does these steps: 1) Throw 155 * away status word bits that cannot be masked. 2) Throw away the bits 156 * currently masked in the control word, assuming the user isn't 157 * interested in them anymore. 3) Reinsert status word bit 7 (stack 158 * fault) if it is set, which cannot be masked but must be presered. 159 * 4) Use the remaining bits to point into the trapcode table. 160 * 161 * The 6 maskable bits in order of their preference, as stated in the 162 * above referenced Intel manual: 163 * 1 Invalid operation (FP_X_INV) 164 * 1a Stack underflow 165 * 1b Stack overflow 166 * 1c Operand of unsupported format 167 * 1d SNaN operand. 168 * 2 QNaN operand (not an exception, irrelavant here) 169 * 3 Any other invalid-operation not mentioned above or zero divide 170 * (FP_X_INV, FP_X_DZ) 171 * 4 Denormal operand (FP_X_DNML) 172 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 173 * 6 Inexact result (FP_X_IMP) 174 */ 175 static char fpetable[128] = { 176 0, 177 FPE_FLTINV, /* 1 - INV */ 178 FPE_FLTUND, /* 2 - DNML */ 179 FPE_FLTINV, /* 3 - INV | DNML */ 180 FPE_FLTDIV, /* 4 - DZ */ 181 FPE_FLTINV, /* 5 - INV | DZ */ 182 FPE_FLTDIV, /* 6 - DNML | DZ */ 183 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 184 FPE_FLTOVF, /* 8 - OFL */ 185 FPE_FLTINV, /* 9 - INV | OFL */ 186 FPE_FLTUND, /* A - DNML | OFL */ 187 FPE_FLTINV, /* B - INV | DNML | OFL */ 188 FPE_FLTDIV, /* C - DZ | OFL */ 189 FPE_FLTINV, /* D - INV | DZ | OFL */ 190 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 191 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 192 FPE_FLTUND, /* 10 - UFL */ 193 FPE_FLTINV, /* 11 - INV | UFL */ 194 FPE_FLTUND, /* 12 - DNML | UFL */ 195 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 196 FPE_FLTDIV, /* 14 - DZ | UFL */ 197 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 198 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 199 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 200 FPE_FLTOVF, /* 18 - OFL | UFL */ 201 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 202 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 203 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 204 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 205 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 206 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 207 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 208 FPE_FLTRES, /* 20 - IMP */ 209 FPE_FLTINV, /* 21 - INV | IMP */ 210 FPE_FLTUND, /* 22 - DNML | IMP */ 211 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 212 FPE_FLTDIV, /* 24 - DZ | IMP */ 213 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 214 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 215 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 216 FPE_FLTOVF, /* 28 - OFL | IMP */ 217 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 218 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 219 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 220 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 221 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 222 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 223 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 224 FPE_FLTUND, /* 30 - UFL | IMP */ 225 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 226 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 227 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 228 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 229 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 230 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 231 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 232 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 233 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 234 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 235 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 236 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 237 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 238 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 239 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 240 FPE_FLTSUB, /* 40 - STK */ 241 FPE_FLTSUB, /* 41 - INV | STK */ 242 FPE_FLTUND, /* 42 - DNML | STK */ 243 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 244 FPE_FLTDIV, /* 44 - DZ | STK */ 245 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 246 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 247 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 248 FPE_FLTOVF, /* 48 - OFL | STK */ 249 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 250 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 251 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 252 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 253 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 254 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 255 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 256 FPE_FLTUND, /* 50 - UFL | STK */ 257 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 258 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 259 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 260 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 261 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 262 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 263 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 264 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 265 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 266 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 267 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 268 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 269 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 270 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 271 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 272 FPE_FLTRES, /* 60 - IMP | STK */ 273 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 274 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 275 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 276 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 277 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 278 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 279 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 280 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 281 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 282 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 283 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 284 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 285 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 286 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 287 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 288 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 289 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 290 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 291 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 292 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 293 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 294 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 295 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 296 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 297 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 298 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 299 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 300 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 301 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 302 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 303 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 304 }; 305 306 #endif 307 308 /* 309 * Implement the device not available (DNA) exception. gd_npxthread had 310 * better be NULL. Restore the current thread's FP state and set gd_npxthread 311 * to curthread. 312 * 313 * Interrupts are enabled and preemption can occur. Enter a critical 314 * section to stabilize the FP state. 315 */ 316 int 317 npxdna(void) 318 { 319 thread_t td = curthread; 320 int didinit = 0; 321 322 if (mdcpu->gd_npxthread != NULL) { 323 kprintf("npxdna: npxthread = %p, curthread = %p\n", 324 mdcpu->gd_npxthread, curthread); 325 panic("npxdna"); 326 } 327 328 /* 329 * Setup the initial saved state if the thread has never before 330 * used the FP unit. This also occurs when a thread pushes a 331 * signal handler and uses FP in the handler. 332 */ 333 crit_enter(); 334 if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) { 335 td->td_flags |= TDF_USINGFP; 336 npxinit(__INITIAL_FPUCW__); 337 didinit = 1; 338 } 339 340 /* 341 * The setting of gd_npxthread and the call to fpurstor() must not 342 * be preempted by an interrupt thread or we will take an npxdna 343 * trap and potentially save our current fpstate (which is garbage) 344 * and then restore the garbage rather then the originally saved 345 * fpstate. 346 */ 347 stop_emulating(); 348 /* 349 * Record new context early in case frstor causes an IRQ13. 350 */ 351 mdcpu->gd_npxthread = td; 352 /* 353 * The following frstor may cause an IRQ13 when the state being 354 * restored has a pending error. The error will appear to have been 355 * triggered by the current (npx) user instruction even when that 356 * instruction is a no-wait instruction that should not trigger an 357 * error (e.g., fnclex). On at least one 486 system all of the 358 * no-wait instructions are broken the same as frstor, so our 359 * treatment does not amplify the breakage. On at least one 360 * 386/Cyrix 387 system, fnclex works correctly while frstor and 361 * fnsave are broken, so our treatment breaks fnclex if it is the 362 * first FPU instruction after a context switch. 363 */ 364 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) 365 #ifndef CPU_DISABLE_SSE 366 && cpu_fxsr 367 #endif 368 ) { 369 krateprintf(&badfprate, 370 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n", 371 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit); 372 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 373 lwpsignal(curproc, curthread->td_lwp, SIGFPE); 374 } 375 fpurstor(td->td_savefpu); 376 crit_exit(); 377 378 return (1); 379 } 380 381 /* 382 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 383 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 384 * any IRQ13 to be handled immediately, and then ignore it. This routine is 385 * often called at splhigh so it must not use many system services. In 386 * particular, it's much easier to install a special handler than to 387 * guarantee that it's safe to use npxintr() and its supporting code. 388 * 389 * WARNING! This call is made during a switch and the MP lock will be 390 * setup for the new target thread rather then the current thread, so we 391 * cannot do anything here that depends on the *_mplock() functions as 392 * we may trip over their assertions. 393 * 394 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 395 * kernel will always assume that the FP state is 'safe' (will not cause 396 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 397 * setup a custom save area before actually using the FP unit, but it will 398 * not bother calling fninit. This greatly improves kernel performance when 399 * it wishes to use the FP unit. 400 */ 401 void 402 npxsave(union savefpu *addr) 403 { 404 crit_enter(); 405 stop_emulating(); 406 fpusave(addr); 407 mdcpu->gd_npxthread = NULL; 408 fninit(); 409 start_emulating(); 410 crit_exit(); 411 } 412 413 static void 414 fpusave(union savefpu *addr) 415 { 416 #ifndef CPU_DISABLE_AVX 417 if (cpu_xsave) 418 xsave(CPU_XFEATURE_X87 | CPU_XFEATURE_SSE | CPU_XFEATURE_YMM, 0, addr); 419 else 420 #endif 421 #ifndef CPU_DISABLE_SSE 422 if (cpu_fxsr) 423 fxsave(addr); 424 else 425 #endif 426 fnsave(addr); 427 } 428 429 /* 430 * Save the FP state to the mcontext structure. 431 * 432 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 433 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 434 */ 435 void 436 npxpush(mcontext_t *mctx) 437 { 438 thread_t td = curthread; 439 440 KKASSERT((td->td_flags & TDF_KERNELFP) == 0); 441 442 if (td->td_flags & TDF_USINGFP) { 443 if (mdcpu->gd_npxthread == td) { 444 /* 445 * XXX Note: This is a bit inefficient if the signal 446 * handler uses floating point, extra faults will 447 * occur. 448 */ 449 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 450 npxsave(td->td_savefpu); 451 } else { 452 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 453 } 454 KKASSERT(sizeof(*td->td_savefpu) <= sizeof(mctx->mc_fpregs)); 455 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(*td->td_savefpu)); 456 td->td_flags &= ~TDF_USINGFP; 457 #ifndef CPU_DISABLE_AVX 458 if (cpu_xsave) 459 mctx->mc_fpformat = _MC_FPFMT_YMM; 460 else 461 #endif 462 #ifndef CPU_DISABLE_SSE 463 if (cpu_fxsr) 464 mctx->mc_fpformat = _MC_FPFMT_XMM; 465 else 466 #endif 467 mctx->mc_fpformat = _MC_FPFMT_387; 468 } else { 469 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 470 mctx->mc_fpformat = _MC_FPFMT_NODEV; 471 } 472 } 473 474 /* 475 * Restore the FP state from the mcontext structure. 476 */ 477 void 478 npxpop(mcontext_t *mctx) 479 { 480 thread_t td = curthread; 481 482 switch(mctx->mc_ownedfp) { 483 case _MC_FPOWNED_NONE: 484 /* 485 * If the signal handler used the FP unit but the interrupted 486 * code did not, release the FP unit. Clear TDF_USINGFP will 487 * force the FP unit to reinit so the interrupted code sees 488 * a clean slate. 489 */ 490 if (td->td_flags & TDF_USINGFP) { 491 if (td == mdcpu->gd_npxthread) 492 npxsave(td->td_savefpu); 493 td->td_flags &= ~TDF_USINGFP; 494 } 495 break; 496 case _MC_FPOWNED_FPU: 497 case _MC_FPOWNED_PCB: 498 /* 499 * Clear ownership of the FP unit and restore our saved state. 500 * 501 * NOTE: The signal handler may have set-up some FP state and 502 * enabled the FP unit, so we have to restore no matter what. 503 * 504 * XXX: This is bit inefficient, if the code being returned 505 * to is actively using the FP this results in multiple 506 * kernel faults. 507 * 508 * WARNING: The saved state was exposed to userland and may 509 * have to be sanitized to avoid a GP fault in the kernel. 510 */ 511 if (td == mdcpu->gd_npxthread) 512 npxsave(td->td_savefpu); 513 KKASSERT(sizeof(*td->td_savefpu) <= sizeof(mctx->mc_fpregs)); 514 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 515 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) 516 #ifndef CPU_DISABLE_SSE 517 && cpu_fxsr 518 #endif 519 ) { 520 krateprintf(&badfprate, 521 "pid %d (%s) signal return from user: " 522 "illegal FP MXCSR %08x\n", 523 td->td_proc->p_pid, 524 td->td_proc->p_comm, 525 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 526 } 527 td->td_flags |= TDF_USINGFP; 528 break; 529 } 530 } 531 532 533 #ifndef CPU_DISABLE_SSE 534 /* 535 * On AuthenticAMD processors, the fxrstor instruction does not restore 536 * the x87's stored last instruction pointer, last data pointer, and last 537 * opcode values, except in the rare case in which the exception summary 538 * (ES) bit in the x87 status word is set to 1. 539 * 540 * In order to avoid leaking this information across processes, we clean 541 * these values by performing a dummy load before executing fxrstor(). 542 */ 543 static double dummy_variable = 0.0; 544 static void 545 fpu_clean_state(void) 546 { 547 u_short status; 548 549 /* 550 * Clear the ES bit in the x87 status word if it is currently 551 * set, in order to avoid causing a fault in the upcoming load. 552 */ 553 fnstsw(&status); 554 if (status & 0x80) 555 fnclex(); 556 557 /* 558 * Load the dummy variable into the x87 stack. This mangles 559 * the x87 stack, but we don't care since we're about to call 560 * fxrstor() anyway. 561 */ 562 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 563 } 564 #endif /* CPU_DISABLE_SSE */ 565 566 static void 567 fpurstor(union savefpu *addr) 568 { 569 #ifndef CPU_DISABLE_AVX 570 if (cpu_xsave) 571 xrstor(CPU_XFEATURE_X87 | CPU_XFEATURE_SSE | CPU_XFEATURE_YMM, 0, addr); 572 else 573 #endif 574 #ifndef CPU_DISABLE_SSE 575 if (cpu_fxsr) { 576 fpu_clean_state(); 577 fxrstor(addr); 578 } else { 579 frstor(addr); 580 } 581 #else 582 frstor(addr); 583 #endif 584 } 585 586