1 /* 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * Copyright (c) 2006 The DragonFly Project. 5 * Copyright (c) 2006 Matthew Dillon. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 36 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 37 */ 38 39 #include "opt_cpu.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/sysctl.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/signalvar.h> 51 52 #include <sys/thread2.h> 53 54 #include <machine/cputypes.h> 55 #include <machine/frame.h> 56 #include <machine/md_var.h> 57 #include <machine/pcb.h> 58 #include <machine/psl.h> 59 #include <machine/specialreg.h> 60 #include <machine/segments.h> 61 #include <machine/globaldata.h> 62 63 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 64 #define fnclex() __asm("fnclex") 65 #define fninit() __asm("fninit") 66 #define fnop() __asm("fnop") 67 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 68 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 69 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 70 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 71 #define fxrstor(addr) __asm("fxrstor64 %0" : : "m" (*(addr))) 72 #define fxsave(addr) __asm __volatile("fxsave64 %0" : "=m" (*(addr))) 73 74 #ifndef CPU_DISABLE_AVX 75 static inline void 76 xrstor(const void *addr, uint64_t mask) 77 { 78 const uint8_t *area = addr; 79 uint32_t low, high; 80 81 low = mask; 82 high = mask >> 32; 83 84 __asm __volatile("xrstor64 %[area]" 85 : 86 : [area] "m" (*area), "a" (low), "d" (high)); 87 } 88 89 static inline void 90 xsave(void *addr, uint64_t mask) 91 { 92 uint8_t *area = addr; 93 uint32_t low, high; 94 95 low = mask; 96 high = mask >> 32; 97 98 __asm __volatile("xsave64 %[area]" 99 : [area] "=m" (*area) 100 : "a" (low), "d" (high) 101 : "memory"); 102 } 103 #endif /* !CPU_DISABLE_AVX */ 104 105 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 106 : : "n" (CR0_TS) : "ax") 107 #define stop_emulating() __asm("clts") 108 109 typedef u_char bool_t; 110 static void fpu_clean_state(void); 111 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 112 113 static struct krate badfprate = { 1 }; 114 115 __read_mostly uint32_t npx_mxcsr_mask = 0xFFBF; /* this is the default */ 116 __read_mostly uint64_t npx_xcr0_mask = 0; 117 118 /* 119 * Probe the npx_mxcsr_mask as described in the intel document 120 * "Intel processor identification and the CPUID instruction" Section 7 121 * "Denormals are Zero". 122 * Note that for fxsave to work reliably, the os support bit for 123 * FXSAVE/FXRESTORE operations in CR4 has to be set as per 124 * Intel 64 and IA-32 Architectures Developer's Manual: Vol. 1, 125 * 10.5.1.2. 126 */ 127 void npxprobemask(void) 128 { 129 static union savefpu dummy __aligned(64); 130 131 crit_enter(); 132 stop_emulating(); 133 load_cr4(rcr4() | CR4_OSFXSR); 134 fxsave(&dummy); 135 npx_mxcsr_mask = ((uint32_t *)&dummy)[7]; 136 start_emulating(); 137 crit_exit(); 138 } 139 140 /* 141 * Initialize the floating point unit. 142 */ 143 void npxinit(void) 144 { 145 static union savefpu dummy __aligned(64); 146 u_short control = __INITIAL_FPUCW__; 147 u_int mxcsr = __INITIAL_MXCSR__; 148 149 /* 150 * fninit has the same h/w bugs as fnsave. Use the detoxified 151 * fnsave to throw away any junk in the fpu. npxsave() initializes 152 * the fpu and sets npxthread = NULL as important side effects. 153 */ 154 npxsave(&dummy); 155 crit_enter(); 156 stop_emulating(); 157 fldcw(&control); 158 ldmxcsr(mxcsr); 159 fpusave(curthread->td_savefpu, npx_xcr0_mask); 160 mdcpu->gd_npxthread = NULL; 161 start_emulating(); 162 crit_exit(); 163 } 164 165 /* 166 * Free coprocessor (if we have it). 167 */ 168 void 169 npxexit(void) 170 { 171 if (curthread == mdcpu->gd_npxthread) 172 npxsave(curthread->td_savefpu); 173 } 174 175 #if 0 176 /* 177 * The following mechanism is used to ensure that the FPE_... value 178 * that is passed as a trapcode to the signal handler of the user 179 * process does not have more than one bit set. 180 * 181 * Multiple bits may be set if the user process modifies the control 182 * word while a status word bit is already set. While this is a sign 183 * of bad coding, we have no choise than to narrow them down to one 184 * bit, since we must not send a trapcode that is not exactly one of 185 * the FPE_ macros. 186 * 187 * The mechanism has a static table with 127 entries. Each combination 188 * of the 7 FPU status word exception bits directly translates to a 189 * position in this table, where a single FPE_... value is stored. 190 * This FPE_... value stored there is considered the "most important" 191 * of the exception bits and will be sent as the signal code. The 192 * precedence of the bits is based upon Intel Document "Numerical 193 * Applications", Chapter "Special Computational Situations". 194 * 195 * The macro to choose one of these values does these steps: 1) Throw 196 * away status word bits that cannot be masked. 2) Throw away the bits 197 * currently masked in the control word, assuming the user isn't 198 * interested in them anymore. 3) Reinsert status word bit 7 (stack 199 * fault) if it is set, which cannot be masked but must be presered. 200 * 4) Use the remaining bits to point into the trapcode table. 201 * 202 * The 6 maskable bits in order of their preference, as stated in the 203 * above referenced Intel manual: 204 * 1 Invalid operation (FP_X_INV) 205 * 1a Stack underflow 206 * 1b Stack overflow 207 * 1c Operand of unsupported format 208 * 1d SNaN operand. 209 * 2 QNaN operand (not an exception, irrelavant here) 210 * 3 Any other invalid-operation not mentioned above or zero divide 211 * (FP_X_INV, FP_X_DZ) 212 * 4 Denormal operand (FP_X_DNML) 213 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 214 * 6 Inexact result (FP_X_IMP) 215 */ 216 static char fpetable[128] = { 217 0, 218 FPE_FLTINV, /* 1 - INV */ 219 FPE_FLTUND, /* 2 - DNML */ 220 FPE_FLTINV, /* 3 - INV | DNML */ 221 FPE_FLTDIV, /* 4 - DZ */ 222 FPE_FLTINV, /* 5 - INV | DZ */ 223 FPE_FLTDIV, /* 6 - DNML | DZ */ 224 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 225 FPE_FLTOVF, /* 8 - OFL */ 226 FPE_FLTINV, /* 9 - INV | OFL */ 227 FPE_FLTUND, /* A - DNML | OFL */ 228 FPE_FLTINV, /* B - INV | DNML | OFL */ 229 FPE_FLTDIV, /* C - DZ | OFL */ 230 FPE_FLTINV, /* D - INV | DZ | OFL */ 231 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 232 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 233 FPE_FLTUND, /* 10 - UFL */ 234 FPE_FLTINV, /* 11 - INV | UFL */ 235 FPE_FLTUND, /* 12 - DNML | UFL */ 236 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 237 FPE_FLTDIV, /* 14 - DZ | UFL */ 238 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 239 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 240 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 241 FPE_FLTOVF, /* 18 - OFL | UFL */ 242 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 243 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 244 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 245 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 246 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 247 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 248 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 249 FPE_FLTRES, /* 20 - IMP */ 250 FPE_FLTINV, /* 21 - INV | IMP */ 251 FPE_FLTUND, /* 22 - DNML | IMP */ 252 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 253 FPE_FLTDIV, /* 24 - DZ | IMP */ 254 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 255 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 256 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 257 FPE_FLTOVF, /* 28 - OFL | IMP */ 258 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 259 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 260 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 261 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 262 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 263 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 264 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 265 FPE_FLTUND, /* 30 - UFL | IMP */ 266 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 267 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 268 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 269 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 270 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 271 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 272 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 273 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 274 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 275 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 276 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 277 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 278 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 279 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 280 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 281 FPE_FLTSUB, /* 40 - STK */ 282 FPE_FLTSUB, /* 41 - INV | STK */ 283 FPE_FLTUND, /* 42 - DNML | STK */ 284 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 285 FPE_FLTDIV, /* 44 - DZ | STK */ 286 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 287 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 288 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 289 FPE_FLTOVF, /* 48 - OFL | STK */ 290 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 291 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 292 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 293 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 294 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 295 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 296 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 297 FPE_FLTUND, /* 50 - UFL | STK */ 298 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 299 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 300 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 301 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 302 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 303 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 304 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 305 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 306 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 307 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 308 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 309 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 310 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 311 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 312 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 313 FPE_FLTRES, /* 60 - IMP | STK */ 314 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 315 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 316 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 317 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 318 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 319 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 320 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 321 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 322 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 323 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 324 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 325 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 326 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 327 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 328 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 329 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 330 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 331 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 332 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 333 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 334 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 335 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 336 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 337 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 338 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 339 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 340 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 341 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 342 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 343 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 344 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 345 }; 346 347 #endif 348 349 /* 350 * Implement the device not available (DNA) exception. gd_npxthread had 351 * better be NULL. Restore the current thread's FP state and set gd_npxthread 352 * to curthread. 353 * 354 * Interrupts are enabled and preemption can occur. Enter a critical 355 * section to stabilize the FP state. 356 */ 357 int 358 npxdna(void) 359 { 360 struct mdglobaldata *md = mdcpu; 361 thread_t td; 362 int didinit = 0; 363 364 td = md->mi.gd_curthread; 365 366 /* 367 * npxthread is almost always NULL. When it isn't NULL it can 368 * only be exactly equal to 'td'. This case occurs when the switch 369 * code pro-actively restores the FPU state due to the trap() code 370 * being interruptable (e.g. such as by an interrupt thread). 371 */ 372 if (__predict_false(md->gd_npxthread != NULL)) { 373 if (md->gd_npxthread == td) { 374 return 1; 375 } 376 kprintf("npxdna: npxthread = %p, curthread = %p\n", 377 md->gd_npxthread, td); 378 panic("npxdna"); 379 } 380 381 /* 382 * Setup the initial saved state if the thread has never before 383 * used the FP unit. This also occurs when a thread pushes a 384 * signal handler and uses FP in the handler. 385 */ 386 crit_enter(); 387 if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) { 388 td->td_flags |= TDF_USINGFP; 389 npxinit(); 390 didinit = 1; 391 } 392 393 /* 394 * The setting of gd_npxthread and the call to fpurstor() must not 395 * be preempted by an interrupt thread or we will take an npxdna 396 * trap and potentially save our current fpstate (which is garbage) 397 * and then restore the garbage rather then the originally saved 398 * fpstate. 399 */ 400 stop_emulating(); 401 402 /* 403 * Record new context early in case frstor causes an IRQ13. 404 */ 405 md->gd_npxthread = td; 406 407 /* 408 * The following frstor may cause an IRQ13 when the state being 409 * restored has a pending error. The error will appear to have been 410 * triggered by the current (npx) user instruction even when that 411 * instruction is a no-wait instruction that should not trigger an 412 * error (e.g., fnclex). On at least one 486 system all of the 413 * no-wait instructions are broken the same as frstor, so our 414 * treatment does not amplify the breakage. On at least one 415 * 386/Cyrix 387 system, fnclex works correctly while frstor and 416 * fnsave are broken, so our treatment breaks fnclex if it is the 417 * first FPU instruction after a context switch. 418 */ 419 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask) && 420 cpu_fxsr) { 421 krateprintf(&badfprate, 422 "%s: FXRSTR: illegal FP MXCSR %08x didinit = %d\n", 423 td->td_comm, td->td_savefpu->sv_xmm.sv_env.en_mxcsr, 424 didinit); 425 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= npx_mxcsr_mask; 426 lwpsignal(td->td_proc, td->td_lwp, SIGFPE); 427 } 428 fpurstor(td->td_savefpu, npx_xcr0_mask); 429 crit_exit(); 430 431 return (1); 432 } 433 434 /* 435 * From cpu heavy restore (already in critical section, gd_npxthread is NULL), 436 * and TDF_USINGFP is already set. Actively restore the FPU state to avoid 437 * excessive npxdna traps. 438 */ 439 void 440 npxdna_quick(thread_t newtd) 441 { 442 stop_emulating(); 443 mdcpu->gd_npxthread = newtd; 444 if ((newtd->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask) && 445 cpu_fxsr) { 446 krateprintf(&badfprate, 447 "%s: FXRSTR: illegal FP MXCSR %08x\n", 448 newtd->td_comm, 449 newtd->td_savefpu->sv_xmm.sv_env.en_mxcsr); 450 newtd->td_savefpu->sv_xmm.sv_env.en_mxcsr &= npx_mxcsr_mask; 451 lwpsignal(newtd->td_proc, newtd->td_lwp, SIGFPE); 452 } 453 fpurstor(newtd->td_savefpu, npx_xcr0_mask); 454 } 455 456 /* 457 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 458 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 459 * any IRQ13 to be handled immediately, and then ignore it. This routine is 460 * often called at splhigh so it must not use many system services. In 461 * particular, it's much easier to install a special handler than to 462 * guarantee that it's safe to use npxintr() and its supporting code. 463 * 464 * WARNING! This call is made during a switch and the MP lock will be 465 * setup for the new target thread rather then the current thread, so we 466 * cannot do anything here that depends on the *_mplock() functions as 467 * we may trip over their assertions. 468 * 469 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 470 * kernel will always assume that the FP state is 'safe' (will not cause 471 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 472 * setup a custom save area before actually using the FP unit, but it will 473 * not bother calling fninit. This greatly improves kernel performance when 474 * it wishes to use the FP unit. 475 */ 476 void 477 npxsave(union savefpu *addr) 478 { 479 struct mdglobaldata *md; 480 481 md = mdcpu; 482 crit_enter(); 483 stop_emulating(); 484 fpusave(addr, npx_xcr0_mask); 485 md->gd_npxthread = NULL; 486 fninit(); 487 fpurstor(&md->gd_zerofpu, npx_xcr0_mask); /* security wipe */ 488 start_emulating(); 489 crit_exit(); 490 } 491 492 void 493 fpusave(union savefpu *addr, uint64_t mask) 494 { 495 #ifndef CPU_DISABLE_AVX 496 if (cpu_xsave) 497 xsave(addr, mask); 498 else 499 #endif 500 if (cpu_fxsr) 501 fxsave(addr); 502 else 503 fnsave(addr); 504 } 505 506 /* 507 * Save the FP state to the mcontext structure. 508 * 509 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 510 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 511 */ 512 void 513 npxpush(mcontext_t *mctx) 514 { 515 thread_t td = curthread; 516 517 KKASSERT((td->td_flags & TDF_KERNELFP) == 0); 518 519 if (td->td_flags & TDF_USINGFP) { 520 if (mdcpu->gd_npxthread == td) { 521 /* 522 * XXX Note: This is a bit inefficient if the signal 523 * handler uses floating point, extra faults will 524 * occur. 525 */ 526 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 527 npxsave(td->td_savefpu); 528 } else { 529 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 530 } 531 KKASSERT(sizeof(*td->td_savefpu) <= sizeof(mctx->mc_fpregs)); 532 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(*td->td_savefpu)); 533 td->td_flags &= ~TDF_USINGFP; 534 #ifndef CPU_DISABLE_AVX 535 if (npx_xcr0_mask & CPU_XFEATURE_YMM) 536 mctx->mc_fpformat = _MC_FPFMT_YMM; 537 else 538 #endif 539 { 540 if (cpu_fxsr) 541 mctx->mc_fpformat = _MC_FPFMT_XMM; 542 else 543 mctx->mc_fpformat = _MC_FPFMT_387; 544 } 545 } else { 546 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 547 mctx->mc_fpformat = _MC_FPFMT_NODEV; 548 } 549 } 550 551 /* 552 * Restore the FP state from the mcontext structure. 553 */ 554 void 555 npxpop(mcontext_t *mctx) 556 { 557 thread_t td = curthread; 558 559 switch (mctx->mc_ownedfp) { 560 case _MC_FPOWNED_NONE: 561 /* 562 * If the signal handler used the FP unit but the interrupted 563 * code did not, release the FP unit. Clear TDF_USINGFP will 564 * force the FP unit to reinit so the interrupted code sees 565 * a clean slate. 566 */ 567 if (td->td_flags & TDF_USINGFP) { 568 if (td == mdcpu->gd_npxthread) 569 npxsave(td->td_savefpu); 570 td->td_flags &= ~TDF_USINGFP; 571 } 572 break; 573 case _MC_FPOWNED_FPU: 574 case _MC_FPOWNED_PCB: 575 /* 576 * Clear ownership of the FP unit and restore our saved state. 577 * 578 * NOTE: The signal handler may have set-up some FP state and 579 * enabled the FP unit, so we have to restore no matter what. 580 * 581 * XXX: This is bit inefficient, if the code being returned 582 * to is actively using the FP this results in multiple 583 * kernel faults. 584 * 585 * WARNING: The saved state was exposed to userland and may 586 * have to be sanitized to avoid a GP fault in the kernel. 587 */ 588 if (td == mdcpu->gd_npxthread) 589 npxsave(td->td_savefpu); 590 KKASSERT(sizeof(*td->td_savefpu) <= sizeof(mctx->mc_fpregs)); 591 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 592 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask) && 593 cpu_fxsr) { 594 krateprintf(&badfprate, 595 "pid %d (%s) signal return from user: " 596 "illegal FP MXCSR %08x\n", 597 td->td_proc->p_pid, 598 td->td_proc->p_comm, 599 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 600 } 601 td->td_flags |= TDF_USINGFP; 602 break; 603 } 604 } 605 606 607 /* 608 * On AuthenticAMD processors, the fxrstor instruction does not restore 609 * the x87's stored last instruction pointer, last data pointer, and last 610 * opcode values, except in the rare case in which the exception summary 611 * (ES) bit in the x87 status word is set to 1. 612 * 613 * In order to avoid leaking this information across processes, we clean 614 * these values by performing a dummy load before executing fxrstor(). 615 */ 616 static void 617 fpu_clean_state(void) 618 { 619 u_short status; 620 621 /* 622 * Clear the ES bit in the x87 status word if it is currently 623 * set, in order to avoid causing a fault in the upcoming load. 624 */ 625 fnstsw(&status); 626 if (status & 0x80) 627 fnclex(); 628 629 /* 630 * Load the dummy variable into the x87 stack. This mangles 631 * the x87 stack, but we don't care since we're about to call 632 * fxrstor() anyway. 633 */ 634 __asm __volatile("ffree %%st(7); fldz"); 635 } 636 637 void 638 fpurstor(union savefpu *addr, uint64_t mask) 639 { 640 #ifndef CPU_DISABLE_AVX 641 if (cpu_xsave) 642 xrstor(addr, mask); 643 else 644 #endif 645 if (cpu_fxsr) { 646 fpu_clean_state(); 647 fxrstor(addr); 648 } else { 649 frstor(addr); 650 } 651 } 652