1 /* 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * Copyright (c) 2006 The DragonFly Project. 5 * Copyright (c) 2006 Matthew Dillon. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 36 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 37 */ 38 39 #include "opt_debug_npx.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/sysctl.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #ifdef NPX_DEBUG 51 #include <sys/syslog.h> 52 #endif 53 #include <sys/signalvar.h> 54 55 #include <sys/thread2.h> 56 #include <sys/mplock2.h> 57 58 #ifndef SMP 59 #include <machine/asmacros.h> 60 #endif 61 #include <machine/cputypes.h> 62 #include <machine/frame.h> 63 #include <machine/md_var.h> 64 #include <machine/pcb.h> 65 #include <machine/psl.h> 66 #ifndef SMP 67 #include <machine/clock.h> 68 #endif 69 #include <machine/specialreg.h> 70 #include <machine/segments.h> 71 #include <machine/globaldata.h> 72 73 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 74 #define fnclex() __asm("fnclex") 75 #define fninit() __asm("fninit") 76 #define fnop() __asm("fnop") 77 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 78 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 79 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 80 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 81 #ifndef CPU_DISABLE_SSE 82 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 83 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 84 #endif 85 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 86 : : "n" (CR0_TS) : "ax") 87 #define stop_emulating() __asm("clts") 88 89 #ifndef CPU_DISABLE_SSE 90 #define GET_FPU_EXSW_PTR(td) \ 91 (cpu_fxsr ? \ 92 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \ 93 &(td)->td_savefpu->sv_87.sv_ex_sw) 94 #else /* CPU_DISABLE_SSE */ 95 #define GET_FPU_EXSW_PTR(td) \ 96 (&(td)->td_savefpu->sv_87.sv_ex_sw) 97 #endif /* CPU_DISABLE_SSE */ 98 99 typedef u_char bool_t; 100 #ifndef CPU_DISABLE_SSE 101 static void fpu_clean_state(void); 102 #endif 103 104 static struct krate badfprate = { 1 }; 105 106 static void fpusave (union savefpu *); 107 static void fpurstor (union savefpu *); 108 109 /* 110 * Initialize the floating point unit. 111 */ 112 void 113 npxinit(u_short control) 114 { 115 static union savefpu dummy __aligned(16); 116 117 /* 118 * fninit has the same h/w bugs as fnsave. Use the detoxified 119 * fnsave to throw away any junk in the fpu. npxsave() initializes 120 * the fpu and sets npxthread = NULL as important side effects. 121 */ 122 npxsave(&dummy); 123 crit_enter(); 124 stop_emulating(); 125 fldcw(&control); 126 fpusave(curthread->td_savefpu); 127 mdcpu->gd_npxthread = NULL; 128 start_emulating(); 129 crit_exit(); 130 } 131 132 /* 133 * Free coprocessor (if we have it). 134 */ 135 void 136 npxexit(void) 137 { 138 if (curthread == mdcpu->gd_npxthread) 139 npxsave(curthread->td_savefpu); 140 } 141 142 #if 0 143 /* 144 * The following mechanism is used to ensure that the FPE_... value 145 * that is passed as a trapcode to the signal handler of the user 146 * process does not have more than one bit set. 147 * 148 * Multiple bits may be set if the user process modifies the control 149 * word while a status word bit is already set. While this is a sign 150 * of bad coding, we have no choise than to narrow them down to one 151 * bit, since we must not send a trapcode that is not exactly one of 152 * the FPE_ macros. 153 * 154 * The mechanism has a static table with 127 entries. Each combination 155 * of the 7 FPU status word exception bits directly translates to a 156 * position in this table, where a single FPE_... value is stored. 157 * This FPE_... value stored there is considered the "most important" 158 * of the exception bits and will be sent as the signal code. The 159 * precedence of the bits is based upon Intel Document "Numerical 160 * Applications", Chapter "Special Computational Situations". 161 * 162 * The macro to choose one of these values does these steps: 1) Throw 163 * away status word bits that cannot be masked. 2) Throw away the bits 164 * currently masked in the control word, assuming the user isn't 165 * interested in them anymore. 3) Reinsert status word bit 7 (stack 166 * fault) if it is set, which cannot be masked but must be presered. 167 * 4) Use the remaining bits to point into the trapcode table. 168 * 169 * The 6 maskable bits in order of their preference, as stated in the 170 * above referenced Intel manual: 171 * 1 Invalid operation (FP_X_INV) 172 * 1a Stack underflow 173 * 1b Stack overflow 174 * 1c Operand of unsupported format 175 * 1d SNaN operand. 176 * 2 QNaN operand (not an exception, irrelavant here) 177 * 3 Any other invalid-operation not mentioned above or zero divide 178 * (FP_X_INV, FP_X_DZ) 179 * 4 Denormal operand (FP_X_DNML) 180 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 181 * 6 Inexact result (FP_X_IMP) 182 */ 183 static char fpetable[128] = { 184 0, 185 FPE_FLTINV, /* 1 - INV */ 186 FPE_FLTUND, /* 2 - DNML */ 187 FPE_FLTINV, /* 3 - INV | DNML */ 188 FPE_FLTDIV, /* 4 - DZ */ 189 FPE_FLTINV, /* 5 - INV | DZ */ 190 FPE_FLTDIV, /* 6 - DNML | DZ */ 191 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 192 FPE_FLTOVF, /* 8 - OFL */ 193 FPE_FLTINV, /* 9 - INV | OFL */ 194 FPE_FLTUND, /* A - DNML | OFL */ 195 FPE_FLTINV, /* B - INV | DNML | OFL */ 196 FPE_FLTDIV, /* C - DZ | OFL */ 197 FPE_FLTINV, /* D - INV | DZ | OFL */ 198 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 199 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 200 FPE_FLTUND, /* 10 - UFL */ 201 FPE_FLTINV, /* 11 - INV | UFL */ 202 FPE_FLTUND, /* 12 - DNML | UFL */ 203 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 204 FPE_FLTDIV, /* 14 - DZ | UFL */ 205 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 206 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 207 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 208 FPE_FLTOVF, /* 18 - OFL | UFL */ 209 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 210 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 211 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 212 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 213 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 214 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 215 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 216 FPE_FLTRES, /* 20 - IMP */ 217 FPE_FLTINV, /* 21 - INV | IMP */ 218 FPE_FLTUND, /* 22 - DNML | IMP */ 219 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 220 FPE_FLTDIV, /* 24 - DZ | IMP */ 221 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 222 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 223 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 224 FPE_FLTOVF, /* 28 - OFL | IMP */ 225 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 226 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 227 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 228 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 229 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 230 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 231 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 232 FPE_FLTUND, /* 30 - UFL | IMP */ 233 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 234 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 235 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 236 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 237 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 238 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 239 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 240 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 241 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 242 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 243 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 244 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 245 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 246 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 247 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 248 FPE_FLTSUB, /* 40 - STK */ 249 FPE_FLTSUB, /* 41 - INV | STK */ 250 FPE_FLTUND, /* 42 - DNML | STK */ 251 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 252 FPE_FLTDIV, /* 44 - DZ | STK */ 253 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 254 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 255 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 256 FPE_FLTOVF, /* 48 - OFL | STK */ 257 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 258 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 259 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 260 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 261 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 262 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 263 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 264 FPE_FLTUND, /* 50 - UFL | STK */ 265 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 266 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 267 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 268 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 269 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 270 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 271 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 272 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 273 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 274 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 275 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 276 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 277 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 278 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 279 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 280 FPE_FLTRES, /* 60 - IMP | STK */ 281 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 282 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 283 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 284 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 285 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 286 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 287 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 288 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 289 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 290 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 291 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 292 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 293 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 294 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 295 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 296 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 297 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 298 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 299 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 300 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 301 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 302 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 303 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 304 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 305 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 306 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 307 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 308 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 309 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 310 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 311 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 312 }; 313 314 #endif 315 316 /* 317 * Implement the device not available (DNA) exception. gd_npxthread had 318 * better be NULL. Restore the current thread's FP state and set gd_npxthread 319 * to curthread. 320 * 321 * Interrupts are enabled and preemption can occur. Enter a critical 322 * section to stabilize the FP state. 323 */ 324 int 325 npxdna(void) 326 { 327 thread_t td = curthread; 328 u_long *exstat; 329 int didinit = 0; 330 331 if (mdcpu->gd_npxthread != NULL) { 332 kprintf("npxdna: npxthread = %p, curthread = %p\n", 333 mdcpu->gd_npxthread, curthread); 334 panic("npxdna"); 335 } 336 337 /* 338 * Setup the initial saved state if the thread has never before 339 * used the FP unit. This also occurs when a thread pushes a 340 * signal handler and uses FP in the handler. 341 */ 342 if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) { 343 td->td_flags |= TDF_USINGFP; 344 npxinit(__INITIAL_NPXCW__); 345 didinit = 1; 346 } 347 348 /* 349 * The setting of gd_npxthread and the call to fpurstor() must not 350 * be preempted by an interrupt thread or we will take an npxdna 351 * trap and potentially save our current fpstate (which is garbage) 352 * and then restore the garbage rather then the originally saved 353 * fpstate. 354 */ 355 crit_enter(); 356 stop_emulating(); 357 /* 358 * Record new context early in case frstor causes an IRQ13. 359 */ 360 mdcpu->gd_npxthread = td; 361 exstat = GET_FPU_EXSW_PTR(td); 362 *exstat = 0; 363 /* 364 * The following frstor may cause an IRQ13 when the state being 365 * restored has a pending error. The error will appear to have been 366 * triggered by the current (npx) user instruction even when that 367 * instruction is a no-wait instruction that should not trigger an 368 * error (e.g., fnclex). On at least one 486 system all of the 369 * no-wait instructions are broken the same as frstor, so our 370 * treatment does not amplify the breakage. On at least one 371 * 386/Cyrix 387 system, fnclex works correctly while frstor and 372 * fnsave are broken, so our treatment breaks fnclex if it is the 373 * first FPU instruction after a context switch. 374 */ 375 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) 376 #ifndef CPU_DISABLE_SSE 377 && cpu_fxsr 378 #endif 379 ) { 380 krateprintf(&badfprate, 381 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n", 382 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit); 383 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 384 lwpsignal(curproc, curthread->td_lwp, SIGFPE); 385 } 386 fpurstor(td->td_savefpu); 387 crit_exit(); 388 389 return (1); 390 } 391 392 /* 393 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 394 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 395 * any IRQ13 to be handled immediately, and then ignore it. This routine is 396 * often called at splhigh so it must not use many system services. In 397 * particular, it's much easier to install a special handler than to 398 * guarantee that it's safe to use npxintr() and its supporting code. 399 * 400 * WARNING! This call is made during a switch and the MP lock will be 401 * setup for the new target thread rather then the current thread, so we 402 * cannot do anything here that depends on the *_mplock() functions as 403 * we may trip over their assertions. 404 * 405 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 406 * kernel will always assume that the FP state is 'safe' (will not cause 407 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 408 * setup a custom save area before actually using the FP unit, but it will 409 * not bother calling fninit. This greatly improves kernel performance when 410 * it wishes to use the FP unit. 411 */ 412 void 413 npxsave(union savefpu *addr) 414 { 415 crit_enter(); 416 stop_emulating(); 417 fpusave(addr); 418 mdcpu->gd_npxthread = NULL; 419 fninit(); 420 start_emulating(); 421 crit_exit(); 422 } 423 424 static void 425 fpusave(union savefpu *addr) 426 { 427 #ifndef CPU_DISABLE_SSE 428 if (cpu_fxsr) 429 fxsave(addr); 430 else 431 #endif 432 fnsave(addr); 433 } 434 435 /* 436 * Save the FP state to the mcontext structure. 437 * 438 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 439 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 440 */ 441 void 442 npxpush(mcontext_t *mctx) 443 { 444 thread_t td = curthread; 445 446 KKASSERT((td->td_flags & TDF_KERNELFP) == 0); 447 448 if (td->td_flags & TDF_USINGFP) { 449 if (mdcpu->gd_npxthread == td) { 450 /* 451 * XXX Note: This is a bit inefficient if the signal 452 * handler uses floating point, extra faults will 453 * occur. 454 */ 455 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 456 npxsave(td->td_savefpu); 457 } else { 458 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 459 } 460 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs)); 461 td->td_flags &= ~TDF_USINGFP; 462 mctx->mc_fpformat = 463 #ifndef CPU_DISABLE_SSE 464 (cpu_fxsr) ? _MC_FPFMT_XMM : 465 #endif 466 _MC_FPFMT_387; 467 } else { 468 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 469 mctx->mc_fpformat = _MC_FPFMT_NODEV; 470 } 471 } 472 473 /* 474 * Restore the FP state from the mcontext structure. 475 */ 476 void 477 npxpop(mcontext_t *mctx) 478 { 479 thread_t td = curthread; 480 481 switch(mctx->mc_ownedfp) { 482 case _MC_FPOWNED_NONE: 483 /* 484 * If the signal handler used the FP unit but the interrupted 485 * code did not, release the FP unit. Clear TDF_USINGFP will 486 * force the FP unit to reinit so the interrupted code sees 487 * a clean slate. 488 */ 489 if (td->td_flags & TDF_USINGFP) { 490 if (td == mdcpu->gd_npxthread) 491 npxsave(td->td_savefpu); 492 td->td_flags &= ~TDF_USINGFP; 493 } 494 break; 495 case _MC_FPOWNED_FPU: 496 case _MC_FPOWNED_PCB: 497 /* 498 * Clear ownership of the FP unit and restore our saved state. 499 * 500 * NOTE: The signal handler may have set-up some FP state and 501 * enabled the FP unit, so we have to restore no matter what. 502 * 503 * XXX: This is bit inefficient, if the code being returned 504 * to is actively using the FP this results in multiple 505 * kernel faults. 506 * 507 * WARNING: The saved state was exposed to userland and may 508 * have to be sanitized to avoid a GP fault in the kernel. 509 */ 510 if (td == mdcpu->gd_npxthread) 511 npxsave(td->td_savefpu); 512 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 513 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) 514 #ifndef CPU_DISABLE_SSE 515 && cpu_fxsr 516 #endif 517 ) { 518 krateprintf(&badfprate, 519 "pid %d (%s) signal return from user: " 520 "illegal FP MXCSR %08x\n", 521 td->td_proc->p_pid, 522 td->td_proc->p_comm, 523 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 524 } 525 td->td_flags |= TDF_USINGFP; 526 break; 527 } 528 } 529 530 531 #ifndef CPU_DISABLE_SSE 532 /* 533 * On AuthenticAMD processors, the fxrstor instruction does not restore 534 * the x87's stored last instruction pointer, last data pointer, and last 535 * opcode values, except in the rare case in which the exception summary 536 * (ES) bit in the x87 status word is set to 1. 537 * 538 * In order to avoid leaking this information across processes, we clean 539 * these values by performing a dummy load before executing fxrstor(). 540 */ 541 static double dummy_variable = 0.0; 542 static void 543 fpu_clean_state(void) 544 { 545 u_short status; 546 547 /* 548 * Clear the ES bit in the x87 status word if it is currently 549 * set, in order to avoid causing a fault in the upcoming load. 550 */ 551 fnstsw(&status); 552 if (status & 0x80) 553 fnclex(); 554 555 /* 556 * Load the dummy variable into the x87 stack. This mangles 557 * the x87 stack, but we don't care since we're about to call 558 * fxrstor() anyway. 559 */ 560 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable)); 561 } 562 #endif /* CPU_DISABLE_SSE */ 563 564 static void 565 fpurstor(union savefpu *addr) 566 { 567 #ifndef CPU_DISABLE_SSE 568 if (cpu_fxsr) { 569 fpu_clean_state(); 570 fxrstor(addr); 571 } else { 572 frstor(addr); 573 } 574 #else 575 frstor(addr); 576 #endif 577 } 578 579