1 /* 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * Copyright (c) 2006 The DragonFly Project. 5 * Copyright (c) 2006 Matthew Dillon. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 36 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 37 */ 38 39 #include "opt_cpu.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/sysctl.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/signalvar.h> 51 52 #include <sys/thread2.h> 53 54 #include <machine/cputypes.h> 55 #include <machine/frame.h> 56 #include <machine/md_var.h> 57 #include <machine/pcb.h> 58 #include <machine/psl.h> 59 #include <machine/specialreg.h> 60 #include <machine/segments.h> 61 #include <machine/globaldata.h> 62 63 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 64 #define fnclex() __asm("fnclex") 65 #define fninit() __asm("fninit") 66 #define fnop() __asm("fnop") 67 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 68 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 69 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 70 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 71 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 72 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 73 #ifndef CPU_DISABLE_AVX 74 static inline void 75 xrstor(const void *addr, uint64_t mask) 76 { 77 uint32_t low, high; 78 79 low = mask; 80 high = mask >> 32; 81 82 __asm __volatile(".byte 0x0f,0xae,0x2f" : : "D" (addr), "a" (low), "d" (high)); 83 } 84 static inline void 85 xsave(void *addr, uint64_t mask) 86 { 87 uint32_t low, high; 88 89 low = mask; 90 high = mask >> 32; 91 92 __asm __volatile(".byte 0x0f,0xae,0x27" : : "D" (addr), "a" (low), "d" (high) : "memory"); 93 } 94 #endif 95 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 96 : : "n" (CR0_TS) : "ax") 97 #define stop_emulating() __asm("clts") 98 99 typedef u_char bool_t; 100 static void fpu_clean_state(void); 101 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 102 103 static struct krate badfprate = { 1 }; 104 105 static void fpusave (union savefpu *); 106 static void fpurstor (union savefpu *); 107 108 __read_mostly uint32_t npx_mxcsr_mask = 0xFFBF; /* this is the default */ 109 __read_mostly uint64_t npx_xcr0_mask = 0; 110 111 /* 112 * Probe the npx_mxcsr_mask as described in the intel document 113 * "Intel processor identification and the CPUID instruction" Section 7 114 * "Denormals are Zero". 115 * Note that for fxsave to work reliably, the os support bit for 116 * FXSAVE/FXRESTORE operations in CR4 has to be set as per 117 * Intel 64 and IA-32 Architectures Developer's Manual: Vol. 1, 118 * 10.5.1.2. 119 */ 120 void npxprobemask(void) 121 { 122 /*64-Byte alignment required for xsave*/ 123 static union savefpu dummy __aligned(64); 124 125 crit_enter(); 126 stop_emulating(); 127 load_cr4(rcr4() | CR4_FXSR); 128 fxsave(&dummy); 129 npx_mxcsr_mask = ((uint32_t *)&dummy)[7]; 130 start_emulating(); 131 crit_exit(); 132 } 133 134 /* 135 * Initialize the floating point unit. 136 */ 137 void npxinit(void) 138 { 139 /*64-Byte alignment required for xsave*/ 140 static union savefpu dummy __aligned(64); 141 u_short control = __INITIAL_FPUCW__; 142 u_int mxcsr = __INITIAL_MXCSR__; 143 144 /* 145 * fninit has the same h/w bugs as fnsave. Use the detoxified 146 * fnsave to throw away any junk in the fpu. npxsave() initializes 147 * the fpu and sets npxthread = NULL as important side effects. 148 */ 149 npxsave(&dummy); 150 crit_enter(); 151 stop_emulating(); 152 fldcw(&control); 153 ldmxcsr(mxcsr); 154 fpusave(curthread->td_savefpu); 155 mdcpu->gd_npxthread = NULL; 156 start_emulating(); 157 crit_exit(); 158 } 159 160 /* 161 * Free coprocessor (if we have it). 162 */ 163 void 164 npxexit(void) 165 { 166 if (curthread == mdcpu->gd_npxthread) 167 npxsave(curthread->td_savefpu); 168 } 169 170 #if 0 171 /* 172 * The following mechanism is used to ensure that the FPE_... value 173 * that is passed as a trapcode to the signal handler of the user 174 * process does not have more than one bit set. 175 * 176 * Multiple bits may be set if the user process modifies the control 177 * word while a status word bit is already set. While this is a sign 178 * of bad coding, we have no choise than to narrow them down to one 179 * bit, since we must not send a trapcode that is not exactly one of 180 * the FPE_ macros. 181 * 182 * The mechanism has a static table with 127 entries. Each combination 183 * of the 7 FPU status word exception bits directly translates to a 184 * position in this table, where a single FPE_... value is stored. 185 * This FPE_... value stored there is considered the "most important" 186 * of the exception bits and will be sent as the signal code. The 187 * precedence of the bits is based upon Intel Document "Numerical 188 * Applications", Chapter "Special Computational Situations". 189 * 190 * The macro to choose one of these values does these steps: 1) Throw 191 * away status word bits that cannot be masked. 2) Throw away the bits 192 * currently masked in the control word, assuming the user isn't 193 * interested in them anymore. 3) Reinsert status word bit 7 (stack 194 * fault) if it is set, which cannot be masked but must be presered. 195 * 4) Use the remaining bits to point into the trapcode table. 196 * 197 * The 6 maskable bits in order of their preference, as stated in the 198 * above referenced Intel manual: 199 * 1 Invalid operation (FP_X_INV) 200 * 1a Stack underflow 201 * 1b Stack overflow 202 * 1c Operand of unsupported format 203 * 1d SNaN operand. 204 * 2 QNaN operand (not an exception, irrelavant here) 205 * 3 Any other invalid-operation not mentioned above or zero divide 206 * (FP_X_INV, FP_X_DZ) 207 * 4 Denormal operand (FP_X_DNML) 208 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 209 * 6 Inexact result (FP_X_IMP) 210 */ 211 static char fpetable[128] = { 212 0, 213 FPE_FLTINV, /* 1 - INV */ 214 FPE_FLTUND, /* 2 - DNML */ 215 FPE_FLTINV, /* 3 - INV | DNML */ 216 FPE_FLTDIV, /* 4 - DZ */ 217 FPE_FLTINV, /* 5 - INV | DZ */ 218 FPE_FLTDIV, /* 6 - DNML | DZ */ 219 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 220 FPE_FLTOVF, /* 8 - OFL */ 221 FPE_FLTINV, /* 9 - INV | OFL */ 222 FPE_FLTUND, /* A - DNML | OFL */ 223 FPE_FLTINV, /* B - INV | DNML | OFL */ 224 FPE_FLTDIV, /* C - DZ | OFL */ 225 FPE_FLTINV, /* D - INV | DZ | OFL */ 226 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 227 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 228 FPE_FLTUND, /* 10 - UFL */ 229 FPE_FLTINV, /* 11 - INV | UFL */ 230 FPE_FLTUND, /* 12 - DNML | UFL */ 231 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 232 FPE_FLTDIV, /* 14 - DZ | UFL */ 233 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 234 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 235 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 236 FPE_FLTOVF, /* 18 - OFL | UFL */ 237 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 238 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 239 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 240 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 241 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 242 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 243 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 244 FPE_FLTRES, /* 20 - IMP */ 245 FPE_FLTINV, /* 21 - INV | IMP */ 246 FPE_FLTUND, /* 22 - DNML | IMP */ 247 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 248 FPE_FLTDIV, /* 24 - DZ | IMP */ 249 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 250 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 251 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 252 FPE_FLTOVF, /* 28 - OFL | IMP */ 253 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 254 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 255 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 256 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 257 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 258 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 259 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 260 FPE_FLTUND, /* 30 - UFL | IMP */ 261 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 262 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 263 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 264 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 265 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 266 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 267 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 268 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 269 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 270 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 271 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 272 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 273 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 274 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 275 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 276 FPE_FLTSUB, /* 40 - STK */ 277 FPE_FLTSUB, /* 41 - INV | STK */ 278 FPE_FLTUND, /* 42 - DNML | STK */ 279 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 280 FPE_FLTDIV, /* 44 - DZ | STK */ 281 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 282 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 283 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 284 FPE_FLTOVF, /* 48 - OFL | STK */ 285 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 286 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 287 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 288 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 289 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 290 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 291 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 292 FPE_FLTUND, /* 50 - UFL | STK */ 293 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 294 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 295 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 296 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 297 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 298 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 299 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 300 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 301 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 302 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 303 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 304 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 305 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 306 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 307 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 308 FPE_FLTRES, /* 60 - IMP | STK */ 309 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 310 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 311 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 312 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 313 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 314 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 315 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 316 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 317 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 318 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 319 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 320 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 321 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 322 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 323 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 324 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 325 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 326 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 327 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 328 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 329 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 330 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 331 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 332 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 333 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 334 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 335 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 336 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 337 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 338 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 339 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 340 }; 341 342 #endif 343 344 /* 345 * Implement the device not available (DNA) exception. gd_npxthread had 346 * better be NULL. Restore the current thread's FP state and set gd_npxthread 347 * to curthread. 348 * 349 * Interrupts are enabled and preemption can occur. Enter a critical 350 * section to stabilize the FP state. 351 */ 352 int 353 npxdna(void) 354 { 355 struct mdglobaldata *md = mdcpu; 356 thread_t td; 357 int didinit = 0; 358 359 td = md->mi.gd_curthread; 360 361 /* 362 * npxthread is almost always NULL. When it isn't NULL it can 363 * only be exactly equal to 'td'. This case occurs when the switch 364 * code pro-actively restores the FPU state due to the trap() code 365 * being interruptable (e.g. such as by an interrupt thread). 366 */ 367 if (__predict_false(md->gd_npxthread != NULL)) { 368 if (md->gd_npxthread == td) { 369 return 1; 370 } 371 kprintf("npxdna: npxthread = %p, curthread = %p\n", 372 md->gd_npxthread, td); 373 panic("npxdna"); 374 } 375 376 /* 377 * Setup the initial saved state if the thread has never before 378 * used the FP unit. This also occurs when a thread pushes a 379 * signal handler and uses FP in the handler. 380 */ 381 crit_enter(); 382 if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) { 383 td->td_flags |= TDF_USINGFP; 384 npxinit(); 385 didinit = 1; 386 } 387 388 /* 389 * The setting of gd_npxthread and the call to fpurstor() must not 390 * be preempted by an interrupt thread or we will take an npxdna 391 * trap and potentially save our current fpstate (which is garbage) 392 * and then restore the garbage rather then the originally saved 393 * fpstate. 394 */ 395 stop_emulating(); 396 397 /* 398 * Record new context early in case frstor causes an IRQ13. 399 */ 400 md->gd_npxthread = td; 401 402 /* 403 * The following frstor may cause an IRQ13 when the state being 404 * restored has a pending error. The error will appear to have been 405 * triggered by the current (npx) user instruction even when that 406 * instruction is a no-wait instruction that should not trigger an 407 * error (e.g., fnclex). On at least one 486 system all of the 408 * no-wait instructions are broken the same as frstor, so our 409 * treatment does not amplify the breakage. On at least one 410 * 386/Cyrix 387 system, fnclex works correctly while frstor and 411 * fnsave are broken, so our treatment breaks fnclex if it is the 412 * first FPU instruction after a context switch. 413 */ 414 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask) && 415 cpu_fxsr) { 416 krateprintf(&badfprate, 417 "%s: FXRSTR: illegal FP MXCSR %08x didinit = %d\n", 418 td->td_comm, td->td_savefpu->sv_xmm.sv_env.en_mxcsr, 419 didinit); 420 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= npx_mxcsr_mask; 421 lwpsignal(td->td_proc, td->td_lwp, SIGFPE); 422 } 423 fpurstor(td->td_savefpu); 424 crit_exit(); 425 426 return (1); 427 } 428 429 /* 430 * From cpu heavy restore (already in critical section, gd_npxthread is NULL), 431 * and TDF_USINGFP is already set. Actively restore the FPU state to avoid 432 * excessive npxdna traps. 433 */ 434 void 435 npxdna_quick(thread_t newtd) 436 { 437 stop_emulating(); 438 mdcpu->gd_npxthread = newtd; 439 if ((newtd->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask) && 440 cpu_fxsr) { 441 krateprintf(&badfprate, 442 "%s: FXRSTR: illegal FP MXCSR %08x\n", 443 newtd->td_comm, 444 newtd->td_savefpu->sv_xmm.sv_env.en_mxcsr); 445 newtd->td_savefpu->sv_xmm.sv_env.en_mxcsr &= npx_mxcsr_mask; 446 lwpsignal(newtd->td_proc, newtd->td_lwp, SIGFPE); 447 } 448 fpurstor(newtd->td_savefpu); 449 } 450 451 /* 452 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 453 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 454 * any IRQ13 to be handled immediately, and then ignore it. This routine is 455 * often called at splhigh so it must not use many system services. In 456 * particular, it's much easier to install a special handler than to 457 * guarantee that it's safe to use npxintr() and its supporting code. 458 * 459 * WARNING! This call is made during a switch and the MP lock will be 460 * setup for the new target thread rather then the current thread, so we 461 * cannot do anything here that depends on the *_mplock() functions as 462 * we may trip over their assertions. 463 * 464 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 465 * kernel will always assume that the FP state is 'safe' (will not cause 466 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 467 * setup a custom save area before actually using the FP unit, but it will 468 * not bother calling fninit. This greatly improves kernel performance when 469 * it wishes to use the FP unit. 470 */ 471 void 472 npxsave(union savefpu *addr) 473 { 474 struct mdglobaldata *md; 475 476 md = mdcpu; 477 crit_enter(); 478 stop_emulating(); 479 fpusave(addr); 480 md->gd_npxthread = NULL; 481 fninit(); 482 fpurstor(&md->gd_zerofpu); /* security wipe */ 483 start_emulating(); 484 crit_exit(); 485 } 486 487 static void 488 fpusave(union savefpu *addr) 489 { 490 #ifndef CPU_DISABLE_AVX 491 if (cpu_xsave) 492 xsave(addr, npx_xcr0_mask); 493 else 494 #endif 495 if (cpu_fxsr) 496 fxsave(addr); 497 else 498 fnsave(addr); 499 } 500 501 /* 502 * Save the FP state to the mcontext structure. 503 * 504 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 505 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 506 */ 507 void 508 npxpush(mcontext_t *mctx) 509 { 510 thread_t td = curthread; 511 512 KKASSERT((td->td_flags & TDF_KERNELFP) == 0); 513 514 if (td->td_flags & TDF_USINGFP) { 515 if (mdcpu->gd_npxthread == td) { 516 /* 517 * XXX Note: This is a bit inefficient if the signal 518 * handler uses floating point, extra faults will 519 * occur. 520 */ 521 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 522 npxsave(td->td_savefpu); 523 } else { 524 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 525 } 526 KKASSERT(sizeof(*td->td_savefpu) <= sizeof(mctx->mc_fpregs)); 527 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(*td->td_savefpu)); 528 td->td_flags &= ~TDF_USINGFP; 529 #ifndef CPU_DISABLE_AVX 530 if (npx_xcr0_mask & CPU_XFEATURE_YMM) 531 mctx->mc_fpformat = _MC_FPFMT_YMM; 532 else 533 #endif 534 { 535 if (cpu_fxsr) 536 mctx->mc_fpformat = _MC_FPFMT_XMM; 537 else 538 mctx->mc_fpformat = _MC_FPFMT_387; 539 } 540 } else { 541 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 542 mctx->mc_fpformat = _MC_FPFMT_NODEV; 543 } 544 } 545 546 /* 547 * Restore the FP state from the mcontext structure. 548 */ 549 void 550 npxpop(mcontext_t *mctx) 551 { 552 thread_t td = curthread; 553 554 switch(mctx->mc_ownedfp) { 555 case _MC_FPOWNED_NONE: 556 /* 557 * If the signal handler used the FP unit but the interrupted 558 * code did not, release the FP unit. Clear TDF_USINGFP will 559 * force the FP unit to reinit so the interrupted code sees 560 * a clean slate. 561 */ 562 if (td->td_flags & TDF_USINGFP) { 563 if (td == mdcpu->gd_npxthread) 564 npxsave(td->td_savefpu); 565 td->td_flags &= ~TDF_USINGFP; 566 } 567 break; 568 case _MC_FPOWNED_FPU: 569 case _MC_FPOWNED_PCB: 570 /* 571 * Clear ownership of the FP unit and restore our saved state. 572 * 573 * NOTE: The signal handler may have set-up some FP state and 574 * enabled the FP unit, so we have to restore no matter what. 575 * 576 * XXX: This is bit inefficient, if the code being returned 577 * to is actively using the FP this results in multiple 578 * kernel faults. 579 * 580 * WARNING: The saved state was exposed to userland and may 581 * have to be sanitized to avoid a GP fault in the kernel. 582 */ 583 if (td == mdcpu->gd_npxthread) 584 npxsave(td->td_savefpu); 585 KKASSERT(sizeof(*td->td_savefpu) <= sizeof(mctx->mc_fpregs)); 586 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 587 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask) && 588 cpu_fxsr) { 589 krateprintf(&badfprate, 590 "pid %d (%s) signal return from user: " 591 "illegal FP MXCSR %08x\n", 592 td->td_proc->p_pid, 593 td->td_proc->p_comm, 594 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 595 } 596 td->td_flags |= TDF_USINGFP; 597 break; 598 } 599 } 600 601 602 /* 603 * On AuthenticAMD processors, the fxrstor instruction does not restore 604 * the x87's stored last instruction pointer, last data pointer, and last 605 * opcode values, except in the rare case in which the exception summary 606 * (ES) bit in the x87 status word is set to 1. 607 * 608 * In order to avoid leaking this information across processes, we clean 609 * these values by performing a dummy load before executing fxrstor(). 610 */ 611 static double dummy_variable = 0.0; 612 static void 613 fpu_clean_state(void) 614 { 615 u_short status; 616 617 /* 618 * Clear the ES bit in the x87 status word if it is currently 619 * set, in order to avoid causing a fault in the upcoming load. 620 */ 621 fnstsw(&status); 622 if (status & 0x80) 623 fnclex(); 624 625 /* 626 * Load the dummy variable into the x87 stack. This mangles 627 * the x87 stack, but we don't care since we're about to call 628 * fxrstor() anyway. 629 */ 630 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 631 } 632 633 static void 634 fpurstor(union savefpu *addr) 635 { 636 #ifndef CPU_DISABLE_AVX 637 if (cpu_xsave) 638 xrstor(addr, npx_xcr0_mask); 639 else 640 #endif 641 if (cpu_fxsr) { 642 fpu_clean_state(); 643 fxrstor(addr); 644 } else { 645 frstor(addr); 646 } 647 } 648 649