1 /* 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * Copyright (c) 2006 The DragonFly Project. 5 * Copyright (c) 2006 Matthew Dillon. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 36 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 37 */ 38 39 #include "opt_cpu.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/sysctl.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/signalvar.h> 51 52 #include <sys/thread2.h> 53 #include <sys/mplock2.h> 54 55 #include <machine/cputypes.h> 56 #include <machine/frame.h> 57 #include <machine/md_var.h> 58 #include <machine/pcb.h> 59 #include <machine/psl.h> 60 #include <machine/specialreg.h> 61 #include <machine/segments.h> 62 #include <machine/globaldata.h> 63 64 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 65 #define fnclex() __asm("fnclex") 66 #define fninit() __asm("fninit") 67 #define fnop() __asm("fnop") 68 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 69 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 70 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 71 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 72 #ifndef CPU_DISABLE_SSE 73 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 74 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 75 #endif 76 #ifndef CPU_DISABLE_AVX 77 #define xrstor(eax,edx,addr) __asm __volatile(".byte 0x0f,0xae,0x2f" : : "D" (addr), "a" (eax), "d" (edx)) 78 #define xsave(eax,edx,addr) __asm __volatile(".byte 0x0f,0xae,0x27" : : "D" (addr), "a" (eax), "d" (edx) : "memory") 79 #endif 80 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 81 : : "n" (CR0_TS) : "ax") 82 #define stop_emulating() __asm("clts") 83 84 typedef u_char bool_t; 85 #ifndef CPU_DISABLE_SSE 86 static void fpu_clean_state(void); 87 #endif 88 89 static struct krate badfprate = { 1 }; 90 91 static void fpusave (union savefpu *); 92 static void fpurstor (union savefpu *); 93 94 /* 95 * Initialize the floating point unit. 96 */ 97 void 98 npxinit(u_short control) 99 { 100 /*64-Byte alignment required for xsave*/ 101 static union savefpu dummy __aligned(64); 102 103 /* 104 * fninit has the same h/w bugs as fnsave. Use the detoxified 105 * fnsave to throw away any junk in the fpu. npxsave() initializes 106 * the fpu and sets npxthread = NULL as important side effects. 107 */ 108 npxsave(&dummy); 109 crit_enter(); 110 stop_emulating(); 111 fldcw(&control); 112 fpusave(curthread->td_savefpu); 113 mdcpu->gd_npxthread = NULL; 114 start_emulating(); 115 crit_exit(); 116 } 117 118 /* 119 * Free coprocessor (if we have it). 120 */ 121 void 122 npxexit(void) 123 { 124 if (curthread == mdcpu->gd_npxthread) 125 npxsave(curthread->td_savefpu); 126 } 127 128 #if 0 129 /* 130 * The following mechanism is used to ensure that the FPE_... value 131 * that is passed as a trapcode to the signal handler of the user 132 * process does not have more than one bit set. 133 * 134 * Multiple bits may be set if the user process modifies the control 135 * word while a status word bit is already set. While this is a sign 136 * of bad coding, we have no choise than to narrow them down to one 137 * bit, since we must not send a trapcode that is not exactly one of 138 * the FPE_ macros. 139 * 140 * The mechanism has a static table with 127 entries. Each combination 141 * of the 7 FPU status word exception bits directly translates to a 142 * position in this table, where a single FPE_... value is stored. 143 * This FPE_... value stored there is considered the "most important" 144 * of the exception bits and will be sent as the signal code. The 145 * precedence of the bits is based upon Intel Document "Numerical 146 * Applications", Chapter "Special Computational Situations". 147 * 148 * The macro to choose one of these values does these steps: 1) Throw 149 * away status word bits that cannot be masked. 2) Throw away the bits 150 * currently masked in the control word, assuming the user isn't 151 * interested in them anymore. 3) Reinsert status word bit 7 (stack 152 * fault) if it is set, which cannot be masked but must be presered. 153 * 4) Use the remaining bits to point into the trapcode table. 154 * 155 * The 6 maskable bits in order of their preference, as stated in the 156 * above referenced Intel manual: 157 * 1 Invalid operation (FP_X_INV) 158 * 1a Stack underflow 159 * 1b Stack overflow 160 * 1c Operand of unsupported format 161 * 1d SNaN operand. 162 * 2 QNaN operand (not an exception, irrelavant here) 163 * 3 Any other invalid-operation not mentioned above or zero divide 164 * (FP_X_INV, FP_X_DZ) 165 * 4 Denormal operand (FP_X_DNML) 166 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 167 * 6 Inexact result (FP_X_IMP) 168 */ 169 static char fpetable[128] = { 170 0, 171 FPE_FLTINV, /* 1 - INV */ 172 FPE_FLTUND, /* 2 - DNML */ 173 FPE_FLTINV, /* 3 - INV | DNML */ 174 FPE_FLTDIV, /* 4 - DZ */ 175 FPE_FLTINV, /* 5 - INV | DZ */ 176 FPE_FLTDIV, /* 6 - DNML | DZ */ 177 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 178 FPE_FLTOVF, /* 8 - OFL */ 179 FPE_FLTINV, /* 9 - INV | OFL */ 180 FPE_FLTUND, /* A - DNML | OFL */ 181 FPE_FLTINV, /* B - INV | DNML | OFL */ 182 FPE_FLTDIV, /* C - DZ | OFL */ 183 FPE_FLTINV, /* D - INV | DZ | OFL */ 184 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 185 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 186 FPE_FLTUND, /* 10 - UFL */ 187 FPE_FLTINV, /* 11 - INV | UFL */ 188 FPE_FLTUND, /* 12 - DNML | UFL */ 189 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 190 FPE_FLTDIV, /* 14 - DZ | UFL */ 191 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 192 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 193 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 194 FPE_FLTOVF, /* 18 - OFL | UFL */ 195 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 196 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 197 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 198 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 199 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 200 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 201 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 202 FPE_FLTRES, /* 20 - IMP */ 203 FPE_FLTINV, /* 21 - INV | IMP */ 204 FPE_FLTUND, /* 22 - DNML | IMP */ 205 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 206 FPE_FLTDIV, /* 24 - DZ | IMP */ 207 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 208 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 209 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 210 FPE_FLTOVF, /* 28 - OFL | IMP */ 211 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 212 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 213 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 214 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 215 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 216 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 217 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 218 FPE_FLTUND, /* 30 - UFL | IMP */ 219 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 220 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 221 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 222 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 223 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 224 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 225 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 226 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 227 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 228 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 229 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 230 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 231 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 232 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 233 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 234 FPE_FLTSUB, /* 40 - STK */ 235 FPE_FLTSUB, /* 41 - INV | STK */ 236 FPE_FLTUND, /* 42 - DNML | STK */ 237 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 238 FPE_FLTDIV, /* 44 - DZ | STK */ 239 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 240 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 241 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 242 FPE_FLTOVF, /* 48 - OFL | STK */ 243 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 244 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 245 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 246 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 247 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 248 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 249 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 250 FPE_FLTUND, /* 50 - UFL | STK */ 251 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 252 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 253 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 254 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 255 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 256 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 257 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 258 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 259 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 260 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 261 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 262 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 263 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 264 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 265 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 266 FPE_FLTRES, /* 60 - IMP | STK */ 267 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 268 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 269 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 270 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 271 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 272 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 273 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 274 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 275 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 276 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 277 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 278 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 279 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 280 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 281 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 282 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 283 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 284 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 285 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 286 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 287 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 288 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 289 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 290 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 291 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 292 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 293 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 294 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 295 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 296 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 297 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 298 }; 299 300 #endif 301 302 /* 303 * Implement the device not available (DNA) exception. gd_npxthread had 304 * better be NULL. Restore the current thread's FP state and set gd_npxthread 305 * to curthread. 306 * 307 * Interrupts are enabled and preemption can occur. Enter a critical 308 * section to stabilize the FP state. 309 */ 310 int 311 npxdna(void) 312 { 313 thread_t td = curthread; 314 int didinit = 0; 315 316 if (mdcpu->gd_npxthread != NULL) { 317 kprintf("npxdna: npxthread = %p, curthread = %p\n", 318 mdcpu->gd_npxthread, curthread); 319 panic("npxdna"); 320 } 321 322 /* 323 * Setup the initial saved state if the thread has never before 324 * used the FP unit. This also occurs when a thread pushes a 325 * signal handler and uses FP in the handler. 326 */ 327 crit_enter(); 328 if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) { 329 td->td_flags |= TDF_USINGFP; 330 npxinit(__INITIAL_FPUCW__); 331 didinit = 1; 332 } 333 334 /* 335 * The setting of gd_npxthread and the call to fpurstor() must not 336 * be preempted by an interrupt thread or we will take an npxdna 337 * trap and potentially save our current fpstate (which is garbage) 338 * and then restore the garbage rather then the originally saved 339 * fpstate. 340 */ 341 stop_emulating(); 342 /* 343 * Record new context early in case frstor causes an IRQ13. 344 */ 345 mdcpu->gd_npxthread = td; 346 /* 347 * The following frstor may cause an IRQ13 when the state being 348 * restored has a pending error. The error will appear to have been 349 * triggered by the current (npx) user instruction even when that 350 * instruction is a no-wait instruction that should not trigger an 351 * error (e.g., fnclex). On at least one 486 system all of the 352 * no-wait instructions are broken the same as frstor, so our 353 * treatment does not amplify the breakage. On at least one 354 * 386/Cyrix 387 system, fnclex works correctly while frstor and 355 * fnsave are broken, so our treatment breaks fnclex if it is the 356 * first FPU instruction after a context switch. 357 */ 358 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) 359 #ifndef CPU_DISABLE_SSE 360 && cpu_fxsr 361 #endif 362 ) { 363 krateprintf(&badfprate, 364 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n", 365 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit); 366 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 367 lwpsignal(curproc, curthread->td_lwp, SIGFPE); 368 } 369 fpurstor(td->td_savefpu); 370 crit_exit(); 371 372 return (1); 373 } 374 375 /* 376 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 377 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 378 * any IRQ13 to be handled immediately, and then ignore it. This routine is 379 * often called at splhigh so it must not use many system services. In 380 * particular, it's much easier to install a special handler than to 381 * guarantee that it's safe to use npxintr() and its supporting code. 382 * 383 * WARNING! This call is made during a switch and the MP lock will be 384 * setup for the new target thread rather then the current thread, so we 385 * cannot do anything here that depends on the *_mplock() functions as 386 * we may trip over their assertions. 387 * 388 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 389 * kernel will always assume that the FP state is 'safe' (will not cause 390 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 391 * setup a custom save area before actually using the FP unit, but it will 392 * not bother calling fninit. This greatly improves kernel performance when 393 * it wishes to use the FP unit. 394 */ 395 void 396 npxsave(union savefpu *addr) 397 { 398 crit_enter(); 399 stop_emulating(); 400 fpusave(addr); 401 mdcpu->gd_npxthread = NULL; 402 fninit(); 403 start_emulating(); 404 crit_exit(); 405 } 406 407 static void 408 fpusave(union savefpu *addr) 409 { 410 #ifndef CPU_DISABLE_AVX 411 if (cpu_xsave) 412 xsave(CPU_XFEATURE_X87 | CPU_XFEATURE_SSE | CPU_XFEATURE_YMM, 0, addr); 413 else 414 #endif 415 #ifndef CPU_DISABLE_SSE 416 if (cpu_fxsr) 417 fxsave(addr); 418 else 419 #endif 420 fnsave(addr); 421 } 422 423 /* 424 * Save the FP state to the mcontext structure. 425 * 426 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 427 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 428 */ 429 void 430 npxpush(mcontext_t *mctx) 431 { 432 thread_t td = curthread; 433 434 KKASSERT((td->td_flags & TDF_KERNELFP) == 0); 435 436 if (td->td_flags & TDF_USINGFP) { 437 if (mdcpu->gd_npxthread == td) { 438 /* 439 * XXX Note: This is a bit inefficient if the signal 440 * handler uses floating point, extra faults will 441 * occur. 442 */ 443 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 444 npxsave(td->td_savefpu); 445 } else { 446 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 447 } 448 KKASSERT(sizeof(*td->td_savefpu) <= sizeof(mctx->mc_fpregs)); 449 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(*td->td_savefpu)); 450 td->td_flags &= ~TDF_USINGFP; 451 #ifndef CPU_DISABLE_AVX 452 if (cpu_xsave) 453 mctx->mc_fpformat = _MC_FPFMT_YMM; 454 else 455 #endif 456 #ifndef CPU_DISABLE_SSE 457 if (cpu_fxsr) 458 mctx->mc_fpformat = _MC_FPFMT_XMM; 459 else 460 #endif 461 mctx->mc_fpformat = _MC_FPFMT_387; 462 } else { 463 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 464 mctx->mc_fpformat = _MC_FPFMT_NODEV; 465 } 466 } 467 468 /* 469 * Restore the FP state from the mcontext structure. 470 */ 471 void 472 npxpop(mcontext_t *mctx) 473 { 474 thread_t td = curthread; 475 476 switch(mctx->mc_ownedfp) { 477 case _MC_FPOWNED_NONE: 478 /* 479 * If the signal handler used the FP unit but the interrupted 480 * code did not, release the FP unit. Clear TDF_USINGFP will 481 * force the FP unit to reinit so the interrupted code sees 482 * a clean slate. 483 */ 484 if (td->td_flags & TDF_USINGFP) { 485 if (td == mdcpu->gd_npxthread) 486 npxsave(td->td_savefpu); 487 td->td_flags &= ~TDF_USINGFP; 488 } 489 break; 490 case _MC_FPOWNED_FPU: 491 case _MC_FPOWNED_PCB: 492 /* 493 * Clear ownership of the FP unit and restore our saved state. 494 * 495 * NOTE: The signal handler may have set-up some FP state and 496 * enabled the FP unit, so we have to restore no matter what. 497 * 498 * XXX: This is bit inefficient, if the code being returned 499 * to is actively using the FP this results in multiple 500 * kernel faults. 501 * 502 * WARNING: The saved state was exposed to userland and may 503 * have to be sanitized to avoid a GP fault in the kernel. 504 */ 505 if (td == mdcpu->gd_npxthread) 506 npxsave(td->td_savefpu); 507 KKASSERT(sizeof(*td->td_savefpu) <= sizeof(mctx->mc_fpregs)); 508 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 509 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) 510 #ifndef CPU_DISABLE_SSE 511 && cpu_fxsr 512 #endif 513 ) { 514 krateprintf(&badfprate, 515 "pid %d (%s) signal return from user: " 516 "illegal FP MXCSR %08x\n", 517 td->td_proc->p_pid, 518 td->td_proc->p_comm, 519 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 520 } 521 td->td_flags |= TDF_USINGFP; 522 break; 523 } 524 } 525 526 527 #ifndef CPU_DISABLE_SSE 528 /* 529 * On AuthenticAMD processors, the fxrstor instruction does not restore 530 * the x87's stored last instruction pointer, last data pointer, and last 531 * opcode values, except in the rare case in which the exception summary 532 * (ES) bit in the x87 status word is set to 1. 533 * 534 * In order to avoid leaking this information across processes, we clean 535 * these values by performing a dummy load before executing fxrstor(). 536 */ 537 static double dummy_variable = 0.0; 538 static void 539 fpu_clean_state(void) 540 { 541 u_short status; 542 543 /* 544 * Clear the ES bit in the x87 status word if it is currently 545 * set, in order to avoid causing a fault in the upcoming load. 546 */ 547 fnstsw(&status); 548 if (status & 0x80) 549 fnclex(); 550 551 /* 552 * Load the dummy variable into the x87 stack. This mangles 553 * the x87 stack, but we don't care since we're about to call 554 * fxrstor() anyway. 555 */ 556 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 557 } 558 #endif /* CPU_DISABLE_SSE */ 559 560 static void 561 fpurstor(union savefpu *addr) 562 { 563 #ifndef CPU_DISABLE_AVX 564 if (cpu_xsave) 565 xrstor(CPU_XFEATURE_X87 | CPU_XFEATURE_SSE | CPU_XFEATURE_YMM, 0, addr); 566 else 567 #endif 568 #ifndef CPU_DISABLE_SSE 569 if (cpu_fxsr) { 570 fpu_clean_state(); 571 fxrstor(addr); 572 } else { 573 frstor(addr); 574 } 575 #else 576 frstor(addr); 577 #endif 578 } 579 580