1 /* 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * Copyright (c) 2006 The DragonFly Project. 5 * Copyright (c) 2006 Matthew Dillon. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 36 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 37 */ 38 39 #include "opt_cpu.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/sysctl.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/signalvar.h> 51 52 #include <sys/thread2.h> 53 54 #include <machine/cputypes.h> 55 #include <machine/frame.h> 56 #include <machine/md_var.h> 57 #include <machine/pcb.h> 58 #include <machine/psl.h> 59 #include <machine/specialreg.h> 60 #include <machine/segments.h> 61 #include <machine/globaldata.h> 62 63 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 64 #define fnclex() __asm("fnclex") 65 #define fninit() __asm("fninit") 66 #define fnop() __asm("fnop") 67 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 68 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 69 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 70 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 71 #define fxrstor(addr) __asm("fxrstor64 %0" : : "m" (*(addr))) 72 #define fxsave(addr) __asm __volatile("fxsave64 %0" : "=m" (*(addr))) 73 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 74 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 75 : : "n" (CR0_TS) : "ax") 76 #define stop_emulating() __asm("clts") 77 78 #ifndef CPU_DISABLE_AVX 79 static inline void 80 xrstor(const void *addr, uint64_t mask) 81 { 82 const uint8_t *area = addr; 83 uint32_t low, high; 84 85 low = mask; 86 high = mask >> 32; 87 88 __asm __volatile("xrstor64 %[area]" 89 : 90 : [area] "m" (*area), "a" (low), "d" (high)); 91 } 92 93 static inline void 94 xsave(void *addr, uint64_t mask) 95 { 96 uint8_t *area = addr; 97 uint32_t low, high; 98 99 low = mask; 100 high = mask >> 32; 101 102 __asm __volatile("xsave64 %[area]" 103 : [area] "=m" (*area) 104 : "a" (low), "d" (high) 105 : "memory"); 106 } 107 #endif /* !CPU_DISABLE_AVX */ 108 109 static void fpu_clean_state(void); 110 111 static struct krate badfprate = { 1 }; 112 113 __read_mostly uint32_t npx_mxcsr_mask = 0xFFBF; /* this is the default */ 114 __read_mostly uint64_t npx_xcr0_mask = 0; 115 116 /* 117 * Probe the npx_mxcsr_mask as described in the intel document 118 * "Intel processor identification and the CPUID instruction" Section 7 119 * "Denormals are Zero". 120 * Note that for fxsave to work reliably, the os support bit for 121 * FXSAVE/FXRESTORE operations in CR4 has to be set as per 122 * Intel 64 and IA-32 Architectures Developer's Manual: Vol. 1, 123 * 10.5.1.2. 124 */ 125 void npxprobemask(void) 126 { 127 static union savefpu dummy __aligned(64); 128 129 crit_enter(); 130 stop_emulating(); 131 load_cr4(rcr4() | CR4_OSFXSR); 132 fxsave(&dummy); 133 npx_mxcsr_mask = ((uint32_t *)&dummy)[7]; 134 start_emulating(); 135 crit_exit(); 136 } 137 138 /* 139 * Initialize the floating point unit. 140 */ 141 void npxinit(void) 142 { 143 static union savefpu dummy __aligned(64); 144 u_short control = __INITIAL_FPUCW__; 145 u_int mxcsr = __INITIAL_MXCSR__; 146 147 /* 148 * fninit has the same h/w bugs as fnsave. Use the detoxified 149 * fnsave to throw away any junk in the fpu. npxsave() initializes 150 * the fpu and sets npxthread = NULL as important side effects. 151 */ 152 npxsave(&dummy); 153 crit_enter(); 154 stop_emulating(); 155 fldcw(&control); 156 ldmxcsr(mxcsr); 157 fpusave(curthread->td_savefpu, npx_xcr0_mask); 158 mdcpu->gd_npxthread = NULL; 159 start_emulating(); 160 crit_exit(); 161 } 162 163 /* 164 * Free coprocessor (if we have it). 165 */ 166 void 167 npxexit(void) 168 { 169 if (curthread == mdcpu->gd_npxthread) 170 npxsave(curthread->td_savefpu); 171 } 172 173 #if 0 174 /* 175 * The following mechanism is used to ensure that the FPE_... value 176 * that is passed as a trapcode to the signal handler of the user 177 * process does not have more than one bit set. 178 * 179 * Multiple bits may be set if the user process modifies the control 180 * word while a status word bit is already set. While this is a sign 181 * of bad coding, we have no choise than to narrow them down to one 182 * bit, since we must not send a trapcode that is not exactly one of 183 * the FPE_ macros. 184 * 185 * The mechanism has a static table with 127 entries. Each combination 186 * of the 7 FPU status word exception bits directly translates to a 187 * position in this table, where a single FPE_... value is stored. 188 * This FPE_... value stored there is considered the "most important" 189 * of the exception bits and will be sent as the signal code. The 190 * precedence of the bits is based upon Intel Document "Numerical 191 * Applications", Chapter "Special Computational Situations". 192 * 193 * The macro to choose one of these values does these steps: 1) Throw 194 * away status word bits that cannot be masked. 2) Throw away the bits 195 * currently masked in the control word, assuming the user isn't 196 * interested in them anymore. 3) Reinsert status word bit 7 (stack 197 * fault) if it is set, which cannot be masked but must be presered. 198 * 4) Use the remaining bits to point into the trapcode table. 199 * 200 * The 6 maskable bits in order of their preference, as stated in the 201 * above referenced Intel manual: 202 * 1 Invalid operation (FP_X_INV) 203 * 1a Stack underflow 204 * 1b Stack overflow 205 * 1c Operand of unsupported format 206 * 1d SNaN operand. 207 * 2 QNaN operand (not an exception, irrelavant here) 208 * 3 Any other invalid-operation not mentioned above or zero divide 209 * (FP_X_INV, FP_X_DZ) 210 * 4 Denormal operand (FP_X_DNML) 211 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 212 * 6 Inexact result (FP_X_IMP) 213 */ 214 static char fpetable[128] = { 215 0, 216 FPE_FLTINV, /* 1 - INV */ 217 FPE_FLTUND, /* 2 - DNML */ 218 FPE_FLTINV, /* 3 - INV | DNML */ 219 FPE_FLTDIV, /* 4 - DZ */ 220 FPE_FLTINV, /* 5 - INV | DZ */ 221 FPE_FLTDIV, /* 6 - DNML | DZ */ 222 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 223 FPE_FLTOVF, /* 8 - OFL */ 224 FPE_FLTINV, /* 9 - INV | OFL */ 225 FPE_FLTUND, /* A - DNML | OFL */ 226 FPE_FLTINV, /* B - INV | DNML | OFL */ 227 FPE_FLTDIV, /* C - DZ | OFL */ 228 FPE_FLTINV, /* D - INV | DZ | OFL */ 229 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 230 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 231 FPE_FLTUND, /* 10 - UFL */ 232 FPE_FLTINV, /* 11 - INV | UFL */ 233 FPE_FLTUND, /* 12 - DNML | UFL */ 234 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 235 FPE_FLTDIV, /* 14 - DZ | UFL */ 236 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 237 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 238 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 239 FPE_FLTOVF, /* 18 - OFL | UFL */ 240 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 241 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 242 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 243 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 244 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 245 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 246 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 247 FPE_FLTRES, /* 20 - IMP */ 248 FPE_FLTINV, /* 21 - INV | IMP */ 249 FPE_FLTUND, /* 22 - DNML | IMP */ 250 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 251 FPE_FLTDIV, /* 24 - DZ | IMP */ 252 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 253 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 254 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 255 FPE_FLTOVF, /* 28 - OFL | IMP */ 256 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 257 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 258 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 259 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 260 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 261 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 262 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 263 FPE_FLTUND, /* 30 - UFL | IMP */ 264 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 265 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 266 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 267 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 268 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 269 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 270 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 271 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 272 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 273 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 274 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 275 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 276 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 277 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 278 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 279 FPE_FLTSUB, /* 40 - STK */ 280 FPE_FLTSUB, /* 41 - INV | STK */ 281 FPE_FLTUND, /* 42 - DNML | STK */ 282 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 283 FPE_FLTDIV, /* 44 - DZ | STK */ 284 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 285 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 286 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 287 FPE_FLTOVF, /* 48 - OFL | STK */ 288 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 289 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 290 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 291 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 292 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 293 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 294 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 295 FPE_FLTUND, /* 50 - UFL | STK */ 296 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 297 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 298 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 299 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 300 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 301 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 302 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 303 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 304 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 305 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 306 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 307 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 308 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 309 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 310 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 311 FPE_FLTRES, /* 60 - IMP | STK */ 312 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 313 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 314 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 315 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 316 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 317 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 318 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 319 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 320 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 321 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 322 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 323 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 324 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 325 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 326 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 327 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 328 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 329 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 330 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 331 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 332 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 333 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 334 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 335 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 336 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 337 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 338 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 339 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 340 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 341 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 342 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 343 }; 344 345 #endif 346 347 /* 348 * Implement the device not available (DNA) exception. gd_npxthread had 349 * better be NULL. Restore the current thread's FP state and set gd_npxthread 350 * to curthread. 351 * 352 * Interrupts are enabled and preemption can occur. Enter a critical 353 * section to stabilize the FP state. 354 */ 355 int 356 npxdna(void) 357 { 358 struct mdglobaldata *md = mdcpu; 359 thread_t td; 360 int didinit = 0; 361 362 td = md->mi.gd_curthread; 363 364 /* 365 * npxthread is almost always NULL. When it isn't NULL it can 366 * only be exactly equal to 'td'. This case occurs when the switch 367 * code pro-actively restores the FPU state due to the trap() code 368 * being interruptable (e.g. such as by an interrupt thread). 369 */ 370 if (__predict_false(md->gd_npxthread != NULL)) { 371 if (md->gd_npxthread == td) { 372 return 1; 373 } 374 kprintf("npxdna: npxthread = %p, curthread = %p\n", 375 md->gd_npxthread, td); 376 panic("npxdna"); 377 } 378 379 /* 380 * Setup the initial saved state if the thread has never before 381 * used the FP unit. This also occurs when a thread pushes a 382 * signal handler and uses FP in the handler. 383 */ 384 crit_enter(); 385 if ((td->td_flags & (TDF_USINGFP | TDF_KERNELFP)) == 0) { 386 td->td_flags |= TDF_USINGFP; 387 npxinit(); 388 didinit = 1; 389 } 390 391 /* 392 * The setting of gd_npxthread and the call to fpurstor() must not 393 * be preempted by an interrupt thread or we will take an npxdna 394 * trap and potentially save our current fpstate (which is garbage) 395 * and then restore the garbage rather then the originally saved 396 * fpstate. 397 */ 398 stop_emulating(); 399 400 /* 401 * Record new context early in case frstor causes an IRQ13. 402 */ 403 md->gd_npxthread = td; 404 405 /* 406 * The following frstor may cause an IRQ13 when the state being 407 * restored has a pending error. The error will appear to have been 408 * triggered by the current (npx) user instruction even when that 409 * instruction is a no-wait instruction that should not trigger an 410 * error (e.g., fnclex). On at least one 486 system all of the 411 * no-wait instructions are broken the same as frstor, so our 412 * treatment does not amplify the breakage. On at least one 413 * 386/Cyrix 387 system, fnclex works correctly while frstor and 414 * fnsave are broken, so our treatment breaks fnclex if it is the 415 * first FPU instruction after a context switch. 416 */ 417 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask) && 418 cpu_fxsr) { 419 krateprintf(&badfprate, 420 "%s: FXRSTOR: illegal FP MXCSR %08x didinit = %d\n", 421 td->td_comm, td->td_savefpu->sv_xmm.sv_env.en_mxcsr, 422 didinit); 423 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= npx_mxcsr_mask; 424 lwpsignal(td->td_proc, td->td_lwp, SIGFPE); 425 } 426 fpurstor(td->td_savefpu, npx_xcr0_mask); 427 crit_exit(); 428 429 return (1); 430 } 431 432 /* 433 * From cpu heavy restore (already in critical section, gd_npxthread is NULL), 434 * and TDF_USINGFP is already set. Actively restore the FPU state to avoid 435 * excessive npxdna traps. 436 */ 437 void 438 npxdna_quick(thread_t newtd) 439 { 440 stop_emulating(); 441 mdcpu->gd_npxthread = newtd; 442 if ((newtd->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask) && 443 cpu_fxsr) { 444 krateprintf(&badfprate, 445 "%s: FXRSTOR: illegal FP MXCSR %08x\n", 446 newtd->td_comm, 447 newtd->td_savefpu->sv_xmm.sv_env.en_mxcsr); 448 newtd->td_savefpu->sv_xmm.sv_env.en_mxcsr &= npx_mxcsr_mask; 449 lwpsignal(newtd->td_proc, newtd->td_lwp, SIGFPE); 450 } 451 fpurstor(newtd->td_savefpu, npx_xcr0_mask); 452 } 453 454 /* 455 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 456 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 457 * any IRQ13 to be handled immediately, and then ignore it. This routine is 458 * often called at splhigh so it must not use many system services. In 459 * particular, it's much easier to install a special handler than to 460 * guarantee that it's safe to use npxintr() and its supporting code. 461 * 462 * WARNING! This call is made during a switch and the MP lock will be 463 * setup for the new target thread rather then the current thread, so we 464 * cannot do anything here that depends on the *_mplock() functions as 465 * we may trip over their assertions. 466 * 467 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 468 * kernel will always assume that the FP state is 'safe' (will not cause 469 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 470 * setup a custom save area before actually using the FP unit, but it will 471 * not bother calling fninit. This greatly improves kernel performance when 472 * it wishes to use the FP unit. 473 */ 474 void 475 npxsave(union savefpu *addr) 476 { 477 struct mdglobaldata *md; 478 479 md = mdcpu; 480 crit_enter(); 481 stop_emulating(); 482 fpusave(addr, npx_xcr0_mask); 483 md->gd_npxthread = NULL; 484 fninit(); 485 fpurstor(&md->gd_zerofpu, npx_xcr0_mask); /* security wipe */ 486 start_emulating(); 487 crit_exit(); 488 } 489 490 void 491 fpusave(union savefpu *addr, uint64_t mask) 492 { 493 #ifndef CPU_DISABLE_AVX 494 if (cpu_xsave) 495 xsave(addr, mask); 496 else 497 #endif 498 if (cpu_fxsr) 499 fxsave(addr); 500 else 501 fnsave(addr); 502 } 503 504 /* 505 * Save the FP state to the mcontext structure. 506 * 507 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 508 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 509 */ 510 void 511 npxpush(mcontext_t *mctx) 512 { 513 thread_t td = curthread; 514 515 KKASSERT((td->td_flags & TDF_KERNELFP) == 0); 516 517 if (td->td_flags & TDF_USINGFP) { 518 if (mdcpu->gd_npxthread == td) { 519 /* 520 * XXX Note: This is a bit inefficient if the signal 521 * handler uses floating point, extra faults will 522 * occur. 523 */ 524 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 525 npxsave(td->td_savefpu); 526 } else { 527 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 528 } 529 KKASSERT(sizeof(*td->td_savefpu) <= sizeof(mctx->mc_fpregs)); 530 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(*td->td_savefpu)); 531 td->td_flags &= ~TDF_USINGFP; 532 #ifndef CPU_DISABLE_AVX 533 if (npx_xcr0_mask & CPU_XFEATURE_YMM) 534 mctx->mc_fpformat = _MC_FPFMT_YMM; 535 else 536 #endif 537 { 538 if (cpu_fxsr) 539 mctx->mc_fpformat = _MC_FPFMT_XMM; 540 else 541 mctx->mc_fpformat = _MC_FPFMT_387; 542 } 543 } else { 544 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 545 mctx->mc_fpformat = _MC_FPFMT_NODEV; 546 } 547 } 548 549 /* 550 * Restore the FP state from the mcontext structure. 551 */ 552 void 553 npxpop(mcontext_t *mctx) 554 { 555 thread_t td = curthread; 556 557 switch (mctx->mc_ownedfp) { 558 case _MC_FPOWNED_NONE: 559 /* 560 * If the signal handler used the FP unit but the interrupted 561 * code did not, release the FP unit. Clear TDF_USINGFP will 562 * force the FP unit to reinit so the interrupted code sees 563 * a clean slate. 564 */ 565 if (td->td_flags & TDF_USINGFP) { 566 if (td == mdcpu->gd_npxthread) 567 npxsave(td->td_savefpu); 568 td->td_flags &= ~TDF_USINGFP; 569 } 570 break; 571 case _MC_FPOWNED_FPU: 572 case _MC_FPOWNED_PCB: 573 /* 574 * Clear ownership of the FP unit and restore our saved state. 575 * 576 * NOTE: The signal handler may have set-up some FP state and 577 * enabled the FP unit, so we have to restore no matter what. 578 * 579 * XXX: This is bit inefficient, if the code being returned 580 * to is actively using the FP this results in multiple 581 * kernel faults. 582 * 583 * WARNING: The saved state was exposed to userland and may 584 * have to be sanitized to avoid a GP fault in the kernel. 585 */ 586 if (td == mdcpu->gd_npxthread) 587 npxsave(td->td_savefpu); 588 KKASSERT(sizeof(*td->td_savefpu) <= sizeof(mctx->mc_fpregs)); 589 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 590 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~npx_mxcsr_mask) && 591 cpu_fxsr) { 592 krateprintf(&badfprate, 593 "pid %d (%s) signal return from user: " 594 "illegal FP MXCSR %08x\n", 595 td->td_proc->p_pid, 596 td->td_proc->p_comm, 597 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 598 } 599 td->td_flags |= TDF_USINGFP; 600 break; 601 } 602 } 603 604 605 /* 606 * On AuthenticAMD processors, the fxrstor instruction does not restore 607 * the x87's stored last instruction pointer, last data pointer, and last 608 * opcode values, except in the rare case in which the exception summary 609 * (ES) bit in the x87 status word is set to 1. 610 * 611 * In order to avoid leaking this information across processes, we clean 612 * these values by performing a dummy load before executing fxrstor(). 613 */ 614 static void 615 fpu_clean_state(void) 616 { 617 u_short status; 618 619 /* 620 * Clear the ES bit in the x87 status word if it is currently 621 * set, in order to avoid causing a fault in the upcoming load. 622 */ 623 fnstsw(&status); 624 if (status & 0x80) 625 fnclex(); 626 627 /* 628 * Load the dummy variable into the x87 stack. This mangles 629 * the x87 stack, but we don't care since we're about to call 630 * fxrstor() anyway. 631 */ 632 __asm __volatile("ffree %st(7); fldz"); 633 } 634 635 void 636 fpurstor(union savefpu *addr, uint64_t mask) 637 { 638 #ifndef CPU_DISABLE_AVX 639 if (cpu_xsave) 640 xrstor(addr, mask); 641 else 642 #endif 643 if (cpu_fxsr) { 644 fpu_clean_state(); 645 fxrstor(addr); 646 } else { 647 frstor(addr); 648 } 649 } 650