1/* 2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved. 3 * Copyright (c) 2008 Jordan Gordeev. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Matthew Dillon <dillon@backplane.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * Copyright (c) 1990 The Regents of the University of California. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * William Jolitz. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. Neither the name of the University nor the names of its contributors 50 * may be used to endorse or promote products derived from this software 51 * without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $ 66 */ 67 68//#include "use_npx.h" 69 70#include <sys/rtprio.h> 71 72#include <machine/asmacros.h> 73#include <machine/segments.h> 74 75#include <machine/pmap.h> 76#if 0 /* JG */ 77#include <machine_base/apic/apicreg.h> 78#endif 79#include <machine/lock.h> 80 81#include "assym.s" 82 83#define MPLOCKED lock ; 84 85/* 86 * PREEMPT_OPTIMIZE 87 * 88 * This feature allows the preempting (interrupt) kernel thread to borrow 89 * %cr3 from the user process it interrupts, allowing us to do-away with 90 * two %cr3 stores, two atomic ops (pm_active is not modified), and pmap 91 * lock tests (not needed since pm_active is not modified). 92 * 93 * Unfortunately, I couldn't really measure any result so for now the 94 * optimization is disabled. 95 */ 96#undef PREEMPT_OPTIMIZE 97 98/* 99 * LWP_SWITCH_OPTIMIZE 100 * 101 * This optimization attempted to avoid a %cr3 store and atomic op, and 102 * it might have been useful on older cpus but newer cpus (and more 103 * importantly multi-core cpus) generally do not switch between LWPs on 104 * the same cpu. Multiple user threads are more likely to be distributed 105 * across multiple cpus. In cpu-bound situations the scheduler will already 106 * be in batch-mode (meaning relatively few context-switches/sec), and 107 * otherwise the lwp(s) are likely to be blocked waiting for events. 108 * 109 * On the flip side, the conditionals this option uses measurably reduce 110 * performance (just slightly, honestly). So this option is disabled. 111 */ 112#undef LWP_SWITCH_OPTIMIZE 113 114 /* 115 * Global Declarations 116 */ 117 .data 118 119 .globl panic 120 .globl lwkt_switch_return 121 122#if defined(SWTCH_OPTIM_STATS) 123 .globl swtch_optim_stats, tlb_flush_count 124swtch_optim_stats: .long 0 /* number of _swtch_optims */ 125tlb_flush_count: .long 0 126#endif 127 128 /* 129 * Code 130 */ 131 .text 132 133/* 134 * cpu_heavy_switch(struct thread *next_thread) 135 * 136 * Switch from the current thread to a new thread. This entry 137 * is normally called via the thread->td_switch function, and will 138 * only be called when the current thread is a heavy weight process. 139 * 140 * Some instructions have been reordered to reduce pipeline stalls. 141 * 142 * YYY disable interrupts once giant is removed. 143 */ 144ENTRY(cpu_heavy_switch) 145 /* 146 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15). 147 */ 148 movq PCPU(curthread),%rcx 149 /* On top of the stack is the return adress. */ 150 movq (%rsp),%rax /* (reorder optimization) */ 151 movq TD_PCB(%rcx),%rdx /* RDX = PCB */ 152 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */ 153 movq %rbx,PCB_RBX(%rdx) 154 movq %rsp,PCB_RSP(%rdx) 155 movq %rbp,PCB_RBP(%rdx) 156 movq %r12,PCB_R12(%rdx) 157 movq %r13,PCB_R13(%rdx) 158 movq %r14,PCB_R14(%rdx) 159 movq %r15,PCB_R15(%rdx) 160 161 /* 162 * Clear the cpu bit in the pmap active mask. The restore 163 * function will set the bit in the pmap active mask. 164 * 165 * If we are switching away due to a preempt, TD_PREEMPTED(%rdi) 166 * will be non-NULL. In this situation we do want to avoid extra 167 * atomic ops and %cr3 reloads (see top of file for reasoning). 168 * 169 * NOTE: Do not try to optimize avoiding the %cr3 reload or pm_active 170 * adjustment. This mattered on uni-processor systems but in 171 * multi-core systems we are highly unlikely to be switching 172 * to another thread belonging to the same process on this cpu. 173 * 174 * (more likely the target thread is still sleeping, or if cpu- 175 * bound the scheduler is in batch mode and the switch rate is 176 * already low). 177 */ 178 movq %rcx,%rbx /* RBX = oldthread */ 179#ifdef PREEMPT_OPTIMIZE 180 /* 181 * If we are being preempted the target thread borrows our %cr3 182 * and we leave our pmap bits intact for the duration. 183 */ 184 movq TD_PREEMPTED(%rdi),%r13 185 testq %r13,%r13 186 jne 2f 187#endif 188 189 movq TD_LWP(%rcx),%rcx /* RCX = oldlwp */ 190 movq LWP_VMSPACE(%rcx), %rcx /* RCX = oldvmspace */ 191#ifdef LWP_SWITCH_OPTIMIZE 192 movq TD_LWP(%rdi),%r13 /* R13 = newlwp */ 193 testq %r13,%r13 /* might not be a heavy */ 194 jz 1f 195 cmpq LWP_VMSPACE(%r13),%rcx /* same vmspace? */ 196 je 2f 1971: 198#endif 199 movq PCPU(cpumask_simple),%rsi 200 movq PCPU(cpumask_offset),%r12 201 xorq $-1,%rsi 202 MPLOCKED andq %rsi, VM_PMAP+PM_ACTIVE(%rcx, %r12, 1) 2032: 204 205 /* 206 * Push the LWKT switch restore function, which resumes a heavy 207 * weight process. Note that the LWKT switcher is based on 208 * TD_SP, while the heavy weight process switcher is based on 209 * PCB_RSP. TD_SP is usually two ints pushed relative to 210 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore. 211 */ 212 pushfq 213 cli 214 movq $cpu_heavy_restore, %rax 215 pushq %rax 216 movq %rsp,TD_SP(%rbx) 217 218 /* 219 * Save debug regs if necessary 220 */ 221 movq PCB_FLAGS(%rdx),%rax 222 andq $PCB_DBREGS,%rax 223 jz 1f /* no, skip over */ 224 movq %dr7,%rax /* yes, do the save */ 225 movq %rax,PCB_DR7(%rdx) 226 /* JG correct value? */ 227 andq $0x0000fc00, %rax /* disable all watchpoints */ 228 movq %rax,%dr7 229 movq %dr6,%rax 230 movq %rax,PCB_DR6(%rdx) 231 movq %dr3,%rax 232 movq %rax,PCB_DR3(%rdx) 233 movq %dr2,%rax 234 movq %rax,PCB_DR2(%rdx) 235 movq %dr1,%rax 236 movq %rax,PCB_DR1(%rdx) 237 movq %dr0,%rax 238 movq %rax,PCB_DR0(%rdx) 2391: 240 241#if 1 242 /* 243 * Save the FP state if we have used the FP. Note that calling 244 * npxsave will NULL out PCPU(npxthread). 245 */ 246 cmpq %rbx,PCPU(npxthread) 247 jne 1f 248 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 249 movq TD_SAVEFPU(%rbx),%rdi 250 call npxsave /* do it in a big C function */ 251 movq %r12,%rdi /* restore %rdi */ 2521: 253#endif 254 255 /* 256 * Switch to the next thread, which was passed as an argument 257 * to cpu_heavy_switch(). The argument is in %rdi. 258 * Set the current thread, load the stack pointer, 259 * and 'ret' into the switch-restore function. 260 * 261 * The switch restore function expects the new thread to be in %rax 262 * and the old one to be in %rbx. 263 * 264 * There is a one-instruction window where curthread is the new 265 * thread but %rsp still points to the old thread's stack, but 266 * we are protected by a critical section so it is ok. 267 */ 268 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */ 269 movq %rax,PCPU(curthread) 270 movq TD_SP(%rax),%rsp 271 ret 272 273/* 274 * cpu_exit_switch(struct thread *next) 275 * 276 * The switch function is changed to this when a thread is going away 277 * for good. We have to ensure that the MMU state is not cached, and 278 * we don't bother saving the existing thread state before switching. 279 * 280 * At this point we are in a critical section and this cpu owns the 281 * thread's token, which serves as an interlock until the switchout is 282 * complete. 283 */ 284ENTRY(cpu_exit_switch) 285 286#ifdef PREEMPT_OPTIMIZE 287 /* 288 * If we were preempting we are switching back to the original thread. 289 * In this situation we already have the original thread's %cr3 and 290 * should not replace it! 291 */ 292 testl $TDF_PREEMPT_DONE, TD_FLAGS(%rdi) 293 jne 1f 294#endif 295 296 /* 297 * Get us out of the vmspace 298 */ 299 movq KPML4phys,%rcx 300 movq %cr3,%rax 301 cmpq %rcx,%rax 302 je 1f 303 304 movq %rcx,%cr3 3051: 306 movq PCPU(curthread),%rbx 307 308 /* 309 * If this is a process/lwp, deactivate the pmap after we've 310 * switched it out. 311 */ 312 movq TD_LWP(%rbx),%rcx 313 testq %rcx,%rcx 314 jz 2f 315 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 316 317 movq PCPU(cpumask_simple),%rax 318 movq PCPU(cpumask_offset),%r12 319 xorq $-1,%rax 320 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE(%rcx, %r12, 1) 3212: 322 /* 323 * Switch to the next thread. RET into the restore function, which 324 * expects the new thread in RAX and the old in RBX. 325 * 326 * There is a one-instruction window where curthread is the new 327 * thread but %rsp still points to the old thread's stack, but 328 * we are protected by a critical section so it is ok. 329 */ 330 cli 331 movq %rdi,%rax 332 movq %rax,PCPU(curthread) 333 movq TD_SP(%rax),%rsp 334 ret 335 336/* 337 * cpu_heavy_restore() (current thread in %rax on entry, old thread in %rbx) 338 * 339 * Restore the thread after an LWKT switch. This entry is normally 340 * called via the LWKT switch restore function, which was pulled 341 * off the thread stack and jumped to. 342 * 343 * This entry is only called if the thread was previously saved 344 * using cpu_heavy_switch() (the heavy weight process thread switcher), 345 * or when a new process is initially scheduled. 346 * 347 * NOTE: The lwp may be in any state, not necessarily LSRUN, because 348 * a preemption switch may interrupt the process and then return via 349 * cpu_heavy_restore. 350 * 351 * YYY theoretically we do not have to restore everything here, a lot 352 * of this junk can wait until we return to usermode. But for now 353 * we restore everything. 354 * 355 * YYY the PCB crap is really crap, it makes startup a bitch because 356 * we can't switch away. 357 * 358 * YYY note: spl check is done in mi_switch when it splx()'s. 359 */ 360 361ENTRY(cpu_heavy_restore) 362 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 363 movq %rdx, PCPU(common_tss) + TSS_RSP0 364 popfq 365 366#if defined(SWTCH_OPTIM_STATS) 367 incl _swtch_optim_stats 368#endif 369#ifdef PREEMPT_OPTIMIZE 370 /* 371 * If restoring our thread after a preemption has returned to 372 * us, our %cr3 and pmap were borrowed and are being returned to 373 * us and no further action on those items need be taken. 374 */ 375 testl $TDF_PREEMPT_DONE, TD_FLAGS(%rax) 376 jne 4f 377#endif 378 379 /* 380 * Tell the pmap that our cpu is using the VMSPACE now. We cannot 381 * safely test/reload %cr3 until after we have set the bit in the 382 * pmap. 383 * 384 * We must do an interlocked test of the CPULOCK_EXCL at the same 385 * time. If found to be set we will have to wait for it to clear 386 * and then do a forced reload of %cr3 (even if the value matches). 387 * 388 * XXX When switching between two LWPs sharing the same vmspace 389 * the cpu_heavy_switch() code currently avoids clearing the 390 * cpu bit in PM_ACTIVE. So if the bit is already set we can 391 * avoid checking for the interlock via CPULOCK_EXCL. We currently 392 * do not perform this optimization. 393 */ 394 movq TD_LWP(%rax),%rcx 395 movq LWP_VMSPACE(%rcx),%rcx /* RCX = vmspace */ 396 397 movq PCPU(cpumask_simple),%rsi 398 movq PCPU(cpumask_offset),%r12 399 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE(%rcx, %r12, 1) 400 401 movl VM_PMAP+PM_ACTIVE_LOCK(%rcx),%esi 402 testl $CPULOCK_EXCL,%esi 403 jz 1f 404 405 movq %rax,%r12 /* save newthread ptr */ 406 movq %rcx,%rdi /* (found to be set) */ 407 call pmap_interlock_wait /* pmap_interlock_wait(%rdi:vm) */ 408 movq %r12,%rax 409 410 /* 411 * Need unconditional load cr3 412 */ 413 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 414 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */ 415 jmp 2f /* unconditional reload */ 4161: 417 /* 418 * Restore the MMU address space. If it is the same as the last 419 * thread we don't have to invalidate the tlb (i.e. reload cr3). 420 * 421 * XXX Temporary cludge, do NOT do this optimization! The problem 422 * is that the pm_active bit for the cpu had dropped for a small 423 * period of time, just a few cycles, but even one cycle is long 424 * enough for some other cpu doing a pmap invalidation to not see 425 * our cpu. 426 * 427 * When that happens, and we don't invltlb (by loading %cr3), we 428 * wind up with a stale TLB. 429 */ 430 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 431 movq %cr3,%rsi /* RSI = current CR3 */ 432 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */ 433 cmpq %rsi,%rcx 434 /*je 4f*/ 4352: 436#if defined(SWTCH_OPTIM_STATS) 437 decl _swtch_optim_stats 438 incl _tlb_flush_count 439#endif 440 movq %rcx,%cr3 4414: 442 443 /* 444 * NOTE: %rbx is the previous thread and %rax is the new thread. 445 * %rbx is retained throughout so we can return it. 446 * 447 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 448 */ 449 450 /* 451 * Deal with the PCB extension, restore the private tss 452 */ 453 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */ 454 movq $1,%rcx /* maybe mark use of a private tss */ 455 testq %rdi,%rdi 456#if 0 /* JG */ 457 jnz 2f 458#endif 459 460 /* 461 * Going back to the common_tss. We may need to update TSS_RSP0 462 * which sets the top of the supervisor stack when entering from 463 * usermode. The PCB is at the top of the stack but we need another 464 * 16 bytes to take vm86 into account. 465 */ 466 movq %rdx,%rcx 467 /*leaq -TF_SIZE(%rdx),%rcx*/ 468 movq %rcx, PCPU(common_tss) + TSS_RSP0 469 470#if 0 /* JG */ 471 cmpl $0,PCPU(private_tss) /* don't have to reload if */ 472 je 3f /* already using the common TSS */ 473 474 /* JG? */ 475 subq %rcx,%rcx /* unmark use of private tss */ 476 477 /* 478 * Get the address of the common TSS descriptor for the ltr. 479 * There is no way to get the address of a segment-accessed variable 480 * so we store a self-referential pointer at the base of the per-cpu 481 * data area and add the appropriate offset. 482 */ 483 /* JG movl? */ 484 movq $gd_common_tssd, %rdi 485 /* JG name for "%gs:0"? */ 486 addq %gs:0, %rdi 487 488 /* 489 * Move the correct TSS descriptor into the GDT slot, then reload 490 * ltr. 491 */ 4922: 493 /* JG */ 494 movl %rcx,PCPU(private_tss) /* mark/unmark private tss */ 495 movq PCPU(tss_gdt), %rbx /* entry in GDT */ 496 movq 0(%rdi), %rax 497 movq %rax, 0(%rbx) 498 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */ 499 ltr %si 500#endif 501 5023: 503 /* 504 * Restore the user %gs and %fs 505 */ 506 movq PCB_FSBASE(%rdx),%r9 507 cmpq PCPU(user_fs),%r9 508 je 4f 509 movq %rdx,%r10 510 movq %r9,PCPU(user_fs) 511 movl $MSR_FSBASE,%ecx 512 movl PCB_FSBASE(%r10),%eax 513 movl PCB_FSBASE+4(%r10),%edx 514 wrmsr 515 movq %r10,%rdx 5164: 517 movq PCB_GSBASE(%rdx),%r9 518 cmpq PCPU(user_gs),%r9 519 je 5f 520 movq %rdx,%r10 521 movq %r9,PCPU(user_gs) 522 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */ 523 movl PCB_GSBASE(%r10),%eax 524 movl PCB_GSBASE+4(%r10),%edx 525 wrmsr 526 movq %r10,%rdx 5275: 528 529 /* 530 * Restore general registers. %rbx is restored later. 531 */ 532 movq PCB_RSP(%rdx), %rsp 533 movq PCB_RBP(%rdx), %rbp 534 movq PCB_R12(%rdx), %r12 535 movq PCB_R13(%rdx), %r13 536 movq PCB_R14(%rdx), %r14 537 movq PCB_R15(%rdx), %r15 538 movq PCB_RIP(%rdx), %rax 539 movq %rax, (%rsp) 540 movw $KDSEL,%ax 541 movw %ax,%es 542 543#if 0 /* JG */ 544 /* 545 * Restore the user LDT if we have one 546 */ 547 cmpl $0, PCB_USERLDT(%edx) 548 jnz 1f 549 movl _default_ldt,%eax 550 cmpl PCPU(currentldt),%eax 551 je 2f 552 lldt _default_ldt 553 movl %eax,PCPU(currentldt) 554 jmp 2f 5551: pushl %edx 556 call set_user_ldt 557 popl %edx 5582: 559#endif 560#if 0 /* JG */ 561 /* 562 * Restore the user TLS if we have one 563 */ 564 pushl %edx 565 call set_user_TLS 566 popl %edx 567#endif 568 569 /* 570 * Restore the DEBUG register state if necessary. 571 */ 572 movq PCB_FLAGS(%rdx),%rax 573 andq $PCB_DBREGS,%rax 574 jz 1f /* no, skip over */ 575 movq PCB_DR6(%rdx),%rax /* yes, do the restore */ 576 movq %rax,%dr6 577 movq PCB_DR3(%rdx),%rax 578 movq %rax,%dr3 579 movq PCB_DR2(%rdx),%rax 580 movq %rax,%dr2 581 movq PCB_DR1(%rdx),%rax 582 movq %rax,%dr1 583 movq PCB_DR0(%rdx),%rax 584 movq %rax,%dr0 585 movq %dr7,%rax /* load dr7 so as not to disturb */ 586 /* JG correct value? */ 587 andq $0x0000fc00,%rax /* reserved bits */ 588 /* JG we've got more registers on x86_64 */ 589 movq PCB_DR7(%rdx),%rcx 590 /* JG correct value? */ 591 andq $~0x0000fc00,%rcx 592 orq %rcx,%rax 593 movq %rax,%dr7 594 595 /* 596 * Clear the QUICKRET flag when restoring a user process context 597 * so we don't try to do a quick syscall return. 598 */ 5991: 600 andl $~RQF_QUICKRET,PCPU(reqflags) 601 movq %rbx,%rax 602 movq PCB_RBX(%rdx),%rbx 603 ret 604 605/* 606 * savectx(struct pcb *pcb) 607 * 608 * Update pcb, saving current processor state. 609 */ 610ENTRY(savectx) 611 /* fetch PCB */ 612 /* JG use %rdi instead of %rcx everywhere? */ 613 movq %rdi,%rcx 614 615 /* caller's return address - child won't execute this routine */ 616 movq (%rsp),%rax 617 movq %rax,PCB_RIP(%rcx) 618 619 movq %cr3,%rax 620 movq %rax,PCB_CR3(%rcx) 621 622 movq %rbx,PCB_RBX(%rcx) 623 movq %rsp,PCB_RSP(%rcx) 624 movq %rbp,PCB_RBP(%rcx) 625 movq %r12,PCB_R12(%rcx) 626 movq %r13,PCB_R13(%rcx) 627 movq %r14,PCB_R14(%rcx) 628 movq %r15,PCB_R15(%rcx) 629 630#if 1 631 /* 632 * If npxthread == NULL, then the npx h/w state is irrelevant and the 633 * state had better already be in the pcb. This is true for forks 634 * but not for dumps (the old book-keeping with FP flags in the pcb 635 * always lost for dumps because the dump pcb has 0 flags). 636 * 637 * If npxthread != NULL, then we have to save the npx h/w state to 638 * npxthread's pcb and copy it to the requested pcb, or save to the 639 * requested pcb and reload. Copying is easier because we would 640 * have to handle h/w bugs for reloading. We used to lose the 641 * parent's npx state for forks by forgetting to reload. 642 */ 643 movq PCPU(npxthread),%rax 644 testq %rax,%rax 645 jz 1f 646 647 pushq %rcx /* target pcb */ 648 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */ 649 pushq %rax 650 651 movq %rax,%rdi 652 call npxsave 653 654 popq %rax 655 popq %rcx 656 657 movq $PCB_SAVEFPU_SIZE,%rdx 658 leaq PCB_SAVEFPU(%rcx),%rcx 659 movq %rcx,%rsi 660 movq %rax,%rdi 661 call bcopy 662#endif 663 6641: 665 ret 666 667/* 668 * cpu_idle_restore() (current thread in %rax on entry, old thread in %rbx) 669 * (one-time entry) 670 * 671 * Don't bother setting up any regs other than %rbp so backtraces 672 * don't die. This restore function is used to bootstrap into the 673 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for 674 * switching. 675 * 676 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3. 677 * This only occurs during system boot so no special handling is 678 * required for migration. 679 * 680 * If we are an AP we have to call ap_init() before jumping to 681 * cpu_idle(). ap_init() will synchronize with the BP and finish 682 * setting up various ncpu-dependant globaldata fields. This may 683 * happen on UP as well as SMP if we happen to be simulating multiple 684 * cpus. 685 */ 686ENTRY(cpu_idle_restore) 687 /* cli */ 688 movq KPML4phys,%rcx 689 xorq %rbp,%rbp /* dummy frame pointer */ 690 pushq $0 /* dummy return pc */ 691 692 /* NOTE: idle thread can never preempt */ 693 movq %rcx,%cr3 694 cmpl $0,PCPU(cpuid) 695 je 1f 696 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 697 orl $TDF_RUNNING,TD_FLAGS(%rax) /* manual, no switch_return */ 698 call ap_init 699 /* 700 * ap_init can decide to enable interrupts early, but otherwise, or if 701 * we are UP, do it here. 702 */ 703 sti 704 jmp cpu_idle 705 706 /* 707 * cpu 0's idle thread entry for the first time must use normal 708 * lwkt_switch_return() semantics or a pending cpu migration on 709 * thread0 will deadlock. 710 */ 7111: 712 sti 713 pushq %rax 714 movq %rbx,%rdi 715 call lwkt_switch_return 716 popq %rax 717 jmp cpu_idle 718 719/* 720 * cpu_kthread_restore() (current thread is %rax on entry, previous is %rbx) 721 * (one-time execution) 722 * 723 * Don't bother setting up any regs other then %rbp so backtraces 724 * don't die. This restore function is used to bootstrap into an 725 * LWKT based kernel thread only. cpu_lwkt_switch() will be used 726 * after this. 727 * 728 * Because this switch target does not 'return' to lwkt_switch() 729 * we have to call lwkt_switch_return(otd) to clean up otd. 730 * otd is in %ebx. 731 * 732 * Since all of our context is on the stack we are reentrant and 733 * we can release our critical section and enable interrupts early. 734 */ 735ENTRY(cpu_kthread_restore) 736 sti 737 movq KPML4phys,%rcx 738 movq TD_PCB(%rax),%r13 739 xorq %rbp,%rbp 740 741#ifdef PREEMPT_OPTIMIZE 742 /* 743 * If we are preempting someone we borrow their %cr3, do not overwrite 744 * it! 745 */ 746 movq TD_PREEMPTED(%rax),%r14 747 testq %r14,%r14 748 jne 1f 749#endif 750 movq %rcx,%cr3 7511: 752 753 /* 754 * rax and rbx come from the switchout code. Call 755 * lwkt_switch_return(otd). 756 * 757 * NOTE: unlike i386, %rsi and %rdi are not call-saved regs. 758 */ 759 pushq %rax 760 movq %rbx,%rdi 761 call lwkt_switch_return 762 popq %rax 763 decl TD_CRITCOUNT(%rax) 764 movq PCB_R12(%r13),%rdi /* argument to RBX function */ 765 movq PCB_RBX(%r13),%rax /* thread function */ 766 /* note: top of stack return address inherited by function */ 767 jmp *%rax 768 769/* 770 * cpu_lwkt_switch(struct thread *) 771 * 772 * Standard LWKT switching function. Only non-scratch registers are 773 * saved and we don't bother with the MMU state or anything else. 774 * 775 * This function is always called while in a critical section. 776 * 777 * There is a one-instruction window where curthread is the new 778 * thread but %rsp still points to the old thread's stack, but 779 * we are protected by a critical section so it is ok. 780 */ 781ENTRY(cpu_lwkt_switch) 782 pushq %rbp /* JG note: GDB hacked to locate ebp rel to td_sp */ 783 pushq %rbx 784 movq PCPU(curthread),%rbx /* becomes old thread in restore */ 785 pushq %r12 786 pushq %r13 787 pushq %r14 788 pushq %r15 789 pushfq 790 cli 791 792#if 1 793 /* 794 * Save the FP state if we have used the FP. Note that calling 795 * npxsave will NULL out PCPU(npxthread). 796 * 797 * We have to deal with the FP state for LWKT threads in case they 798 * happen to get preempted or block while doing an optimized 799 * bzero/bcopy/memcpy. 800 */ 801 cmpq %rbx,PCPU(npxthread) 802 jne 1f 803 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 804 movq TD_SAVEFPU(%rbx),%rdi 805 call npxsave /* do it in a big C function */ 806 movq %r12,%rdi /* restore %rdi */ 8071: 808#endif 809 810 movq %rdi,%rax /* switch to this thread */ 811 pushq $cpu_lwkt_restore 812 movq %rsp,TD_SP(%rbx) 813 /* 814 * %rax contains new thread, %rbx contains old thread. 815 */ 816 movq %rax,PCPU(curthread) 817 movq TD_SP(%rax),%rsp 818 ret 819 820/* 821 * cpu_lwkt_restore() (current thread in %rax on entry) 822 * 823 * Standard LWKT restore function. This function is always called 824 * while in a critical section. 825 * 826 * WARNING! Due to preemption the restore function can be used to 'return' 827 * to the original thread. Interrupt disablement must be 828 * protected through the switch so we cannot run splz here. 829 */ 830ENTRY(cpu_lwkt_restore) 831#ifdef PREEMPT_OPTIMIZE 832 /* 833 * If we are preempting someone we borrow their %cr3 and pmap 834 */ 835 movq TD_PREEMPTED(%rax),%r14 /* kernel thread preempting? */ 836 testq %r14,%r14 837 jne 1f /* yes, borrow %cr3 from old thread */ 838#endif 839 /* 840 * Don't reload %cr3 if it hasn't changed. Since this is a LWKT 841 * thread (a kernel thread), and the kernel_pmap always permanently 842 * sets all pm_active bits, we don't have the same problem with it 843 * that we do with process pmaps. 844 */ 845 movq KPML4phys,%rcx 846 movq %cr3,%rdx 847 cmpq %rcx,%rdx 848 je 1f 849 movq %rcx,%cr3 8501: 851 /* 852 * Safety, clear RSP0 in the tss so it isn't pointing at the 853 * previous thread's kstack (if a heavy weight user thread). 854 * RSP0 should only be used in ring 3 transitions and kernel 855 * threads run in ring 0 so there should be none. 856 */ 857 xorq %rdx,%rdx 858 movq %rdx, PCPU(common_tss) + TSS_RSP0 859 860 /* 861 * NOTE: %rbx is the previous thread and %rax is the new thread. 862 * %rbx is retained throughout so we can return it. 863 * 864 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 865 */ 866 movq %rbx,%rax 867 popfq 868 popq %r15 869 popq %r14 870 popq %r13 871 popq %r12 872 popq %rbx 873 popq %rbp 874 ret 875