1/* 2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved. 3 * Copyright (c) 2008 Jordan Gordeev. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Matthew Dillon <dillon@backplane.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * Copyright (c) 1990 The Regents of the University of California. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * William Jolitz. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. Neither the name of the University nor the names of its contributors 50 * may be used to endorse or promote products derived from this software 51 * without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $ 66 */ 67 68//#include "use_npx.h" 69 70#include <sys/rtprio.h> 71 72#include <machine/asmacros.h> 73#include <machine/segments.h> 74 75#include <machine/pmap.h> 76#if 0 /* JG */ 77#include <machine_base/apic/apicreg.h> 78#endif 79#include <machine/lock.h> 80 81#include "assym.s" 82 83#define MPLOCKED lock ; 84 85/* 86 * PREEMPT_OPTIMIZE 87 * 88 * This feature allows the preempting (interrupt) kernel thread to borrow 89 * %cr3 from the user process it interrupts, allowing us to do-away with 90 * two %cr3 stores, two atomic ops (pm_active is not modified), and pmap 91 * lock tests (not needed since pm_active is not modified). 92 * 93 * Unfortunately, I couldn't really measure any result so for now the 94 * optimization is disabled. 95 */ 96#undef PREEMPT_OPTIMIZE 97 98/* 99 * LWP_SWITCH_OPTIMIZE 100 * 101 * This optimization attempted to avoid a %cr3 store and atomic op, and 102 * it might have been useful on older cpus but newer cpus (and more 103 * importantly multi-core cpus) generally do not switch between LWPs on 104 * the same cpu. Multiple user threads are more likely to be distributed 105 * across multiple cpus. In cpu-bound situations the scheduler will already 106 * be in batch-mode (meaning relatively few context-switches/sec), and 107 * otherwise the lwp(s) are likely to be blocked waiting for events. 108 * 109 * On the flip side, the conditionals this option uses measurably reduce 110 * performance (just slightly, honestly). So this option is disabled. 111 */ 112#undef LWP_SWITCH_OPTIMIZE 113 114 /* 115 * Global Declarations 116 */ 117 .data 118 119 .globl panic 120 .globl lwkt_switch_return 121 122#if defined(SWTCH_OPTIM_STATS) 123 .globl swtch_optim_stats, tlb_flush_count 124swtch_optim_stats: .long 0 /* number of _swtch_optims */ 125tlb_flush_count: .long 0 126#endif 127 128 /* 129 * Code 130 */ 131 .text 132 133/* 134 * cpu_heavy_switch(struct thread *next_thread) 135 * 136 * Switch from the current thread to a new thread. This entry 137 * is normally called via the thread->td_switch function, and will 138 * only be called when the current thread is a heavy weight process. 139 * 140 * Some instructions have been reordered to reduce pipeline stalls. 141 * 142 * YYY disable interrupts once giant is removed. 143 */ 144ENTRY(cpu_heavy_switch) 145 /* 146 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15). 147 */ 148 movq PCPU(curthread),%rcx 149 /* On top of the stack is the return adress. */ 150 movq (%rsp),%rax /* (reorder optimization) */ 151 movq TD_PCB(%rcx),%rdx /* RDX = PCB */ 152 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */ 153 movq %rbx,PCB_RBX(%rdx) 154 movq %rsp,PCB_RSP(%rdx) 155 movq %rbp,PCB_RBP(%rdx) 156 movq %r12,PCB_R12(%rdx) 157 movq %r13,PCB_R13(%rdx) 158 movq %r14,PCB_R14(%rdx) 159 movq %r15,PCB_R15(%rdx) 160 161 /* 162 * Clear the cpu bit in the pmap active mask. The restore 163 * function will set the bit in the pmap active mask. 164 * 165 * If we are switching away due to a preempt, TD_PREEMPTED(%rdi) 166 * will be non-NULL. In this situation we do want to avoid extra 167 * atomic ops and %cr3 reloads (see top of file for reasoning). 168 * 169 * NOTE: Do not try to optimize avoiding the %cr3 reload or pm_active 170 * adjustment. This mattered on uni-processor systems but in 171 * multi-core systems we are highly unlikely to be switching 172 * to another thread belonging to the same process on this cpu. 173 * 174 * (more likely the target thread is still sleeping, or if cpu- 175 * bound the scheduler is in batch mode and the switch rate is 176 * already low). 177 */ 178 movq %rcx,%rbx /* RBX = oldthread */ 179#ifdef PREEMPT_OPTIMIZE 180 /* 181 * If we are being preempted the target thread borrows our %cr3 182 * and we leave our pmap bits intact for the duration. 183 */ 184 movq TD_PREEMPTED(%rdi),%r13 185 testq %r13,%r13 186 jne 2f 187#endif 188 189 movq TD_LWP(%rcx),%rcx /* RCX = oldlwp */ 190 movq LWP_VMSPACE(%rcx), %rcx /* RCX = oldvmspace */ 191#ifdef LWP_SWITCH_OPTIMIZE 192 movq TD_LWP(%rdi),%r13 /* R13 = newlwp */ 193 testq %r13,%r13 /* might not be a heavy */ 194 jz 1f 195 cmpq LWP_VMSPACE(%r13),%rcx /* same vmspace? */ 196 je 2f 1971: 198#endif 199 movq PCPU(cpumask_simple),%rsi 200 movq PCPU(cpumask_offset),%r12 201 xorq $-1,%rsi 202 MPLOCKED andq %rsi, VM_PMAP+PM_ACTIVE(%rcx, %r12, 1) 2032: 204 205 /* 206 * Push the LWKT switch restore function, which resumes a heavy 207 * weight process. Note that the LWKT switcher is based on 208 * TD_SP, while the heavy weight process switcher is based on 209 * PCB_RSP. TD_SP is usually two ints pushed relative to 210 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore. 211 */ 212 pushfq 213 cli 214 movq $cpu_heavy_restore, %rax 215 pushq %rax 216 movq %rsp,TD_SP(%rbx) 217 218 /* 219 * Save debug regs if necessary 220 */ 221 movq PCB_FLAGS(%rdx),%rax 222 andq $PCB_DBREGS,%rax 223 jz 1f /* no, skip over */ 224 movq %dr7,%rax /* yes, do the save */ 225 movq %rax,PCB_DR7(%rdx) 226 /* JG correct value? */ 227 andq $0x0000fc00, %rax /* disable all watchpoints */ 228 movq %rax,%dr7 229 movq %dr6,%rax 230 movq %rax,PCB_DR6(%rdx) 231 movq %dr3,%rax 232 movq %rax,PCB_DR3(%rdx) 233 movq %dr2,%rax 234 movq %rax,PCB_DR2(%rdx) 235 movq %dr1,%rax 236 movq %rax,PCB_DR1(%rdx) 237 movq %dr0,%rax 238 movq %rax,PCB_DR0(%rdx) 2391: 240 241#if 1 242 /* 243 * Save the FP state if we have used the FP. Note that calling 244 * npxsave will NULL out PCPU(npxthread). 245 */ 246 cmpq %rbx,PCPU(npxthread) 247 jne 1f 248 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 249 movq TD_SAVEFPU(%rbx),%rdi 250 call npxsave /* do it in a big C function */ 251 movq %r12,%rdi /* restore %rdi */ 2521: 253#endif 254 255 /* 256 * Switch to the next thread, which was passed as an argument 257 * to cpu_heavy_switch(). The argument is in %rdi. 258 * Set the current thread, load the stack pointer, 259 * and 'ret' into the switch-restore function. 260 * 261 * The switch restore function expects the new thread to be in %rax 262 * and the old one to be in %rbx. 263 * 264 * There is a one-instruction window where curthread is the new 265 * thread but %rsp still points to the old thread's stack, but 266 * we are protected by a critical section so it is ok. 267 */ 268 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */ 269 movq %rax,PCPU(curthread) 270 movq TD_SP(%rax),%rsp 271 ret 272END(cpu_heavy_switch) 273 274/* 275 * cpu_exit_switch(struct thread *next) 276 * 277 * The switch function is changed to this when a thread is going away 278 * for good. We have to ensure that the MMU state is not cached, and 279 * we don't bother saving the existing thread state before switching. 280 * 281 * At this point we are in a critical section and this cpu owns the 282 * thread's token, which serves as an interlock until the switchout is 283 * complete. 284 */ 285ENTRY(cpu_exit_switch) 286 287#ifdef PREEMPT_OPTIMIZE 288 /* 289 * If we were preempting we are switching back to the original thread. 290 * In this situation we already have the original thread's %cr3 and 291 * should not replace it! 292 */ 293 testl $TDF_PREEMPT_DONE, TD_FLAGS(%rdi) 294 jne 1f 295#endif 296 297 /* 298 * Get us out of the vmspace 299 */ 300 movq KPML4phys,%rcx 301 movq %cr3,%rax 302 cmpq %rcx,%rax 303 je 1f 304 305 movq %rcx,%cr3 3061: 307 movq PCPU(curthread),%rbx 308 309 /* 310 * If this is a process/lwp, deactivate the pmap after we've 311 * switched it out. 312 */ 313 movq TD_LWP(%rbx),%rcx 314 testq %rcx,%rcx 315 jz 2f 316 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 317 318 movq PCPU(cpumask_simple),%rax 319 movq PCPU(cpumask_offset),%r12 320 xorq $-1,%rax 321 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE(%rcx, %r12, 1) 3222: 323 /* 324 * Switch to the next thread. RET into the restore function, which 325 * expects the new thread in RAX and the old in RBX. 326 * 327 * There is a one-instruction window where curthread is the new 328 * thread but %rsp still points to the old thread's stack, but 329 * we are protected by a critical section so it is ok. 330 */ 331 cli 332 movq %rdi,%rax 333 movq %rax,PCPU(curthread) 334 movq TD_SP(%rax),%rsp 335 ret 336END(cpu_exit_switch) 337 338/* 339 * cpu_heavy_restore() (current thread in %rax on entry, old thread in %rbx) 340 * 341 * Restore the thread after an LWKT switch. This entry is normally 342 * called via the LWKT switch restore function, which was pulled 343 * off the thread stack and jumped to. 344 * 345 * This entry is only called if the thread was previously saved 346 * using cpu_heavy_switch() (the heavy weight process thread switcher), 347 * or when a new process is initially scheduled. 348 * 349 * NOTE: The lwp may be in any state, not necessarily LSRUN, because 350 * a preemption switch may interrupt the process and then return via 351 * cpu_heavy_restore. 352 * 353 * YYY theoretically we do not have to restore everything here, a lot 354 * of this junk can wait until we return to usermode. But for now 355 * we restore everything. 356 * 357 * YYY the PCB crap is really crap, it makes startup a bitch because 358 * we can't switch away. 359 * 360 * YYY note: spl check is done in mi_switch when it splx()'s. 361 */ 362 363ENTRY(cpu_heavy_restore) 364 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 365 movq %rdx, PCPU(common_tss) + TSS_RSP0 366 popfq 367 368#if defined(SWTCH_OPTIM_STATS) 369 incl _swtch_optim_stats 370#endif 371#ifdef PREEMPT_OPTIMIZE 372 /* 373 * If restoring our thread after a preemption has returned to 374 * us, our %cr3 and pmap were borrowed and are being returned to 375 * us and no further action on those items need be taken. 376 */ 377 testl $TDF_PREEMPT_DONE, TD_FLAGS(%rax) 378 jne 4f 379#endif 380 381 /* 382 * Tell the pmap that our cpu is using the VMSPACE now. We cannot 383 * safely test/reload %cr3 until after we have set the bit in the 384 * pmap. 385 * 386 * We must do an interlocked test of the CPULOCK_EXCL at the same 387 * time. If found to be set we will have to wait for it to clear 388 * and then do a forced reload of %cr3 (even if the value matches). 389 * 390 * XXX When switching between two LWPs sharing the same vmspace 391 * the cpu_heavy_switch() code currently avoids clearing the 392 * cpu bit in PM_ACTIVE. So if the bit is already set we can 393 * avoid checking for the interlock via CPULOCK_EXCL. We currently 394 * do not perform this optimization. 395 */ 396 movq TD_LWP(%rax),%rcx 397 movq LWP_VMSPACE(%rcx),%rcx /* RCX = vmspace */ 398 399 movq PCPU(cpumask_simple),%rsi 400 movq PCPU(cpumask_offset),%r12 401 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE(%rcx, %r12, 1) 402 403 movl VM_PMAP+PM_ACTIVE_LOCK(%rcx),%esi 404 testl $CPULOCK_EXCL,%esi 405 jz 1f 406 407 movq %rax,%r12 /* save newthread ptr */ 408 movq %rcx,%rdi /* (found to be set) */ 409 call pmap_interlock_wait /* pmap_interlock_wait(%rdi:vm) */ 410 movq %r12,%rax 411 412 /* 413 * Need unconditional load cr3 414 */ 415 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 416 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */ 417 jmp 2f /* unconditional reload */ 4181: 419 /* 420 * Restore the MMU address space. If it is the same as the last 421 * thread we don't have to invalidate the tlb (i.e. reload cr3). 422 * 423 * XXX Temporary cludge, do NOT do this optimization! The problem 424 * is that the pm_active bit for the cpu had dropped for a small 425 * period of time, just a few cycles, but even one cycle is long 426 * enough for some other cpu doing a pmap invalidation to not see 427 * our cpu. 428 * 429 * When that happens, and we don't invltlb (by loading %cr3), we 430 * wind up with a stale TLB. 431 */ 432 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 433 movq %cr3,%rsi /* RSI = current CR3 */ 434 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */ 435 cmpq %rsi,%rcx 436 /*je 4f*/ 4372: 438#if defined(SWTCH_OPTIM_STATS) 439 decl _swtch_optim_stats 440 incl _tlb_flush_count 441#endif 442 movq %rcx,%cr3 4434: 444 445 /* 446 * NOTE: %rbx is the previous thread and %rax is the new thread. 447 * %rbx is retained throughout so we can return it. 448 * 449 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 450 */ 451 452 /* 453 * Deal with the PCB extension, restore the private tss 454 */ 455 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */ 456 movq $1,%rcx /* maybe mark use of a private tss */ 457 testq %rdi,%rdi 458#if 0 /* JG */ 459 jnz 2f 460#endif 461 462 /* 463 * Going back to the common_tss. We may need to update TSS_RSP0 464 * which sets the top of the supervisor stack when entering from 465 * usermode. The PCB is at the top of the stack but we need another 466 * 16 bytes to take vm86 into account. 467 */ 468 movq %rdx,%rcx 469 /*leaq -TF_SIZE(%rdx),%rcx*/ 470 movq %rcx, PCPU(common_tss) + TSS_RSP0 471 472#if 0 /* JG */ 473 cmpl $0,PCPU(private_tss) /* don't have to reload if */ 474 je 3f /* already using the common TSS */ 475 476 /* JG? */ 477 subq %rcx,%rcx /* unmark use of private tss */ 478 479 /* 480 * Get the address of the common TSS descriptor for the ltr. 481 * There is no way to get the address of a segment-accessed variable 482 * so we store a self-referential pointer at the base of the per-cpu 483 * data area and add the appropriate offset. 484 */ 485 /* JG movl? */ 486 movq $gd_common_tssd, %rdi 487 /* JG name for "%gs:0"? */ 488 addq %gs:0, %rdi 489 490 /* 491 * Move the correct TSS descriptor into the GDT slot, then reload 492 * ltr. 493 */ 4942: 495 /* JG */ 496 movl %rcx,PCPU(private_tss) /* mark/unmark private tss */ 497 movq PCPU(tss_gdt), %rbx /* entry in GDT */ 498 movq 0(%rdi), %rax 499 movq %rax, 0(%rbx) 500 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */ 501 ltr %si 502#endif 503 5043: 505 /* 506 * Restore the user %gs and %fs 507 */ 508 movq PCB_FSBASE(%rdx),%r9 509 cmpq PCPU(user_fs),%r9 510 je 4f 511 movq %rdx,%r10 512 movq %r9,PCPU(user_fs) 513 movl $MSR_FSBASE,%ecx 514 movl PCB_FSBASE(%r10),%eax 515 movl PCB_FSBASE+4(%r10),%edx 516 wrmsr 517 movq %r10,%rdx 5184: 519 movq PCB_GSBASE(%rdx),%r9 520 cmpq PCPU(user_gs),%r9 521 je 5f 522 movq %rdx,%r10 523 movq %r9,PCPU(user_gs) 524 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */ 525 movl PCB_GSBASE(%r10),%eax 526 movl PCB_GSBASE+4(%r10),%edx 527 wrmsr 528 movq %r10,%rdx 5295: 530 531 /* 532 * Restore general registers. %rbx is restored later. 533 */ 534 movq PCB_RSP(%rdx), %rsp 535 movq PCB_RBP(%rdx), %rbp 536 movq PCB_R12(%rdx), %r12 537 movq PCB_R13(%rdx), %r13 538 movq PCB_R14(%rdx), %r14 539 movq PCB_R15(%rdx), %r15 540 movq PCB_RIP(%rdx), %rax 541 movq %rax, (%rsp) 542 movw $KDSEL,%ax 543 movw %ax,%es 544 545#if 0 /* JG */ 546 /* 547 * Restore the user LDT if we have one 548 */ 549 cmpl $0, PCB_USERLDT(%edx) 550 jnz 1f 551 movl _default_ldt,%eax 552 cmpl PCPU(currentldt),%eax 553 je 2f 554 lldt _default_ldt 555 movl %eax,PCPU(currentldt) 556 jmp 2f 5571: pushl %edx 558 call set_user_ldt 559 popl %edx 5602: 561#endif 562#if 0 /* JG */ 563 /* 564 * Restore the user TLS if we have one 565 */ 566 pushl %edx 567 call set_user_TLS 568 popl %edx 569#endif 570 571 /* 572 * Restore the DEBUG register state if necessary. 573 */ 574 movq PCB_FLAGS(%rdx),%rax 575 andq $PCB_DBREGS,%rax 576 jz 1f /* no, skip over */ 577 movq PCB_DR6(%rdx),%rax /* yes, do the restore */ 578 movq %rax,%dr6 579 movq PCB_DR3(%rdx),%rax 580 movq %rax,%dr3 581 movq PCB_DR2(%rdx),%rax 582 movq %rax,%dr2 583 movq PCB_DR1(%rdx),%rax 584 movq %rax,%dr1 585 movq PCB_DR0(%rdx),%rax 586 movq %rax,%dr0 587 movq %dr7,%rax /* load dr7 so as not to disturb */ 588 /* JG correct value? */ 589 andq $0x0000fc00,%rax /* reserved bits */ 590 /* JG we've got more registers on x86_64 */ 591 movq PCB_DR7(%rdx),%rcx 592 /* JG correct value? */ 593 andq $~0x0000fc00,%rcx 594 orq %rcx,%rax 595 movq %rax,%dr7 596 597 /* 598 * Clear the QUICKRET flag when restoring a user process context 599 * so we don't try to do a quick syscall return. 600 */ 6011: 602 andl $~RQF_QUICKRET,PCPU(reqflags) 603 movq %rbx,%rax 604 movq PCB_RBX(%rdx),%rbx 605 ret 606END(cpu_heavy_restore) 607 608/* 609 * savectx(struct pcb *pcb) 610 * 611 * Update pcb, saving current processor state. 612 */ 613ENTRY(savectx) 614 /* fetch PCB */ 615 /* JG use %rdi instead of %rcx everywhere? */ 616 movq %rdi,%rcx 617 618 /* caller's return address - child won't execute this routine */ 619 movq (%rsp),%rax 620 movq %rax,PCB_RIP(%rcx) 621 622 movq %cr3,%rax 623 movq %rax,PCB_CR3(%rcx) 624 625 movq %rbx,PCB_RBX(%rcx) 626 movq %rsp,PCB_RSP(%rcx) 627 movq %rbp,PCB_RBP(%rcx) 628 movq %r12,PCB_R12(%rcx) 629 movq %r13,PCB_R13(%rcx) 630 movq %r14,PCB_R14(%rcx) 631 movq %r15,PCB_R15(%rcx) 632 633#if 1 634 /* 635 * If npxthread == NULL, then the npx h/w state is irrelevant and the 636 * state had better already be in the pcb. This is true for forks 637 * but not for dumps (the old book-keeping with FP flags in the pcb 638 * always lost for dumps because the dump pcb has 0 flags). 639 * 640 * If npxthread != NULL, then we have to save the npx h/w state to 641 * npxthread's pcb and copy it to the requested pcb, or save to the 642 * requested pcb and reload. Copying is easier because we would 643 * have to handle h/w bugs for reloading. We used to lose the 644 * parent's npx state for forks by forgetting to reload. 645 */ 646 movq PCPU(npxthread),%rax 647 testq %rax,%rax 648 jz 1f 649 650 pushq %rcx /* target pcb */ 651 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */ 652 pushq %rax 653 654 movq %rax,%rdi 655 call npxsave 656 657 popq %rax 658 popq %rcx 659 660 movq $PCB_SAVEFPU_SIZE,%rdx 661 leaq PCB_SAVEFPU(%rcx),%rcx 662 movq %rcx,%rsi 663 movq %rax,%rdi 664 call bcopy 665#endif 666 6671: 668 ret 669END(savectx) 670 671/* 672 * cpu_idle_restore() (current thread in %rax on entry, old thread in %rbx) 673 * (one-time entry) 674 * 675 * Don't bother setting up any regs other than %rbp so backtraces 676 * don't die. This restore function is used to bootstrap into the 677 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for 678 * switching. 679 * 680 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3. 681 * This only occurs during system boot so no special handling is 682 * required for migration. 683 * 684 * If we are an AP we have to call ap_init() before jumping to 685 * cpu_idle(). ap_init() will synchronize with the BP and finish 686 * setting up various ncpu-dependant globaldata fields. This may 687 * happen on UP as well as SMP if we happen to be simulating multiple 688 * cpus. 689 */ 690ENTRY(cpu_idle_restore) 691 /* cli */ 692 movq KPML4phys,%rcx 693 xorq %rbp,%rbp /* dummy frame pointer */ 694 pushq $0 /* dummy return pc */ 695 696 /* NOTE: idle thread can never preempt */ 697 movq %rcx,%cr3 698 cmpl $0,PCPU(cpuid) 699 je 1f 700 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 701 orl $TDF_RUNNING,TD_FLAGS(%rax) /* manual, no switch_return */ 702 call ap_init 703 /* 704 * ap_init can decide to enable interrupts early, but otherwise, or if 705 * we are UP, do it here. 706 */ 707 sti 708 jmp cpu_idle 709 710 /* 711 * cpu 0's idle thread entry for the first time must use normal 712 * lwkt_switch_return() semantics or a pending cpu migration on 713 * thread0 will deadlock. 714 */ 7151: 716 sti 717 pushq %rax 718 movq %rbx,%rdi 719 call lwkt_switch_return 720 popq %rax 721 jmp cpu_idle 722END(cpu_idle_restore) 723 724/* 725 * cpu_kthread_restore() (current thread is %rax on entry, previous is %rbx) 726 * (one-time execution) 727 * 728 * Don't bother setting up any regs other then %rbp so backtraces 729 * don't die. This restore function is used to bootstrap into an 730 * LWKT based kernel thread only. cpu_lwkt_switch() will be used 731 * after this. 732 * 733 * Because this switch target does not 'return' to lwkt_switch() 734 * we have to call lwkt_switch_return(otd) to clean up otd. 735 * otd is in %ebx. 736 * 737 * Since all of our context is on the stack we are reentrant and 738 * we can release our critical section and enable interrupts early. 739 */ 740ENTRY(cpu_kthread_restore) 741 sti 742 movq KPML4phys,%rcx 743 movq TD_PCB(%rax),%r13 744 xorq %rbp,%rbp 745 746#ifdef PREEMPT_OPTIMIZE 747 /* 748 * If we are preempting someone we borrow their %cr3, do not overwrite 749 * it! 750 */ 751 movq TD_PREEMPTED(%rax),%r14 752 testq %r14,%r14 753 jne 1f 754#endif 755 movq %rcx,%cr3 7561: 757 758 /* 759 * rax and rbx come from the switchout code. Call 760 * lwkt_switch_return(otd). 761 * 762 * NOTE: unlike i386, %rsi and %rdi are not call-saved regs. 763 */ 764 pushq %rax 765 movq %rbx,%rdi 766 call lwkt_switch_return 767 popq %rax 768 decl TD_CRITCOUNT(%rax) 769 movq PCB_R12(%r13),%rdi /* argument to RBX function */ 770 movq PCB_RBX(%r13),%rax /* thread function */ 771 /* note: top of stack return address inherited by function */ 772 jmp *%rax 773END(cpu_kthread_restore) 774 775/* 776 * cpu_lwkt_switch(struct thread *) 777 * 778 * Standard LWKT switching function. Only non-scratch registers are 779 * saved and we don't bother with the MMU state or anything else. 780 * 781 * This function is always called while in a critical section. 782 * 783 * There is a one-instruction window where curthread is the new 784 * thread but %rsp still points to the old thread's stack, but 785 * we are protected by a critical section so it is ok. 786 */ 787ENTRY(cpu_lwkt_switch) 788 pushq %rbp /* JG note: GDB hacked to locate ebp rel to td_sp */ 789 pushq %rbx 790 movq PCPU(curthread),%rbx /* becomes old thread in restore */ 791 pushq %r12 792 pushq %r13 793 pushq %r14 794 pushq %r15 795 pushfq 796 cli 797 798#if 1 799 /* 800 * Save the FP state if we have used the FP. Note that calling 801 * npxsave will NULL out PCPU(npxthread). 802 * 803 * We have to deal with the FP state for LWKT threads in case they 804 * happen to get preempted or block while doing an optimized 805 * bzero/bcopy/memcpy. 806 */ 807 cmpq %rbx,PCPU(npxthread) 808 jne 1f 809 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 810 movq TD_SAVEFPU(%rbx),%rdi 811 call npxsave /* do it in a big C function */ 812 movq %r12,%rdi /* restore %rdi */ 8131: 814#endif 815 816 movq %rdi,%rax /* switch to this thread */ 817 pushq $cpu_lwkt_restore 818 movq %rsp,TD_SP(%rbx) 819 /* 820 * %rax contains new thread, %rbx contains old thread. 821 */ 822 movq %rax,PCPU(curthread) 823 movq TD_SP(%rax),%rsp 824 ret 825END(cpu_lwkt_switch) 826 827/* 828 * cpu_lwkt_restore() (current thread in %rax on entry) 829 * 830 * Standard LWKT restore function. This function is always called 831 * while in a critical section. 832 * 833 * WARNING! Due to preemption the restore function can be used to 'return' 834 * to the original thread. Interrupt disablement must be 835 * protected through the switch so we cannot run splz here. 836 */ 837ENTRY(cpu_lwkt_restore) 838#ifdef PREEMPT_OPTIMIZE 839 /* 840 * If we are preempting someone we borrow their %cr3 and pmap 841 */ 842 movq TD_PREEMPTED(%rax),%r14 /* kernel thread preempting? */ 843 testq %r14,%r14 844 jne 1f /* yes, borrow %cr3 from old thread */ 845#endif 846 /* 847 * Don't reload %cr3 if it hasn't changed. Since this is a LWKT 848 * thread (a kernel thread), and the kernel_pmap always permanently 849 * sets all pm_active bits, we don't have the same problem with it 850 * that we do with process pmaps. 851 */ 852 movq KPML4phys,%rcx 853 movq %cr3,%rdx 854 cmpq %rcx,%rdx 855 je 1f 856 movq %rcx,%cr3 8571: 858 /* 859 * Safety, clear RSP0 in the tss so it isn't pointing at the 860 * previous thread's kstack (if a heavy weight user thread). 861 * RSP0 should only be used in ring 3 transitions and kernel 862 * threads run in ring 0 so there should be none. 863 */ 864 xorq %rdx,%rdx 865 movq %rdx, PCPU(common_tss) + TSS_RSP0 866 867 /* 868 * NOTE: %rbx is the previous thread and %rax is the new thread. 869 * %rbx is retained throughout so we can return it. 870 * 871 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 872 */ 873 movq %rbx,%rax 874 popfq 875 popq %r15 876 popq %r14 877 popq %r13 878 popq %r12 879 popq %rbx 880 popq %rbp 881 ret 882END(cpu_lwkt_restore) 883