1/* 2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved. 3 * Copyright (c) 2008 Jordan Gordeev. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Matthew Dillon <dillon@backplane.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * Copyright (c) 1990 The Regents of the University of California. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * William Jolitz. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the University of 52 * California, Berkeley and its contributors. 53 * 4. Neither the name of the University nor the names of its contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 67 * SUCH DAMAGE. 68 * 69 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $ 70 */ 71 72//#include "use_npx.h" 73 74#include <sys/rtprio.h> 75 76#include <machine/asmacros.h> 77#include <machine/segments.h> 78 79#include <machine/pmap.h> 80#if 0 /* JG */ 81#include <machine_base/apic/apicreg.h> 82#endif 83#include <machine/lock.h> 84 85#include "assym.s" 86 87#define MPLOCKED lock ; 88 89 .data 90 91 .globl panic 92 .globl lwkt_switch_return 93 94#if defined(SWTCH_OPTIM_STATS) 95 .globl swtch_optim_stats, tlb_flush_count 96swtch_optim_stats: .long 0 /* number of _swtch_optims */ 97tlb_flush_count: .long 0 98#endif 99 100 .text 101 102 103/* 104 * cpu_heavy_switch(struct thread *next_thread) 105 * 106 * Switch from the current thread to a new thread. This entry 107 * is normally called via the thread->td_switch function, and will 108 * only be called when the current thread is a heavy weight process. 109 * 110 * Some instructions have been reordered to reduce pipeline stalls. 111 * 112 * YYY disable interrupts once giant is removed. 113 */ 114ENTRY(cpu_heavy_switch) 115 /* 116 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15). 117 */ 118 movq PCPU(curthread),%rcx 119 /* On top of the stack is the return adress. */ 120 movq (%rsp),%rax /* (reorder optimization) */ 121 movq TD_PCB(%rcx),%rdx /* RDX = PCB */ 122 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */ 123 movq %rbx,PCB_RBX(%rdx) 124 movq %rsp,PCB_RSP(%rdx) 125 movq %rbp,PCB_RBP(%rdx) 126 movq %r12,PCB_R12(%rdx) 127 movq %r13,PCB_R13(%rdx) 128 movq %r14,PCB_R14(%rdx) 129 movq %r15,PCB_R15(%rdx) 130 131 /* 132 * Clear the cpu bit in the pmap active mask. The restore 133 * function will set the bit in the pmap active mask. 134 * 135 * Special case: when switching between threads sharing the 136 * same vmspace if we avoid clearing the bit we do not have 137 * to reload %cr3 (if we clear the bit we could race page 138 * table ops done by other threads and would have to reload 139 * %cr3, because those ops will not know to IPI us). 140 */ 141 movq %rcx,%rbx /* RBX = oldthread */ 142 movq TD_LWP(%rcx),%rcx /* RCX = oldlwp */ 143 movq TD_LWP(%rdi),%r13 /* R13 = newlwp */ 144 movq LWP_VMSPACE(%rcx), %rcx /* RCX = oldvmspace */ 145 testq %r13,%r13 /* might not be a heavy */ 146 jz 1f 147 cmpq LWP_VMSPACE(%r13),%rcx /* same vmspace? */ 148 je 2f 149#if CPUMASK_ELEMENTS != 4 150#error "assembly incompatible with cpumask_t" 151#endif 1521: 153 movq PCPU(other_cpus)+0,%rax 154 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+0(%rcx) 155 movq PCPU(other_cpus)+8,%rax 156 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+8(%rcx) 157 movq PCPU(other_cpus)+16,%rax 158 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+16(%rcx) 159 movq PCPU(other_cpus)+24,%rax 160 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+24(%rcx) 1612: 162 163 /* 164 * Push the LWKT switch restore function, which resumes a heavy 165 * weight process. Note that the LWKT switcher is based on 166 * TD_SP, while the heavy weight process switcher is based on 167 * PCB_RSP. TD_SP is usually two ints pushed relative to 168 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore. 169 */ 170 pushfq 171 cli 172 movq $cpu_heavy_restore, %rax 173 pushq %rax 174 movq %rsp,TD_SP(%rbx) 175 176 /* 177 * Save debug regs if necessary 178 */ 179 movq PCB_FLAGS(%rdx),%rax 180 andq $PCB_DBREGS,%rax 181 jz 1f /* no, skip over */ 182 movq %dr7,%rax /* yes, do the save */ 183 movq %rax,PCB_DR7(%rdx) 184 /* JG correct value? */ 185 andq $0x0000fc00, %rax /* disable all watchpoints */ 186 movq %rax,%dr7 187 movq %dr6,%rax 188 movq %rax,PCB_DR6(%rdx) 189 movq %dr3,%rax 190 movq %rax,PCB_DR3(%rdx) 191 movq %dr2,%rax 192 movq %rax,PCB_DR2(%rdx) 193 movq %dr1,%rax 194 movq %rax,PCB_DR1(%rdx) 195 movq %dr0,%rax 196 movq %rax,PCB_DR0(%rdx) 1971: 198 199#if 1 200 /* 201 * Save the FP state if we have used the FP. Note that calling 202 * npxsave will NULL out PCPU(npxthread). 203 */ 204 cmpq %rbx,PCPU(npxthread) 205 jne 1f 206 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 207 movq TD_SAVEFPU(%rbx),%rdi 208 call npxsave /* do it in a big C function */ 209 movq %r12,%rdi /* restore %rdi */ 2101: 211#endif 212 213 /* 214 * Switch to the next thread, which was passed as an argument 215 * to cpu_heavy_switch(). The argument is in %rdi. 216 * Set the current thread, load the stack pointer, 217 * and 'ret' into the switch-restore function. 218 * 219 * The switch restore function expects the new thread to be in %rax 220 * and the old one to be in %rbx. 221 * 222 * There is a one-instruction window where curthread is the new 223 * thread but %rsp still points to the old thread's stack, but 224 * we are protected by a critical section so it is ok. 225 */ 226 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */ 227 movq %rax,PCPU(curthread) 228 movq TD_SP(%rax),%rsp 229 ret 230 231/* 232 * cpu_exit_switch(struct thread *next) 233 * 234 * The switch function is changed to this when a thread is going away 235 * for good. We have to ensure that the MMU state is not cached, and 236 * we don't bother saving the existing thread state before switching. 237 * 238 * At this point we are in a critical section and this cpu owns the 239 * thread's token, which serves as an interlock until the switchout is 240 * complete. 241 */ 242ENTRY(cpu_exit_switch) 243 /* 244 * Get us out of the vmspace 245 */ 246 movq KPML4phys,%rcx 247 movq %cr3,%rax 248#if 1 249 cmpq %rcx,%rax 250 je 1f 251#endif 252 /* JG no increment of statistics counters? see cpu_heavy_restore */ 253 movq %rcx,%cr3 2541: 255 movq PCPU(curthread),%rbx 256 257 /* 258 * If this is a process/lwp, deactivate the pmap after we've 259 * switched it out. 260 */ 261 movq TD_LWP(%rbx),%rcx 262 testq %rcx,%rcx 263 jz 2f 264 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 265 movq PCPU(other_cpus)+0,%rax 266 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+0(%rcx) 267 movq PCPU(other_cpus)+8,%rax 268 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+8(%rcx) 269 movq PCPU(other_cpus)+16,%rax 270 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+16(%rcx) 271 movq PCPU(other_cpus)+24,%rax 272 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+24(%rcx) 2732: 274 /* 275 * Switch to the next thread. RET into the restore function, which 276 * expects the new thread in RAX and the old in RBX. 277 * 278 * There is a one-instruction window where curthread is the new 279 * thread but %rsp still points to the old thread's stack, but 280 * we are protected by a critical section so it is ok. 281 */ 282 cli 283 movq %rdi,%rax 284 movq %rax,PCPU(curthread) 285 movq TD_SP(%rax),%rsp 286 ret 287 288/* 289 * cpu_heavy_restore() (current thread in %rax on entry, old thread in %rbx) 290 * 291 * Restore the thread after an LWKT switch. This entry is normally 292 * called via the LWKT switch restore function, which was pulled 293 * off the thread stack and jumped to. 294 * 295 * This entry is only called if the thread was previously saved 296 * using cpu_heavy_switch() (the heavy weight process thread switcher), 297 * or when a new process is initially scheduled. 298 * 299 * NOTE: The lwp may be in any state, not necessarily LSRUN, because 300 * a preemption switch may interrupt the process and then return via 301 * cpu_heavy_restore. 302 * 303 * YYY theoretically we do not have to restore everything here, a lot 304 * of this junk can wait until we return to usermode. But for now 305 * we restore everything. 306 * 307 * YYY the PCB crap is really crap, it makes startup a bitch because 308 * we can't switch away. 309 * 310 * YYY note: spl check is done in mi_switch when it splx()'s. 311 */ 312 313ENTRY(cpu_heavy_restore) 314 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 315 movq %rdx, PCPU(common_tss) + TSS_RSP0 316 popfq 317 318#if defined(SWTCH_OPTIM_STATS) 319 incl _swtch_optim_stats 320#endif 321 /* 322 * Tell the pmap that our cpu is using the VMSPACE now. We cannot 323 * safely test/reload %cr3 until after we have set the bit in the 324 * pmap. 325 * 326 * We must do an interlocked test of the CPULOCK_EXCL at the same 327 * time. If found to be set we will have to wait for it to clear 328 * and then do a forced reload of %cr3 (even if the value matches). 329 * 330 * XXX When switching between two LWPs sharing the same vmspace 331 * the cpu_heavy_switch() code currently avoids clearing the 332 * cpu bit in PM_ACTIVE. So if the bit is already set we can 333 * avoid checking for the interlock via CPULOCK_EXCL. We currently 334 * do not perform this optimization. 335 */ 336 movq TD_LWP(%rax),%rcx 337 movq LWP_VMSPACE(%rcx),%rcx /* RCX = vmspace */ 338 339#if CPUMASK_ELEMENTS != 4 340#error "assembly incompatible with cpumask_t" 341#endif 342 movq PCPU(cpumask)+0,%rsi /* new contents */ 343 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+0(%rcx) 344 movq PCPU(cpumask)+8,%rsi 345 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+8(%rcx) 346 movq PCPU(cpumask)+16,%rsi 347 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+16(%rcx) 348 movq PCPU(cpumask)+24,%rsi 349 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+24(%rcx) 350 351 movl VM_PMAP+PM_ACTIVE_LOCK(%rcx),%esi 352 testl $CPULOCK_EXCL,%esi 353 jz 1f 354 355 movq %rax,%r12 /* save newthread ptr */ 356 movq %rcx,%rdi /* (found to be set) */ 357 call pmap_interlock_wait /* pmap_interlock_wait(%rdi:vm) */ 358 movq %r12,%rax 359 360 /* 361 * Need unconditional load cr3 362 */ 363 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 364 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */ 365 jmp 2f /* unconditional reload */ 3661: 367 /* 368 * Restore the MMU address space. If it is the same as the last 369 * thread we don't have to invalidate the tlb (i.e. reload cr3). 370 * YYY which naturally also means that the PM_ACTIVE bit had better 371 * already have been set before we set it above, check? YYY 372 */ 373 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 374 movq %cr3,%rsi /* RSI = current CR3 */ 375 movq PCB_CR3(%rdx),%rcx /* RCX = desired CR3 */ 376 cmpq %rsi,%rcx 377 je 4f 3782: 379#if defined(SWTCH_OPTIM_STATS) 380 decl _swtch_optim_stats 381 incl _tlb_flush_count 382#endif 383 movq %rcx,%cr3 3844: 385 386 /* 387 * NOTE: %rbx is the previous thread and %rax is the new thread. 388 * %rbx is retained throughout so we can return it. 389 * 390 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 391 */ 392 393 /* 394 * Deal with the PCB extension, restore the private tss 395 */ 396 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */ 397 movq $1,%rcx /* maybe mark use of a private tss */ 398 testq %rdi,%rdi 399#if 0 /* JG */ 400 jnz 2f 401#endif 402 403 /* 404 * Going back to the common_tss. We may need to update TSS_RSP0 405 * which sets the top of the supervisor stack when entering from 406 * usermode. The PCB is at the top of the stack but we need another 407 * 16 bytes to take vm86 into account. 408 */ 409 movq %rdx,%rcx 410 /*leaq -TF_SIZE(%rdx),%rcx*/ 411 movq %rcx, PCPU(common_tss) + TSS_RSP0 412 413#if 0 /* JG */ 414 cmpl $0,PCPU(private_tss) /* don't have to reload if */ 415 je 3f /* already using the common TSS */ 416 417 /* JG? */ 418 subq %rcx,%rcx /* unmark use of private tss */ 419 420 /* 421 * Get the address of the common TSS descriptor for the ltr. 422 * There is no way to get the address of a segment-accessed variable 423 * so we store a self-referential pointer at the base of the per-cpu 424 * data area and add the appropriate offset. 425 */ 426 /* JG movl? */ 427 movq $gd_common_tssd, %rdi 428 /* JG name for "%gs:0"? */ 429 addq %gs:0, %rdi 430 431 /* 432 * Move the correct TSS descriptor into the GDT slot, then reload 433 * ltr. 434 */ 4352: 436 /* JG */ 437 movl %rcx,PCPU(private_tss) /* mark/unmark private tss */ 438 movq PCPU(tss_gdt), %rbx /* entry in GDT */ 439 movq 0(%rdi), %rax 440 movq %rax, 0(%rbx) 441 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */ 442 ltr %si 443#endif 444 4453: 446 /* 447 * Restore the user %gs and %fs 448 */ 449 movq PCB_FSBASE(%rdx),%r9 450 cmpq PCPU(user_fs),%r9 451 je 4f 452 movq %rdx,%r10 453 movq %r9,PCPU(user_fs) 454 movl $MSR_FSBASE,%ecx 455 movl PCB_FSBASE(%r10),%eax 456 movl PCB_FSBASE+4(%r10),%edx 457 wrmsr 458 movq %r10,%rdx 4594: 460 movq PCB_GSBASE(%rdx),%r9 461 cmpq PCPU(user_gs),%r9 462 je 5f 463 movq %rdx,%r10 464 movq %r9,PCPU(user_gs) 465 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */ 466 movl PCB_GSBASE(%r10),%eax 467 movl PCB_GSBASE+4(%r10),%edx 468 wrmsr 469 movq %r10,%rdx 4705: 471 472 /* 473 * Restore general registers. %rbx is restored later. 474 */ 475 movq PCB_RSP(%rdx), %rsp 476 movq PCB_RBP(%rdx), %rbp 477 movq PCB_R12(%rdx), %r12 478 movq PCB_R13(%rdx), %r13 479 movq PCB_R14(%rdx), %r14 480 movq PCB_R15(%rdx), %r15 481 movq PCB_RIP(%rdx), %rax 482 movq %rax, (%rsp) 483 movw $KDSEL,%ax 484 movw %ax,%es 485 486#if 0 /* JG */ 487 /* 488 * Restore the user LDT if we have one 489 */ 490 cmpl $0, PCB_USERLDT(%edx) 491 jnz 1f 492 movl _default_ldt,%eax 493 cmpl PCPU(currentldt),%eax 494 je 2f 495 lldt _default_ldt 496 movl %eax,PCPU(currentldt) 497 jmp 2f 4981: pushl %edx 499 call set_user_ldt 500 popl %edx 5012: 502#endif 503#if 0 /* JG */ 504 /* 505 * Restore the user TLS if we have one 506 */ 507 pushl %edx 508 call set_user_TLS 509 popl %edx 510#endif 511 512 /* 513 * Restore the DEBUG register state if necessary. 514 */ 515 movq PCB_FLAGS(%rdx),%rax 516 andq $PCB_DBREGS,%rax 517 jz 1f /* no, skip over */ 518 movq PCB_DR6(%rdx),%rax /* yes, do the restore */ 519 movq %rax,%dr6 520 movq PCB_DR3(%rdx),%rax 521 movq %rax,%dr3 522 movq PCB_DR2(%rdx),%rax 523 movq %rax,%dr2 524 movq PCB_DR1(%rdx),%rax 525 movq %rax,%dr1 526 movq PCB_DR0(%rdx),%rax 527 movq %rax,%dr0 528 movq %dr7,%rax /* load dr7 so as not to disturb */ 529 /* JG correct value? */ 530 andq $0x0000fc00,%rax /* reserved bits */ 531 /* JG we've got more registers on x86_64 */ 532 movq PCB_DR7(%rdx),%rcx 533 /* JG correct value? */ 534 andq $~0x0000fc00,%rcx 535 orq %rcx,%rax 536 movq %rax,%dr7 537 538 /* 539 * Clear the QUICKRET flag when restoring a user process context 540 * so we don't try to do a quick syscall return. 541 */ 5421: 543 andl $~RQF_QUICKRET,PCPU(reqflags) 544 movq %rbx,%rax 545 movq PCB_RBX(%rdx),%rbx 546 ret 547 548/* 549 * savectx(struct pcb *pcb) 550 * 551 * Update pcb, saving current processor state. 552 */ 553ENTRY(savectx) 554 /* fetch PCB */ 555 /* JG use %rdi instead of %rcx everywhere? */ 556 movq %rdi,%rcx 557 558 /* caller's return address - child won't execute this routine */ 559 movq (%rsp),%rax 560 movq %rax,PCB_RIP(%rcx) 561 562 movq %cr3,%rax 563 movq %rax,PCB_CR3(%rcx) 564 565 movq %rbx,PCB_RBX(%rcx) 566 movq %rsp,PCB_RSP(%rcx) 567 movq %rbp,PCB_RBP(%rcx) 568 movq %r12,PCB_R12(%rcx) 569 movq %r13,PCB_R13(%rcx) 570 movq %r14,PCB_R14(%rcx) 571 movq %r15,PCB_R15(%rcx) 572 573#if 1 574 /* 575 * If npxthread == NULL, then the npx h/w state is irrelevant and the 576 * state had better already be in the pcb. This is true for forks 577 * but not for dumps (the old book-keeping with FP flags in the pcb 578 * always lost for dumps because the dump pcb has 0 flags). 579 * 580 * If npxthread != NULL, then we have to save the npx h/w state to 581 * npxthread's pcb and copy it to the requested pcb, or save to the 582 * requested pcb and reload. Copying is easier because we would 583 * have to handle h/w bugs for reloading. We used to lose the 584 * parent's npx state for forks by forgetting to reload. 585 */ 586 movq PCPU(npxthread),%rax 587 testq %rax,%rax 588 jz 1f 589 590 pushq %rcx /* target pcb */ 591 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */ 592 pushq %rax 593 594 movq %rax,%rdi 595 call npxsave 596 597 popq %rax 598 popq %rcx 599 600 movq $PCB_SAVEFPU_SIZE,%rdx 601 leaq PCB_SAVEFPU(%rcx),%rcx 602 movq %rcx,%rsi 603 movq %rax,%rdi 604 call bcopy 605#endif 606 6071: 608 ret 609 610/* 611 * cpu_idle_restore() (current thread in %rax on entry) (one-time execution) 612 * 613 * Don't bother setting up any regs other than %rbp so backtraces 614 * don't die. This restore function is used to bootstrap into the 615 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for 616 * switching. 617 * 618 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3. 619 * This only occurs during system boot so no special handling is 620 * required for migration. 621 * 622 * If we are an AP we have to call ap_init() before jumping to 623 * cpu_idle(). ap_init() will synchronize with the BP and finish 624 * setting up various ncpu-dependant globaldata fields. This may 625 * happen on UP as well as SMP if we happen to be simulating multiple 626 * cpus. 627 */ 628ENTRY(cpu_idle_restore) 629 /* cli */ 630 movq KPML4phys,%rcx 631 /* JG xor? */ 632 movq $0,%rbp 633 /* JG push RBP? */ 634 pushq $0 635 movq %rcx,%cr3 636 cmpl $0,PCPU(cpuid) 637 je 1f 638 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 639 orl $TDF_RUNNING,TD_FLAGS(%rax) /* manual, no switch_return */ 640 call ap_init 641 /* 642 * ap_init can decide to enable interrupts early, but otherwise, or if 643 * we are UP, do it here. 644 */ 645 sti 646 jmp cpu_idle 647 648 /* 649 * cpu 0's idle thread entry for the first time must use normal 650 * lwkt_switch_return() semantics or a pending cpu migration on 651 * thread0 will deadlock. 652 */ 6531: 654 sti 655 pushq %rax 656 movq %rbx,%rdi 657 call lwkt_switch_return 658 popq %rax 659 jmp cpu_idle 660 661/* 662 * cpu_kthread_restore() (current thread is %rax on entry, previous is %rbx) 663 * (one-time execution) 664 * 665 * Don't bother setting up any regs other then %rbp so backtraces 666 * don't die. This restore function is used to bootstrap into an 667 * LWKT based kernel thread only. cpu_lwkt_switch() will be used 668 * after this. 669 * 670 * Because this switch target does not 'return' to lwkt_switch() 671 * we have to call lwkt_switch_return(otd) to clean up otd. 672 * otd is in %ebx. 673 * 674 * Since all of our context is on the stack we are reentrant and 675 * we can release our critical section and enable interrupts early. 676 */ 677ENTRY(cpu_kthread_restore) 678 sti 679 movq KPML4phys,%rcx 680 movq TD_PCB(%rax),%r13 681 xorq %rbp,%rbp 682 movq %rcx,%cr3 683 684 /* 685 * rax and rbx come from the switchout code. Call 686 * lwkt_switch_return(otd). 687 * 688 * NOTE: unlike i386, %rsi and %rdi are not call-saved regs. 689 */ 690 pushq %rax 691 movq %rbx,%rdi 692 call lwkt_switch_return 693 popq %rax 694 decl TD_CRITCOUNT(%rax) 695 movq PCB_R12(%r13),%rdi /* argument to RBX function */ 696 movq PCB_RBX(%r13),%rax /* thread function */ 697 /* note: top of stack return address inherited by function */ 698 jmp *%rax 699 700/* 701 * cpu_lwkt_switch(struct thread *) 702 * 703 * Standard LWKT switching function. Only non-scratch registers are 704 * saved and we don't bother with the MMU state or anything else. 705 * 706 * This function is always called while in a critical section. 707 * 708 * There is a one-instruction window where curthread is the new 709 * thread but %rsp still points to the old thread's stack, but 710 * we are protected by a critical section so it is ok. 711 */ 712ENTRY(cpu_lwkt_switch) 713 pushq %rbp /* JG note: GDB hacked to locate ebp rel to td_sp */ 714 pushq %rbx 715 movq PCPU(curthread),%rbx /* becomes old thread in restore */ 716 pushq %r12 717 pushq %r13 718 pushq %r14 719 pushq %r15 720 pushfq 721 cli 722 723#if 1 724 /* 725 * Save the FP state if we have used the FP. Note that calling 726 * npxsave will NULL out PCPU(npxthread). 727 * 728 * We have to deal with the FP state for LWKT threads in case they 729 * happen to get preempted or block while doing an optimized 730 * bzero/bcopy/memcpy. 731 */ 732 cmpq %rbx,PCPU(npxthread) 733 jne 1f 734 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 735 movq TD_SAVEFPU(%rbx),%rdi 736 call npxsave /* do it in a big C function */ 737 movq %r12,%rdi /* restore %rdi */ 7381: 739#endif 740 741 movq %rdi,%rax /* switch to this thread */ 742 pushq $cpu_lwkt_restore 743 movq %rsp,TD_SP(%rbx) 744 /* 745 * %rax contains new thread, %rbx contains old thread. 746 */ 747 movq %rax,PCPU(curthread) 748 movq TD_SP(%rax),%rsp 749 ret 750 751/* 752 * cpu_lwkt_restore() (current thread in %rax on entry) 753 * 754 * Standard LWKT restore function. This function is always called 755 * while in a critical section. 756 * 757 * Warning: due to preemption the restore function can be used to 758 * 'return' to the original thread. Interrupt disablement must be 759 * protected through the switch so we cannot run splz here. 760 * 761 * YYY we theoretically do not need to load KPML4phys into cr3, but if 762 * so we need a way to detect when the PTD we are using is being 763 * deleted due to a process exiting. 764 */ 765ENTRY(cpu_lwkt_restore) 766 movq KPML4phys,%rcx /* YYY borrow but beware desched/cpuchg/exit */ 767 movq %cr3,%rdx 768#if 1 769 cmpq %rcx,%rdx 770 je 1f 771#endif 772 movq %rcx,%cr3 7731: 774 /* 775 * Safety, clear RSP0 in the tss so it isn't pointing at the 776 * previous thread's kstack (if a heavy weight user thread). 777 * RSP0 should only be used in ring 3 transitions and kernel 778 * threads run in ring 0 so there should be none. 779 */ 780 xorq %rdx,%rdx 781 movq %rdx, PCPU(common_tss) + TSS_RSP0 782 783 /* 784 * NOTE: %rbx is the previous thread and %rax is the new thread. 785 * %rbx is retained throughout so we can return it. 786 * 787 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 788 */ 789 movq %rbx,%rax 790 popfq 791 popq %r15 792 popq %r14 793 popq %r13 794 popq %r12 795 popq %rbx 796 popq %rbp 797 ret 798