1/* 2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved. 3 * Copyright (c) 2008 Jordan Gordeev. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Matthew Dillon <dillon@backplane.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * Copyright (c) 1990 The Regents of the University of California. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * William Jolitz. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the University of 52 * California, Berkeley and its contributors. 53 * 4. Neither the name of the University nor the names of its contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 67 * SUCH DAMAGE. 68 * 69 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $ 70 */ 71 72//#include "use_npx.h" 73 74#include <sys/rtprio.h> 75 76#include <machine/asmacros.h> 77#include <machine/segments.h> 78 79#include <machine/pmap.h> 80#if JG 81#include <machine_base/apic/apicreg.h> 82#endif 83#include <machine/lock.h> 84 85#include "assym.s" 86 87#if defined(SMP) 88#define MPLOCKED lock ; 89#else 90#define MPLOCKED 91#endif 92 93 .data 94 95 .globl panic 96 .globl lwkt_switch_return 97 98#if defined(SWTCH_OPTIM_STATS) 99 .globl swtch_optim_stats, tlb_flush_count 100swtch_optim_stats: .long 0 /* number of _swtch_optims */ 101tlb_flush_count: .long 0 102#endif 103 104 .text 105 106 107/* 108 * cpu_heavy_switch(struct thread *next_thread) 109 * 110 * Switch from the current thread to a new thread. This entry 111 * is normally called via the thread->td_switch function, and will 112 * only be called when the current thread is a heavy weight process. 113 * 114 * Some instructions have been reordered to reduce pipeline stalls. 115 * 116 * YYY disable interrupts once giant is removed. 117 */ 118ENTRY(cpu_heavy_switch) 119 /* 120 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15). 121 */ 122 movq PCPU(curthread),%rcx 123 /* On top of the stack is the return adress. */ 124 movq (%rsp),%rax /* (reorder optimization) */ 125 movq TD_PCB(%rcx),%rdx /* RDX = PCB */ 126 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */ 127 movq %rbx,PCB_RBX(%rdx) 128 movq %rsp,PCB_RSP(%rdx) 129 movq %rbp,PCB_RBP(%rdx) 130 movq %r12,PCB_R12(%rdx) 131 movq %r13,PCB_R13(%rdx) 132 movq %r14,PCB_R14(%rdx) 133 movq %r15,PCB_R15(%rdx) 134 135 /* 136 * Clear the cpu bit in the pmap active mask. The restore 137 * function will set the bit in the pmap active mask. 138 * 139 * Special case: when switching between threads sharing the 140 * same vmspace if we avoid clearing the bit we do not have 141 * to reload %cr3 (if we clear the bit we could race page 142 * table ops done by other threads and would have to reload 143 * %cr3, because those ops will not know to IPI us). 144 */ 145 movq %rcx,%rbx /* RBX = oldthread */ 146 movq TD_LWP(%rcx),%rcx /* RCX = oldlwp */ 147 movq TD_LWP(%rdi),%r13 /* R13 = newlwp */ 148 movq LWP_VMSPACE(%rcx), %rcx /* RCX = oldvmspace */ 149 testq %r13,%r13 /* might not be a heavy */ 150 jz 1f 151 cmpq LWP_VMSPACE(%r13),%rcx /* same vmspace? */ 152 je 2f 1531: 154 movslq PCPU(cpuid), %rax 155 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx) 1562: 157 158 /* 159 * Push the LWKT switch restore function, which resumes a heavy 160 * weight process. Note that the LWKT switcher is based on 161 * TD_SP, while the heavy weight process switcher is based on 162 * PCB_RSP. TD_SP is usually two ints pushed relative to 163 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore. 164 */ 165 pushfq 166 movq $cpu_heavy_restore, %rax 167 pushq %rax 168 movq %rsp,TD_SP(%rbx) 169 170 /* 171 * Save debug regs if necessary 172 */ 173 movq PCB_FLAGS(%rdx),%rax 174 andq $PCB_DBREGS,%rax 175 jz 1f /* no, skip over */ 176 movq %dr7,%rax /* yes, do the save */ 177 movq %rax,PCB_DR7(%rdx) 178 /* JG correct value? */ 179 andq $0x0000fc00, %rax /* disable all watchpoints */ 180 movq %rax,%dr7 181 movq %dr6,%rax 182 movq %rax,PCB_DR6(%rdx) 183 movq %dr3,%rax 184 movq %rax,PCB_DR3(%rdx) 185 movq %dr2,%rax 186 movq %rax,PCB_DR2(%rdx) 187 movq %dr1,%rax 188 movq %rax,PCB_DR1(%rdx) 189 movq %dr0,%rax 190 movq %rax,PCB_DR0(%rdx) 1911: 192 193#if 1 194 /* 195 * Save the FP state if we have used the FP. Note that calling 196 * npxsave will NULL out PCPU(npxthread). 197 */ 198 cmpq %rbx,PCPU(npxthread) 199 jne 1f 200 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 201 movq TD_SAVEFPU(%rbx),%rdi 202 call npxsave /* do it in a big C function */ 203 movq %r12,%rdi /* restore %rdi */ 2041: 205#endif 206 207 /* 208 * Switch to the next thread, which was passed as an argument 209 * to cpu_heavy_switch(). The argument is in %rdi. 210 * Set the current thread, load the stack pointer, 211 * and 'ret' into the switch-restore function. 212 * 213 * The switch restore function expects the new thread to be in %rax 214 * and the old one to be in %rbx. 215 * 216 * There is a one-instruction window where curthread is the new 217 * thread but %rsp still points to the old thread's stack, but 218 * we are protected by a critical section so it is ok. 219 */ 220 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */ 221 movq %rax,PCPU(curthread) 222 movq TD_SP(%rax),%rsp 223 ret 224 225/* 226 * cpu_exit_switch(struct thread *next) 227 * 228 * The switch function is changed to this when a thread is going away 229 * for good. We have to ensure that the MMU state is not cached, and 230 * we don't bother saving the existing thread state before switching. 231 * 232 * At this point we are in a critical section and this cpu owns the 233 * thread's token, which serves as an interlock until the switchout is 234 * complete. 235 */ 236ENTRY(cpu_exit_switch) 237 /* 238 * Get us out of the vmspace 239 */ 240 movq KPML4phys,%rcx 241 movq %cr3,%rax 242 cmpq %rcx,%rax 243 je 1f 244 /* JG no increment of statistics counters? see cpu_heavy_restore */ 245 movq %rcx,%cr3 2461: 247 movq PCPU(curthread),%rbx 248 249 /* 250 * If this is a process/lwp, deactivate the pmap after we've 251 * switched it out. 252 */ 253 movq TD_LWP(%rbx),%rcx 254 testq %rcx,%rcx 255 jz 2f 256 movslq PCPU(cpuid), %rax 257 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 258 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx) 2592: 260 /* 261 * Switch to the next thread. RET into the restore function, which 262 * expects the new thread in RAX and the old in RBX. 263 * 264 * There is a one-instruction window where curthread is the new 265 * thread but %rsp still points to the old thread's stack, but 266 * we are protected by a critical section so it is ok. 267 */ 268 movq %rdi,%rax 269 movq %rax,PCPU(curthread) 270 movq TD_SP(%rax),%rsp 271 ret 272 273/* 274 * cpu_heavy_restore() (current thread in %rax on entry) 275 * 276 * Restore the thread after an LWKT switch. This entry is normally 277 * called via the LWKT switch restore function, which was pulled 278 * off the thread stack and jumped to. 279 * 280 * This entry is only called if the thread was previously saved 281 * using cpu_heavy_switch() (the heavy weight process thread switcher), 282 * or when a new process is initially scheduled. 283 * 284 * NOTE: The lwp may be in any state, not necessarily LSRUN, because 285 * a preemption switch may interrupt the process and then return via 286 * cpu_heavy_restore. 287 * 288 * YYY theoretically we do not have to restore everything here, a lot 289 * of this junk can wait until we return to usermode. But for now 290 * we restore everything. 291 * 292 * YYY the PCB crap is really crap, it makes startup a bitch because 293 * we can't switch away. 294 * 295 * YYY note: spl check is done in mi_switch when it splx()'s. 296 */ 297 298ENTRY(cpu_heavy_restore) 299 popfq 300 movq TD_LWP(%rax),%rcx 301 302#if defined(SWTCH_OPTIM_STATS) 303 incl _swtch_optim_stats 304#endif 305 /* 306 * Tell the pmap that our cpu is using the VMSPACE now. We cannot 307 * safely test/reload %cr3 until after we have set the bit in the 308 * pmap (remember, we do not hold the MP lock in the switch code). 309 * 310 * Also note that when switching between two lwps sharing the 311 * same vmspace we have already avoided clearing the cpu bit 312 * in pm_active. If we had cleared it other cpus would not know 313 * to IPI us and we would have to unconditionally reload %cr3. 314 * 315 * Also note that if the pmap is undergoing an atomic inval/mod 316 * that is unaware that our cpu has been added to it we have to 317 * wait for it to complete before we can continue. 318 */ 319 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 320 movq PCPU(cpumask), %rsi 321 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE(%rcx) 322#ifdef SMP 323 btq $CPUMASK_BIT,VM_PMAP+PM_ACTIVE(%rcx) 324 jnc 1f 325 pushq %rax 326 movq %rcx,%rdi 327 call pmap_interlock_wait /* pmap_interlock_wait(vm) */ 328 popq %rax 3291: 330#endif 331 332 /* 333 * Restore the MMU address space. If it is the same as the last 334 * thread we don't have to invalidate the tlb (i.e. reload cr3). 335 * YYY which naturally also means that the PM_ACTIVE bit had better 336 * already have been set before we set it above, check? YYY 337 */ 338 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 339 movq %cr3,%rsi 340 movq PCB_CR3(%rdx),%rcx 341 cmpq %rsi,%rcx 342 je 4f 343#if defined(SWTCH_OPTIM_STATS) 344 decl _swtch_optim_stats 345 incl _tlb_flush_count 346#endif 347 movq %rcx,%cr3 3484: 349 /* 350 * NOTE: %rbx is the previous thread and %eax is the new thread. 351 * %rbx is retained throughout so we can return it. 352 * 353 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 354 */ 355 356 /* 357 * Deal with the PCB extension, restore the private tss 358 */ 359 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */ 360 movq $1,%rcx /* maybe mark use of a private tss */ 361 testq %rdi,%rdi 362#if JG 363 jnz 2f 364#endif 365 366 /* 367 * Going back to the common_tss. We may need to update TSS_RSP0 368 * which sets the top of the supervisor stack when entering from 369 * usermode. The PCB is at the top of the stack but we need another 370 * 16 bytes to take vm86 into account. 371 */ 372 movq %rdx,%rcx 373 /*leaq -TF_SIZE(%rdx),%rcx*/ 374 movq %rcx, PCPU(common_tss) + TSS_RSP0 375 376#if JG 377 cmpl $0,PCPU(private_tss) /* don't have to reload if */ 378 je 3f /* already using the common TSS */ 379 380 /* JG? */ 381 subq %rcx,%rcx /* unmark use of private tss */ 382 383 /* 384 * Get the address of the common TSS descriptor for the ltr. 385 * There is no way to get the address of a segment-accessed variable 386 * so we store a self-referential pointer at the base of the per-cpu 387 * data area and add the appropriate offset. 388 */ 389 /* JG movl? */ 390 movq $gd_common_tssd, %rdi 391 /* JG name for "%gs:0"? */ 392 addq %gs:0, %rdi 393 394 /* 395 * Move the correct TSS descriptor into the GDT slot, then reload 396 * ltr. 397 */ 3982: 399 /* JG */ 400 movl %rcx,PCPU(private_tss) /* mark/unmark private tss */ 401 movq PCPU(tss_gdt), %rbx /* entry in GDT */ 402 movq 0(%rdi), %rax 403 movq %rax, 0(%rbx) 404 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */ 405 ltr %si 406#endif 407 4083: 409 /* 410 * Restore the user %gs and %fs 411 */ 412 movq PCB_FSBASE(%rdx),%r9 413 cmpq PCPU(user_fs),%r9 414 je 4f 415 movq %rdx,%r10 416 movq %r9,PCPU(user_fs) 417 movl $MSR_FSBASE,%ecx 418 movl PCB_FSBASE(%r10),%eax 419 movl PCB_FSBASE+4(%r10),%edx 420 wrmsr 421 movq %r10,%rdx 4224: 423 movq PCB_GSBASE(%rdx),%r9 424 cmpq PCPU(user_gs),%r9 425 je 5f 426 movq %rdx,%r10 427 movq %r9,PCPU(user_gs) 428 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */ 429 movl PCB_GSBASE(%r10),%eax 430 movl PCB_GSBASE+4(%r10),%edx 431 wrmsr 432 movq %r10,%rdx 4335: 434 435 /* 436 * Restore general registers. %rbx is restored later. 437 */ 438 movq PCB_RSP(%rdx), %rsp 439 movq PCB_RBP(%rdx), %rbp 440 movq PCB_R12(%rdx), %r12 441 movq PCB_R13(%rdx), %r13 442 movq PCB_R14(%rdx), %r14 443 movq PCB_R15(%rdx), %r15 444 movq PCB_RIP(%rdx), %rax 445 movq %rax, (%rsp) 446 447#if JG 448 /* 449 * Restore the user LDT if we have one 450 */ 451 cmpl $0, PCB_USERLDT(%edx) 452 jnz 1f 453 movl _default_ldt,%eax 454 cmpl PCPU(currentldt),%eax 455 je 2f 456 lldt _default_ldt 457 movl %eax,PCPU(currentldt) 458 jmp 2f 4591: pushl %edx 460 call set_user_ldt 461 popl %edx 4622: 463#endif 464#if JG 465 /* 466 * Restore the user TLS if we have one 467 */ 468 pushl %edx 469 call set_user_TLS 470 popl %edx 471#endif 472 473 /* 474 * Restore the DEBUG register state if necessary. 475 */ 476 movq PCB_FLAGS(%rdx),%rax 477 andq $PCB_DBREGS,%rax 478 jz 1f /* no, skip over */ 479 movq PCB_DR6(%rdx),%rax /* yes, do the restore */ 480 movq %rax,%dr6 481 movq PCB_DR3(%rdx),%rax 482 movq %rax,%dr3 483 movq PCB_DR2(%rdx),%rax 484 movq %rax,%dr2 485 movq PCB_DR1(%rdx),%rax 486 movq %rax,%dr1 487 movq PCB_DR0(%rdx),%rax 488 movq %rax,%dr0 489 movq %dr7,%rax /* load dr7 so as not to disturb */ 490 /* JG correct value? */ 491 andq $0x0000fc00,%rax /* reserved bits */ 492 /* JG we've got more registers on x86_64 */ 493 movq PCB_DR7(%rdx),%rcx 494 /* JG correct value? */ 495 andq $~0x0000fc00,%rcx 496 orq %rcx,%rax 497 movq %rax,%dr7 4981: 499 movq %rbx,%rax 500 movq PCB_RBX(%rdx),%rbx 501 ret 502 503/* 504 * savectx(struct pcb *pcb) 505 * 506 * Update pcb, saving current processor state. 507 */ 508ENTRY(savectx) 509 /* fetch PCB */ 510 /* JG use %rdi instead of %rcx everywhere? */ 511 movq %rdi,%rcx 512 513 /* caller's return address - child won't execute this routine */ 514 movq (%rsp),%rax 515 movq %rax,PCB_RIP(%rcx) 516 517 movq %cr3,%rax 518 movq %rax,PCB_CR3(%rcx) 519 520 movq %rbx,PCB_RBX(%rcx) 521 movq %rsp,PCB_RSP(%rcx) 522 movq %rbp,PCB_RBP(%rcx) 523 movq %r12,PCB_R12(%rcx) 524 movq %r13,PCB_R13(%rcx) 525 movq %r14,PCB_R14(%rcx) 526 movq %r15,PCB_R15(%rcx) 527 528#if 1 529 /* 530 * If npxthread == NULL, then the npx h/w state is irrelevant and the 531 * state had better already be in the pcb. This is true for forks 532 * but not for dumps (the old book-keeping with FP flags in the pcb 533 * always lost for dumps because the dump pcb has 0 flags). 534 * 535 * If npxthread != NULL, then we have to save the npx h/w state to 536 * npxthread's pcb and copy it to the requested pcb, or save to the 537 * requested pcb and reload. Copying is easier because we would 538 * have to handle h/w bugs for reloading. We used to lose the 539 * parent's npx state for forks by forgetting to reload. 540 */ 541 movq PCPU(npxthread),%rax 542 testq %rax,%rax 543 jz 1f 544 545 pushq %rcx /* target pcb */ 546 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */ 547 pushq %rax 548 549 movq %rax,%rdi 550 call npxsave 551 552 popq %rax 553 popq %rcx 554 555 movq $PCB_SAVEFPU_SIZE,%rdx 556 leaq PCB_SAVEFPU(%rcx),%rcx 557 movq %rcx,%rsi 558 movq %rax,%rdi 559 call bcopy 560#endif 561 5621: 563 ret 564 565/* 566 * cpu_idle_restore() (current thread in %rax on entry) (one-time execution) 567 * 568 * Don't bother setting up any regs other than %rbp so backtraces 569 * don't die. This restore function is used to bootstrap into the 570 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for 571 * switching. 572 * 573 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3. 574 * This only occurs during system boot so no special handling is 575 * required for migration. 576 * 577 * If we are an AP we have to call ap_init() before jumping to 578 * cpu_idle(). ap_init() will synchronize with the BP and finish 579 * setting up various ncpu-dependant globaldata fields. This may 580 * happen on UP as well as SMP if we happen to be simulating multiple 581 * cpus. 582 */ 583ENTRY(cpu_idle_restore) 584 /* cli */ 585 movq KPML4phys,%rcx 586 /* JG xor? */ 587 movq $0,%rbp 588 /* JG push RBP? */ 589 pushq $0 590 movq %rcx,%cr3 591 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 592#if 0 593 orl $TDF_RUNNING,TD_FLAGS(%rax) 594#endif 595#ifdef SMP 596 cmpl $0,PCPU(cpuid) 597 je 1f 598 call ap_init 5991: 600#endif 601 /* 602 * ap_init can decide to enable interrupts early, but otherwise, or if 603 * we are UP, do it here. 604 */ 605 sti 606 jmp cpu_idle 607 608/* 609 * cpu_kthread_restore() (current thread is %rax on entry) (one-time execution) 610 * 611 * Don't bother setting up any regs other then %rbp so backtraces 612 * don't die. This restore function is used to bootstrap into an 613 * LWKT based kernel thread only. cpu_lwkt_switch() will be used 614 * after this. 615 * 616 * Because this switch target does not 'return' to lwkt_switch() 617 * we have to call lwkt_switch_return(otd) to clean up otd. 618 * otd is in %ebx. 619 * 620 * Since all of our context is on the stack we are reentrant and 621 * we can release our critical section and enable interrupts early. 622 */ 623ENTRY(cpu_kthread_restore) 624 sti 625 movq KPML4phys,%rcx 626 movq TD_PCB(%rax),%r13 627 /* JG "movq $0, %rbp"? "xorq %rbp, %rbp"? */ 628 movq $0,%rbp 629 movq %rcx,%cr3 630 631 /* 632 * rax and rbx come from the switchout code. Call 633 * lwkt_switch_return(otd). 634 * 635 * NOTE: unlike i386, %rsi and %rdi are not call-saved regs. 636 */ 637 pushq %rax 638 movq %rbx,%rdi 639 call lwkt_switch_return 640 popq %rax 641#if 0 642 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 643 orl $TDF_RUNNING,TD_FLAGS(%rax) 644#endif 645 decl TD_CRITCOUNT(%rax) 646 movq PCB_R12(%r13),%rdi /* argument to RBX function */ 647 movq PCB_RBX(%r13),%rax /* thread function */ 648 /* note: top of stack return address inherited by function */ 649 jmp *%rax 650 651/* 652 * cpu_lwkt_switch(struct thread *) 653 * 654 * Standard LWKT switching function. Only non-scratch registers are 655 * saved and we don't bother with the MMU state or anything else. 656 * 657 * This function is always called while in a critical section. 658 * 659 * There is a one-instruction window where curthread is the new 660 * thread but %rsp still points to the old thread's stack, but 661 * we are protected by a critical section so it is ok. 662 */ 663ENTRY(cpu_lwkt_switch) 664 pushq %rbp /* JG note: GDB hacked to locate ebp rel to td_sp */ 665 pushq %rbx 666 movq PCPU(curthread),%rbx 667 pushq %r12 668 pushq %r13 669 pushq %r14 670 pushq %r15 671 pushfq 672 673#if 1 674 /* 675 * Save the FP state if we have used the FP. Note that calling 676 * npxsave will NULL out PCPU(npxthread). 677 * 678 * We have to deal with the FP state for LWKT threads in case they 679 * happen to get preempted or block while doing an optimized 680 * bzero/bcopy/memcpy. 681 */ 682 cmpq %rbx,PCPU(npxthread) 683 jne 1f 684 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 685 movq TD_SAVEFPU(%rbx),%rdi 686 call npxsave /* do it in a big C function */ 687 movq %r12,%rdi /* restore %rdi */ 6881: 689#endif 690 691 movq %rdi,%rax /* switch to this thread */ 692 pushq $cpu_lwkt_restore 693 movq %rsp,TD_SP(%rbx) 694 movq %rax,PCPU(curthread) 695 movq TD_SP(%rax),%rsp 696 697 /* 698 * %rax contains new thread, %rbx contains old thread. 699 */ 700 ret 701 702/* 703 * cpu_lwkt_restore() (current thread in %rax on entry) 704 * 705 * Standard LWKT restore function. This function is always called 706 * while in a critical section. 707 * 708 * Warning: due to preemption the restore function can be used to 709 * 'return' to the original thread. Interrupt disablement must be 710 * protected through the switch so we cannot run splz here. 711 * 712 * YYY we theoretically do not need to load KPML4phys into cr3, but if 713 * so we need a way to detect when the PTD we are using is being 714 * deleted due to a process exiting. 715 */ 716ENTRY(cpu_lwkt_restore) 717 movq KPML4phys,%rcx /* YYY borrow but beware desched/cpuchg/exit */ 718 movq %cr3,%rdx 719 cmpq %rcx,%rdx 720 je 1f 721 movq %rcx,%cr3 7221: 723 /* 724 * NOTE: %rbx is the previous thread and %eax is the new thread. 725 * %rbx is retained throughout so we can return it. 726 * 727 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 728 */ 729 movq %rbx,%rax 730 popfq 731 popq %r15 732 popq %r14 733 popq %r13 734 popq %r12 735 popq %rbx 736 popq %rbp 737 ret 738