1 /*- 2 * Copyright (c) 1982, 1986 The Regents of the University of California. 3 * Copyright (c) 1989, 1990 William Jolitz 4 * Copyright (c) 1994 John Dyson 5 * Copyright (c) 2008-2018 The DragonFly Project. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department, and William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: @(#)vm_machdep.c 7.3 (Berkeley) 5/13/91 41 * Utah $Hdr: vm_machdep.c 1.16.1.1 89/06/23$ 42 * $FreeBSD: src/sys/i386/i386/vm_machdep.c,v 1.132.2.9 2003/01/25 19:02:23 dillon Exp $ 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/proc.h> 49 #include <sys/buf.h> 50 #include <sys/interrupt.h> 51 #include <sys/vnode.h> 52 #include <sys/vmmeter.h> 53 #include <sys/kernel.h> 54 #include <sys/sysctl.h> 55 #include <sys/unistd.h> 56 #include <sys/lwp.h> 57 58 #include <machine/clock.h> 59 #include <machine/cpu.h> 60 #include <machine/md_var.h> 61 #include <machine/smp.h> 62 #include <machine/pcb.h> 63 #include <machine/pcb_ext.h> 64 #include <machine/segments.h> 65 #include <machine/globaldata.h> /* npxthread */ 66 #include <machine/specialreg.h> 67 68 #include <vm/vm.h> 69 #include <vm/vm_param.h> 70 #include <sys/lock.h> 71 #include <vm/vm_kern.h> 72 #include <vm/vm_page.h> 73 #include <vm/vm_map.h> 74 #include <vm/vm_extern.h> 75 76 #include <sys/thread2.h> 77 78 #include <bus/isa/isa.h> 79 80 static void cpu_reset_real (void); 81 82 static int spectre_mitigation = -1; 83 static int spectre_support = 0; 84 static int spectre_mode = 0; 85 SYSCTL_INT(_machdep, OID_AUTO, spectre_mode, CTLFLAG_RD, 86 &spectre_mode, 0, "current Spectre enablements"); 87 88 static int mds_mitigation = -1; 89 static int mds_support = 0; 90 static int mds_mode = 0; 91 SYSCTL_INT(_machdep, OID_AUTO, mds_mode, CTLFLAG_RD, 92 &mds_mode, 0, "current MDS enablements"); 93 94 /* 95 * Finish a fork operation, with lwp lp2 nearly set up. 96 * Copy and update the pcb, set up the stack so that the child 97 * ready to run and return to user mode. 98 */ 99 void 100 cpu_fork(struct lwp *lp1, struct lwp *lp2, int flags) 101 { 102 struct pcb *pcb2; 103 struct pmap *pmap2; 104 105 if ((flags & RFPROC) == 0) { 106 if ((flags & RFMEM) == 0) { 107 /* 108 * Unshare user LDT. > 1 test is MPSAFE. While 109 * it can potentially race a 2->1 transition, the 110 * worst that happens is that we do an unnecessary 111 * ldt replacement. 112 */ 113 struct pcb *pcb1 = lp1->lwp_thread->td_pcb; 114 struct pcb_ldt *pcb_ldt = pcb1->pcb_ldt; 115 116 if (pcb_ldt && pcb_ldt->ldt_refcnt > 1) { 117 pcb_ldt = user_ldt_alloc(pcb1,pcb_ldt->ldt_len); 118 user_ldt_free(pcb1); 119 pcb1->pcb_ldt = pcb_ldt; 120 set_user_ldt(pcb1); 121 } 122 } 123 return; 124 } 125 126 /* Ensure that lp1's pcb is up to date. */ 127 if (mdcpu->gd_npxthread == lp1->lwp_thread) 128 npxsave(lp1->lwp_thread->td_savefpu); 129 130 /* 131 * Copy lp1's PCB. This really only applies to the 132 * debug registers and FP state, but its faster to just copy the 133 * whole thing. Because we only save the PCB at switchout time, 134 * the register state may not be current. 135 */ 136 pcb2 = lp2->lwp_thread->td_pcb; 137 *pcb2 = *lp1->lwp_thread->td_pcb; 138 139 /* 140 * Create a new fresh stack for the new process. 141 * Copy the trap frame for the return to user mode as if from a 142 * syscall. This copies the user mode register values. 143 * 144 * pcb_rsp must allocate an additional call-return pointer below 145 * the trap frame which will be restored by cpu_heavy_restore from 146 * PCB_RIP, and the thread's td_sp pointer must allocate an 147 * additonal two quadwords below the pcb_rsp call-return pointer to 148 * hold the LWKT restore function pointer and rflags. 149 * 150 * The LWKT restore function pointer must be set to cpu_heavy_restore, 151 * which is our standard heavy-weight process switch-in function. 152 * YYY eventually we should shortcut fork_return and fork_trampoline 153 * to use the LWKT restore function directly so we can get rid of 154 * all the extra crap we are setting up. 155 */ 156 lp2->lwp_md.md_regs = (struct trapframe *)pcb2 - 1; 157 bcopy(lp1->lwp_md.md_regs, lp2->lwp_md.md_regs, sizeof(*lp2->lwp_md.md_regs)); 158 159 /* 160 * Set registers for trampoline to user mode. Leave space for the 161 * return address on stack. These are the kernel mode register values. 162 * 163 * Set the new pmap CR3. If the new process uses isolated VM spaces, 164 * also set the isolated CR3. 165 */ 166 pmap2 = vmspace_pmap(lp2->lwp_proc->p_vmspace); 167 pcb2->pcb_cr3 = vtophys(pmap2->pm_pml4); 168 if ((pcb2->pcb_flags & PCB_ISOMMU) && pmap2->pm_pmlpv_iso) { 169 pcb2->pcb_cr3_iso = vtophys(pmap2->pm_pml4_iso); 170 } else { 171 pcb2->pcb_flags &= ~PCB_ISOMMU; 172 pcb2->pcb_cr3_iso = 0; 173 } 174 175 #if 0 176 /* 177 * Per-process spectre mitigation (future) 178 */ 179 pcb2->pcb_flags &= ~(PCB_IBRS1 | PCB_IBRS2); 180 switch (spectre_mitigation) { 181 case 1: 182 pcb2->pcb_flags |= PCB_IBRS1; 183 break; 184 case 2: 185 pcb2->pcb_flags |= PCB_IBRS2; 186 break; 187 default: 188 break; 189 } 190 #endif 191 192 pcb2->pcb_rbx = (unsigned long)fork_return; /* fork_trampoline argument */ 193 pcb2->pcb_rbp = 0; 194 pcb2->pcb_rsp = (unsigned long)lp2->lwp_md.md_regs - sizeof(void *); 195 pcb2->pcb_r12 = (unsigned long)lp2; /* fork_trampoline argument */ 196 pcb2->pcb_r13 = 0; 197 pcb2->pcb_r14 = 0; 198 pcb2->pcb_r15 = 0; 199 pcb2->pcb_rip = (unsigned long)fork_trampoline; 200 lp2->lwp_thread->td_sp = (char *)(pcb2->pcb_rsp - sizeof(void *)); 201 *(u_int64_t *)lp2->lwp_thread->td_sp = PSL_USER; 202 lp2->lwp_thread->td_sp -= sizeof(void *); 203 *(void **)lp2->lwp_thread->td_sp = (void *)cpu_heavy_restore; 204 205 /* 206 * pcb2->pcb_ldt: duplicated below, if necessary. 207 * pcb2->pcb_savefpu: cloned above. 208 * pcb2->pcb_flags: cloned above 209 * pcb2->pcb_onfault: cloned above (always NULL here). 210 * pcb2->pcb_onfault_sp:cloned above (dont care) 211 */ 212 213 /* 214 * XXX don't copy the i/o pages. this should probably be fixed. 215 */ 216 pcb2->pcb_ext = NULL; 217 218 /* Copy the LDT, if necessary. */ 219 if (pcb2->pcb_ldt != NULL) { 220 if (flags & RFMEM) { 221 atomic_add_int(&pcb2->pcb_ldt->ldt_refcnt, 1); 222 } else { 223 pcb2->pcb_ldt = user_ldt_alloc(pcb2, 224 pcb2->pcb_ldt->ldt_len); 225 } 226 } 227 bcopy(&lp1->lwp_thread->td_tls, &lp2->lwp_thread->td_tls, 228 sizeof(lp2->lwp_thread->td_tls)); 229 /* 230 * Now, cpu_switch() can schedule the new lwp. 231 * pcb_rsp is loaded pointing to the cpu_switch() stack frame 232 * containing the return address when exiting cpu_switch. 233 * This will normally be to fork_trampoline(), which will have 234 * %rbx loaded with the new lwp's pointer. fork_trampoline() 235 * will set up a stack to call fork_return(lp, frame); to complete 236 * the return to user-mode. 237 */ 238 } 239 240 /* 241 * Prepare new lwp to return to the address specified in params. 242 */ 243 int 244 cpu_prepare_lwp(struct lwp *lp, struct lwp_params *params) 245 { 246 struct trapframe *regs = lp->lwp_md.md_regs; 247 void *bad_return = NULL; 248 int error; 249 250 regs->tf_rip = (long)params->lwp_func; 251 regs->tf_rsp = (long)params->lwp_stack; 252 /* Set up argument for function call */ 253 regs->tf_rdi = (long)params->lwp_arg; 254 255 /* 256 * Set up fake return address. As the lwp function may never return, 257 * we simply copy out a NULL pointer and force the lwp to receive 258 * a SIGSEGV if it returns anyways. 259 */ 260 regs->tf_rsp -= sizeof(void *); 261 error = copyout(&bad_return, (void *)regs->tf_rsp, sizeof(bad_return)); 262 if (error) 263 return (error); 264 265 cpu_set_fork_handler(lp, 266 (void (*)(void *, struct trapframe *))generic_lwp_return, lp); 267 return (0); 268 } 269 270 /* 271 * Intercept the return address from a freshly forked process that has NOT 272 * been scheduled yet. 273 * 274 * This is needed to make kernel threads stay in kernel mode. 275 */ 276 void 277 cpu_set_fork_handler(struct lwp *lp, void (*func)(void *, struct trapframe *), 278 void *arg) 279 { 280 /* 281 * Note that the trap frame follows the args, so the function 282 * is really called like this: func(arg, frame); 283 */ 284 lp->lwp_thread->td_pcb->pcb_rbx = (long)func; /* function */ 285 lp->lwp_thread->td_pcb->pcb_r12 = (long)arg; /* first arg */ 286 } 287 288 void 289 cpu_set_thread_handler(thread_t td, void (*rfunc)(void), void *func, void *arg) 290 { 291 td->td_pcb->pcb_rbx = (long)func; 292 td->td_pcb->pcb_r12 = (long)arg; 293 td->td_switch = cpu_lwkt_switch; 294 td->td_sp -= sizeof(void *); 295 *(void **)td->td_sp = rfunc; /* exit function on return */ 296 td->td_sp -= sizeof(void *); 297 *(void **)td->td_sp = cpu_kthread_restore; 298 } 299 300 void 301 cpu_lwp_exit(void) 302 { 303 struct thread *td = curthread; 304 struct pcb *pcb; 305 306 pcb = td->td_pcb; 307 308 /* Some x86 functionality was dropped */ 309 KKASSERT(pcb->pcb_ext == NULL); 310 311 /* 312 * disable all hardware breakpoints 313 */ 314 if (pcb->pcb_flags & PCB_DBREGS) { 315 reset_dbregs(); 316 pcb->pcb_flags &= ~PCB_DBREGS; 317 } 318 td->td_gd->gd_cnt.v_swtch++; 319 320 crit_enter_quick(td); 321 if (td->td_flags & TDF_TSLEEPQ) 322 tsleep_remove(td); 323 lwkt_deschedule_self(td); 324 lwkt_remove_tdallq(td); 325 cpu_thread_exit(); 326 } 327 328 /* 329 * Terminate the current thread. The caller must have already acquired 330 * the thread's rwlock and placed it on a reap list or otherwise notified 331 * a reaper of its existance. We set a special assembly switch function which 332 * releases td_rwlock after it has cleaned up the MMU state and switched 333 * out the stack. 334 * 335 * Must be caller from a critical section and with the thread descheduled. 336 */ 337 void 338 cpu_thread_exit(void) 339 { 340 npxexit(); 341 curthread->td_switch = cpu_exit_switch; 342 curthread->td_flags |= TDF_EXITING; 343 lwkt_switch(); 344 panic("cpu_thread_exit: lwkt_switch() unexpectedly returned"); 345 } 346 347 void 348 cpu_reset(void) 349 { 350 cpu_reset_real(); 351 } 352 353 static void 354 cpu_reset_real(void) 355 { 356 /* 357 * Attempt to do a CPU reset via the keyboard controller, 358 * do not turn off the GateA20, as any machine that fails 359 * to do the reset here would then end up in no man's land. 360 */ 361 362 #if !defined(BROKEN_KEYBOARD_RESET) 363 outb(IO_KBD + 4, 0xFE); 364 DELAY(500000); /* wait 0.5 sec to see if that did it */ 365 kprintf("Keyboard reset did not work, attempting CPU shutdown\n"); 366 DELAY(1000000); /* wait 1 sec for kprintf to complete */ 367 #endif 368 #if 0 /* JG */ 369 /* force a shutdown by unmapping entire address space ! */ 370 bzero((caddr_t) PTD, PAGE_SIZE); 371 #endif 372 373 /* "good night, sweet prince .... <THUNK!>" */ 374 cpu_invltlb(); 375 /* NOTREACHED */ 376 while(1); 377 } 378 379 static void 380 swi_vm(void *arg, void *frame) 381 { 382 if (busdma_swi_pending != 0) 383 busdma_swi(); 384 } 385 386 static void 387 swi_vm_setup(void *arg) 388 { 389 register_swi_mp(SWI_VM, swi_vm, NULL, "swi_vm", NULL, 0); 390 } 391 392 SYSINIT(swi_vm_setup, SI_BOOT2_MACHDEP, SI_ORDER_ANY, swi_vm_setup, NULL); 393 394 /* 395 * NOTE: This routine is also called after a successful microcode 396 * reload on cpu 0. 397 */ 398 void mitigation_vm_setup(void *arg); 399 400 /* 401 * Check for IBPB and IBRS support 402 * 403 * This bits also specify desired modes in the spectre_mitigation sysctl. 404 */ 405 #define IBRS_SUPPORTED 0x0001 406 #define STIBP_SUPPORTED 0x0002 407 #define IBPB_SUPPORTED 0x0004 408 #define IBRS_AUTO_SUPPORTED 0x0008 409 #define STIBP_AUTO_SUPPORTED 0x0010 410 #define IBRS_PREFERRED_REQUEST 0x0020 411 412 static 413 int 414 spectre_check_support(void) 415 { 416 uint32_t p[4]; 417 int rv = 0; 418 419 /* 420 * Spectre mitigation hw bits 421 * 422 * IBRS Indirect Branch Restricted Speculation (isolation) 423 * STIBP Single Thread Indirect Branch Prediction (isolation) 424 * IBPB Branch Prediction Barrier (barrier) 425 * 426 * IBRS and STIBP must be toggled (enabled on entry to kernel, 427 * disabled on exit, as well as disabled during any MWAIT/HLT). 428 * When *_AUTO bits are available, IBRS and STIBP may be left 429 * turned on and do not have to be toggled on kernel entry/exit. 430 * Be sure to clear before going idle (else hyperthread performance 431 * will drop). 432 * 433 * All this shit has enormous overhead. IBPB in particular, and 434 * non-auto modes are disabled by default. 435 */ 436 if (cpu_vendor_id == CPU_VENDOR_INTEL) { 437 p[0] = 0; 438 p[1] = 0; 439 p[2] = 0; 440 p[3] = 0; 441 cpuid_count(7, 0, p); 442 if (p[3] & CPUID_STDEXT3_IBPB) 443 rv |= IBRS_SUPPORTED | IBPB_SUPPORTED; 444 if (p[3] & CPUID_STDEXT3_STIBP) 445 rv |= STIBP_SUPPORTED; 446 447 /* 448 * 0x80000008 p[1] bit 12 indicates IBPB support 449 * 450 * This bit might be set even though STDEXT3_IBPB is not set. 451 */ 452 p[0] = 0; 453 p[1] = 0; 454 p[2] = 0; 455 p[3] = 0; 456 do_cpuid(0x80000008U, p); 457 if (p[1] & CPUID_CAPEX_IBPB) 458 rv |= IBPB_SUPPORTED; 459 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 460 /* 461 * 0x80000008 462 * p[1] bit 12 indicates IBPB support 463 * p[1] bit 14 indicates IBRS support 464 * p[1] bit 15 indicates STIBP support 465 * 466 * p[1] bit 16 indicates IBRS auto support 467 * p[1] bit 17 indicates STIBP auto support 468 * p[1] bit 18 indicates processor prefers using 469 * IBRS instead of retpoline. 470 */ 471 p[0] = 0; 472 p[1] = 0; 473 p[2] = 0; 474 p[3] = 0; 475 do_cpuid(0x80000008U, p); 476 if (p[1] & CPUID_CAPEX_IBPB) 477 rv |= IBPB_SUPPORTED; 478 if (p[1] & CPUID_CAPEX_IBRS) 479 rv |= IBRS_SUPPORTED; 480 if (p[1] & CPUID_CAPEX_STIBP) 481 rv |= STIBP_SUPPORTED; 482 483 if (p[1] & CPUID_CAPEX_IBRS_ALWAYSON) 484 rv |= IBRS_AUTO_SUPPORTED; 485 if (p[1] & CPUID_CAPEX_STIBP_ALWAYSON) 486 rv |= STIBP_AUTO_SUPPORTED; 487 if (p[1] & CPUID_CAPEX_PREFER_IBRS) 488 rv |= IBRS_PREFERRED_REQUEST; 489 } 490 491 return rv; 492 } 493 494 /* 495 * Iterate CPUs and adjust MSR for global operations, since 496 * the KMMU* code won't do it if spectre_mitigation is 0 or 2. 497 */ 498 #define CHECK(flag) (spectre_mitigation & spectre_support & (flag)) 499 500 static 501 void 502 spectre_sysctl_changed(void) 503 { 504 globaldata_t save_gd; 505 struct trampframe *tr; 506 int spec_ctrl; 507 int spec_mask; 508 int mode; 509 int n; 510 511 spec_mask = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | 512 SPEC_CTRL_DUMMY_ENABLE | SPEC_CTRL_DUMMY_IBPB; 513 514 /* 515 * Fixup state 516 */ 517 mode = 0; 518 save_gd = mycpu; 519 for (n = 0; n < ncpus; ++n) { 520 lwkt_setcpu_self(globaldata_find(n)); 521 cpu_ccfence(); 522 tr = &pscpu->trampoline; 523 524 /* 525 * Make sure we are cleaned out. 526 * 527 * XXX cleanup, reusing globals inside the loop (they get 528 * set to the same thing each loop) 529 * 530 * [0] kernel entry (idle exit) 531 * [1] kernel exit (idle entry) 532 */ 533 tr->tr_pcb_spec_ctrl[0] &= ~spec_mask; 534 tr->tr_pcb_spec_ctrl[1] &= ~spec_mask; 535 536 /* 537 * Don't try to parse if not available 538 */ 539 if (spectre_mitigation < 0) 540 continue; 541 542 /* 543 * IBRS mode. Auto overrides toggling. 544 * 545 * Only set the ENABLE flag if we have to toggle something 546 * on entry and exit. 547 */ 548 spec_ctrl = 0; 549 if (CHECK(IBRS_AUTO_SUPPORTED)) { 550 spec_ctrl |= SPEC_CTRL_IBRS; 551 mode |= IBRS_AUTO_SUPPORTED; 552 } else if (CHECK(IBRS_SUPPORTED)) { 553 spec_ctrl |= SPEC_CTRL_IBRS | SPEC_CTRL_DUMMY_ENABLE; 554 mode |= IBRS_SUPPORTED; 555 } 556 if (CHECK(STIBP_AUTO_SUPPORTED)) { 557 spec_ctrl |= SPEC_CTRL_STIBP; 558 mode |= STIBP_AUTO_SUPPORTED; 559 } else if (CHECK(STIBP_SUPPORTED)) { 560 spec_ctrl |= SPEC_CTRL_STIBP | SPEC_CTRL_DUMMY_ENABLE; 561 mode |= STIBP_SUPPORTED; 562 } 563 564 /* 565 * IBPB requested and supported. 566 */ 567 if (CHECK(IBPB_SUPPORTED)) { 568 spec_ctrl |= SPEC_CTRL_DUMMY_IBPB; 569 mode |= IBPB_SUPPORTED; 570 } 571 572 /* 573 * Update the MSR if the cpu supports the modes to ensure 574 * proper disablement if the user disabled the mode. 575 */ 576 if (spectre_support & (IBRS_SUPPORTED | IBRS_AUTO_SUPPORTED | 577 STIBP_SUPPORTED | STIBP_AUTO_SUPPORTED)) { 578 wrmsr(MSR_SPEC_CTRL, 579 spec_ctrl & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP)); 580 } 581 582 /* 583 * Update spec_ctrl fields in the trampoline. 584 * 585 * [0] on-kernel-entry (on-idle-exit) 586 * [1] on-kernel-exit (on-idle-entry) 587 * 588 * When auto mode is supported we leave the bit set, otherwise 589 * we clear the bits. 590 */ 591 tr->tr_pcb_spec_ctrl[0] |= spec_ctrl; 592 if (CHECK(IBRS_AUTO_SUPPORTED) == 0) 593 spec_ctrl &= ~SPEC_CTRL_IBRS; 594 if (CHECK(STIBP_AUTO_SUPPORTED) == 0) 595 spec_ctrl &= ~SPEC_CTRL_STIBP; 596 tr->tr_pcb_spec_ctrl[1] |= spec_ctrl; 597 598 /* 599 * Make sure we set this on the first loop. It will be 600 * the same value on remaining loops. 601 */ 602 spectre_mode = mode; 603 } 604 lwkt_setcpu_self(save_gd); 605 cpu_ccfence(); 606 607 /* 608 * Console message on mitigation mode change 609 */ 610 kprintf("Spectre: support=("); 611 if (spectre_support == 0) { 612 kprintf(" none"); 613 } else { 614 if (spectre_support & IBRS_SUPPORTED) 615 kprintf(" IBRS"); 616 if (spectre_support & STIBP_SUPPORTED) 617 kprintf(" STIBP"); 618 if (spectre_support & IBPB_SUPPORTED) 619 kprintf(" IBPB"); 620 if (spectre_support & IBRS_AUTO_SUPPORTED) 621 kprintf(" IBRS_AUTO"); 622 if (spectre_support & STIBP_AUTO_SUPPORTED) 623 kprintf(" STIBP_AUTO"); 624 if (spectre_support & IBRS_PREFERRED_REQUEST) 625 kprintf(" IBRS_REQUESTED"); 626 } 627 kprintf(" ) req=%04x operating=(", (uint16_t)spectre_mitigation); 628 if (spectre_mode == 0) { 629 kprintf(" none"); 630 } else { 631 if (spectre_mode & IBRS_SUPPORTED) 632 kprintf(" IBRS"); 633 if (spectre_mode & STIBP_SUPPORTED) 634 kprintf(" STIBP"); 635 if (spectre_mode & IBPB_SUPPORTED) 636 kprintf(" IBPB"); 637 if (spectre_mode & IBRS_AUTO_SUPPORTED) 638 kprintf(" IBRS_AUTO"); 639 if (spectre_mode & STIBP_AUTO_SUPPORTED) 640 kprintf(" STIBP_AUTO"); 641 if (spectre_mode & IBRS_PREFERRED_REQUEST) 642 kprintf(" IBRS_REQUESTED"); 643 } 644 kprintf(" )\n"); 645 } 646 647 #undef CHECK 648 649 /* 650 * User changes sysctl value 651 */ 652 static int 653 sysctl_spectre_mitigation(SYSCTL_HANDLER_ARGS) 654 { 655 char buf[128]; 656 char *ptr; 657 char *iter; 658 size_t len; 659 int spectre; 660 int error = 0; 661 int loop = 0; 662 663 /* 664 * Return current operating mode or support. 665 */ 666 if (oidp->oid_kind & CTLFLAG_WR) 667 spectre = spectre_mode; 668 else 669 spectre = spectre_support; 670 671 spectre &= (IBRS_SUPPORTED | IBRS_AUTO_SUPPORTED | 672 STIBP_SUPPORTED | STIBP_AUTO_SUPPORTED | 673 IBPB_SUPPORTED); 674 while (spectre) { 675 if (error) 676 break; 677 if (loop++) { 678 error = SYSCTL_OUT(req, " ", 1); 679 if (error) 680 break; 681 } 682 if (spectre & IBRS_SUPPORTED) { 683 spectre &= ~IBRS_SUPPORTED; 684 error = SYSCTL_OUT(req, "IBRS", 4); 685 } else 686 if (spectre & IBRS_AUTO_SUPPORTED) { 687 spectre &= ~IBRS_AUTO_SUPPORTED; 688 error = SYSCTL_OUT(req, "IBRS_AUTO", 9); 689 } else 690 if (spectre & STIBP_SUPPORTED) { 691 spectre &= ~STIBP_SUPPORTED; 692 error = SYSCTL_OUT(req, "STIBP", 5); 693 } else 694 if (spectre & STIBP_AUTO_SUPPORTED) { 695 spectre &= ~STIBP_AUTO_SUPPORTED; 696 error = SYSCTL_OUT(req, "STIBP_AUTO", 10); 697 } else 698 if (spectre & IBPB_SUPPORTED) { 699 spectre &= ~IBPB_SUPPORTED; 700 error = SYSCTL_OUT(req, "IBPB", 4); 701 } 702 } 703 if (loop == 0) { 704 error = SYSCTL_OUT(req, "NONE", 4); 705 } 706 707 if (error || req->newptr == NULL) 708 return error; 709 if ((oidp->oid_kind & CTLFLAG_WR) == 0) 710 return error; 711 712 /* 713 * Change current operating mode 714 */ 715 len = req->newlen - req->newidx; 716 if (len >= sizeof(buf)) { 717 error = EINVAL; 718 len = 0; 719 } else { 720 error = SYSCTL_IN(req, buf, len); 721 } 722 buf[len] = 0; 723 iter = &buf[0]; 724 spectre = 0; 725 726 while (error == 0 && iter) { 727 ptr = strsep(&iter, " ,\t\r\n"); 728 if (*ptr == 0) 729 continue; 730 if (strcasecmp(ptr, "NONE") == 0) 731 spectre |= 0; 732 else if (strcasecmp(ptr, "IBRS") == 0) 733 spectre |= IBRS_SUPPORTED; 734 else if (strcasecmp(ptr, "IBRS_AUTO") == 0) 735 spectre |= IBRS_AUTO_SUPPORTED; 736 else if (strcasecmp(ptr, "STIBP") == 0) 737 spectre |= STIBP_SUPPORTED; 738 else if (strcasecmp(ptr, "STIBP_AUTO") == 0) 739 spectre |= STIBP_AUTO_SUPPORTED; 740 else if (strcasecmp(ptr, "IBPB") == 0) 741 spectre |= IBPB_SUPPORTED; 742 else 743 error = ENOENT; 744 } 745 if (error == 0) { 746 spectre_mitigation = spectre; 747 spectre_sysctl_changed(); 748 } 749 return error; 750 } 751 752 SYSCTL_PROC(_machdep, OID_AUTO, spectre_mitigation, 753 CTLTYPE_STRING | CTLFLAG_RW, 754 0, 0, sysctl_spectre_mitigation, "A", "Spectre exploit mitigation"); 755 SYSCTL_PROC(_machdep, OID_AUTO, spectre_support, 756 CTLTYPE_STRING | CTLFLAG_RD, 757 0, 0, sysctl_spectre_mitigation, "A", "Spectre supported features"); 758 759 /* 760 * NOTE: Called at SI_BOOT2_MACHDEP and also when the microcode is 761 * updated. Microcode updates must be applied to all cpus 762 * for support to be recognized. 763 */ 764 static void 765 spectre_vm_setup(void *arg) 766 { 767 int inconsistent = 0; 768 int supmask; 769 770 /* 771 * Fetch tunable in auto mode 772 */ 773 if (spectre_mitigation < 0) { 774 TUNABLE_INT_FETCH("machdep.spectre_mitigation", 775 &spectre_mitigation); 776 } 777 778 if ((supmask = spectre_check_support()) != 0) { 779 /* 780 * Must be supported on all cpus before we 781 * can enable it. Returns silently if it 782 * isn't. 783 * 784 * NOTE! arg != NULL indicates we were called 785 * from cpuctl after a successful microcode 786 * update. 787 */ 788 if (arg != NULL) { 789 globaldata_t save_gd; 790 int n; 791 792 save_gd = mycpu; 793 for (n = 0; n < ncpus; ++n) { 794 lwkt_setcpu_self(globaldata_find(n)); 795 cpu_ccfence(); 796 if (spectre_check_support() != 797 supmask) { 798 inconsistent = 1; 799 break; 800 } 801 } 802 lwkt_setcpu_self(save_gd); 803 cpu_ccfence(); 804 } 805 } 806 807 /* 808 * Be silent while microcode is being loaded on various CPUs, 809 * until all done. 810 */ 811 if (inconsistent) { 812 spectre_mitigation = -1; 813 spectre_support = 0; 814 return; 815 } 816 817 /* 818 * IBRS support 819 */ 820 spectre_support = supmask; 821 822 /* 823 * Enable spectre_mitigation, set defaults if -1, adjust 824 * tuned value according to support if not. 825 * 826 * NOTE! We do not enable IBPB for user->kernel transitions 827 * by default, so this code is commented out for now. 828 */ 829 if (spectre_support) { 830 if (spectre_mitigation < 0) { 831 spectre_mitigation = 0; 832 833 /* 834 * IBRS toggling not currently recommended as a 835 * default. 836 */ 837 if (spectre_support & IBRS_AUTO_SUPPORTED) 838 spectre_mitigation |= IBRS_AUTO_SUPPORTED; 839 else if (spectre_support & IBRS_SUPPORTED) 840 spectre_mitigation |= 0; 841 842 /* 843 * STIBP toggling not currently recommended as a 844 * default. 845 */ 846 if (spectre_support & STIBP_AUTO_SUPPORTED) 847 spectre_mitigation |= STIBP_AUTO_SUPPORTED; 848 else if (spectre_support & STIBP_SUPPORTED) 849 spectre_mitigation |= 0; 850 851 /* 852 * IBPB adds enormous (~2uS) overhead to system 853 * calls etc, we do not enable it by default. 854 */ 855 if (spectre_support & IBPB_SUPPORTED) 856 spectre_mitigation |= 0; 857 } 858 } else { 859 spectre_mitigation = -1; 860 } 861 862 /* 863 * Disallow sysctl changes when there is no support (otherwise 864 * the wrmsr will cause a protection fault). 865 */ 866 if (spectre_mitigation < 0) 867 sysctl___machdep_spectre_mitigation.oid_kind &= ~CTLFLAG_WR; 868 else 869 sysctl___machdep_spectre_mitigation.oid_kind |= CTLFLAG_WR; 870 871 spectre_sysctl_changed(); 872 } 873 874 #define MDS_AVX512_4VNNIW_SUPPORTED 0x0001 875 #define MDS_AVX512_4FMAPS_SUPPORTED 0x0002 876 #define MDS_MD_CLEAR_SUPPORTED 0x0004 877 #define MDS_TSX_FORCE_ABORT_SUPPORTED 0x0008 878 #define MDS_NOT_REQUIRED 0x8000 879 880 static 881 int 882 mds_check_support(void) 883 { 884 uint64_t msr; 885 uint32_t p[4]; 886 int rv = 0; 887 888 /* 889 * MDS mitigation hw bits 890 * 891 * MD_CLEAR Use microcode-supported verf insn. This is the 892 * only mode we really support. 893 */ 894 if (cpu_vendor_id == CPU_VENDOR_INTEL) { 895 p[0] = 0; 896 p[1] = 0; 897 p[2] = 0; 898 p[3] = 0; 899 cpuid_count(7, 0, p); 900 901 /* 902 * Some hypervisors fail to implement 903 * MSR_IA32_ARCH_CAPABILITIES. 904 */ 905 if (p[3] & CPUID_STDEXT3_ARCH_CAP) { 906 msr = 0; 907 if (rdmsr_safe(MSR_IA32_ARCH_CAPABILITIES, &msr)) { 908 kprintf("Warning: MSR_IA32_ARCH_CAPABILITIES " 909 "cannot be accessed\n"); 910 } 911 if (msr & IA32_ARCH_CAP_MDS_NO) 912 rv = MDS_NOT_REQUIRED; 913 } 914 if (p[3] & CPUID_STDEXT3_AVX5124VNNIW) 915 rv |= MDS_AVX512_4VNNIW_SUPPORTED; 916 if (p[3] & CPUID_STDEXT3_AVX5124FMAPS) 917 rv |= MDS_AVX512_4FMAPS_SUPPORTED; 918 if (p[3] & CPUID_STDEXT3_MD_CLEAR) 919 rv |= MDS_MD_CLEAR_SUPPORTED; 920 if (p[3] & CPUID_STDEXT3_TSXFA) 921 rv |= MDS_TSX_FORCE_ABORT_SUPPORTED; 922 } else { 923 rv = MDS_NOT_REQUIRED; 924 } 925 926 return rv; 927 } 928 929 /* 930 * Iterate CPUs and adjust MSR for global operations, since 931 * the KMMU* code won't do it if spectre_mitigation is 0 or 2. 932 */ 933 #define CHECK(flag) (mds_mitigation & mds_support & (flag)) 934 935 static 936 void 937 mds_sysctl_changed(void) 938 { 939 globaldata_t save_gd; 940 struct trampframe *tr; 941 int spec_ctrl; 942 int spec_mask; 943 int mode; 944 int n; 945 946 spec_mask = SPEC_CTRL_MDS_ENABLE; 947 948 /* 949 * Fixup state 950 */ 951 mode = 0; 952 save_gd = mycpu; 953 for (n = 0; n < ncpus; ++n) { 954 lwkt_setcpu_self(globaldata_find(n)); 955 cpu_ccfence(); 956 tr = &pscpu->trampoline; 957 958 /* 959 * Make sure we are cleaned out. 960 * 961 * XXX cleanup, reusing globals inside the loop (they get 962 * set to the same thing each loop) 963 * 964 * [0] kernel entry (idle exit) 965 * [1] kernel exit (idle entry) 966 */ 967 tr->tr_pcb_spec_ctrl[0] &= ~spec_mask; 968 tr->tr_pcb_spec_ctrl[1] &= ~spec_mask; 969 970 /* 971 * Don't try to parse if not available 972 */ 973 if (mds_mitigation < 0) 974 continue; 975 976 spec_ctrl = 0; 977 if (CHECK(MDS_MD_CLEAR_SUPPORTED)) { 978 spec_ctrl |= SPEC_CTRL_MDS_ENABLE; 979 mode |= MDS_MD_CLEAR_SUPPORTED; 980 } 981 982 /* 983 * Update spec_ctrl fields in the trampoline. 984 * 985 * [0] on-kernel-entry (on-idle-exit) 986 * [1] on-kernel-exit (on-idle-entry) 987 * 988 * The MDS stuff is only needed on kernel-exit or idle-entry 989 */ 990 /* tr->tr_pcb_spec_ctrl[0] |= spec_ctrl; */ 991 tr->tr_pcb_spec_ctrl[1] |= spec_ctrl; 992 993 /* 994 * Make sure we set this on the first loop. It will be 995 * the same value on remaining loops. 996 */ 997 mds_mode = mode; 998 } 999 lwkt_setcpu_self(save_gd); 1000 cpu_ccfence(); 1001 1002 /* 1003 * Console message on mitigation mode change 1004 */ 1005 kprintf("MDS: support=("); 1006 if (mds_support == 0) { 1007 kprintf(" none"); 1008 } else { 1009 if (mds_support & MDS_AVX512_4VNNIW_SUPPORTED) 1010 kprintf(" AVX512_4VNNIW"); 1011 if (mds_support & MDS_AVX512_4FMAPS_SUPPORTED) 1012 kprintf(" AVX512_4FMAPS"); 1013 if (mds_support & MDS_MD_CLEAR_SUPPORTED) 1014 kprintf(" MD_CLEAR"); 1015 if (mds_support & MDS_TSX_FORCE_ABORT_SUPPORTED) 1016 kprintf(" TSX_FORCE_ABORT"); 1017 if (mds_support & MDS_NOT_REQUIRED) 1018 kprintf(" MDS_NOT_REQUIRED"); 1019 } 1020 kprintf(" ) req=%04x operating=(", (uint16_t)mds_mitigation); 1021 if (mds_mode == 0) { 1022 kprintf(" none"); 1023 } else { 1024 if (mds_mode & MDS_AVX512_4VNNIW_SUPPORTED) 1025 kprintf(" AVX512_4VNNIW"); 1026 if (mds_mode & MDS_AVX512_4FMAPS_SUPPORTED) 1027 kprintf(" AVX512_4FMAPS"); 1028 if (mds_mode & MDS_MD_CLEAR_SUPPORTED) 1029 kprintf(" MD_CLEAR"); 1030 if (mds_mode & MDS_TSX_FORCE_ABORT_SUPPORTED) 1031 kprintf(" TSX_FORCE_ABORT"); 1032 if (mds_mode & MDS_NOT_REQUIRED) 1033 kprintf(" MDS_NOT_REQUIRED"); 1034 } 1035 kprintf(" )\n"); 1036 } 1037 1038 #undef CHECK 1039 1040 /* 1041 * User changes sysctl value 1042 */ 1043 static int 1044 sysctl_mds_mitigation(SYSCTL_HANDLER_ARGS) 1045 { 1046 char buf[128]; 1047 char *ptr; 1048 char *iter; 1049 size_t len; 1050 int mds; 1051 int error = 0; 1052 int loop = 0; 1053 1054 /* 1055 * Return current operating mode or support. 1056 */ 1057 if (oidp->oid_kind & CTLFLAG_WR) 1058 mds = mds_mode; 1059 else 1060 mds = mds_support; 1061 1062 mds &= MDS_AVX512_4VNNIW_SUPPORTED | 1063 MDS_AVX512_4FMAPS_SUPPORTED | 1064 MDS_MD_CLEAR_SUPPORTED | 1065 MDS_TSX_FORCE_ABORT_SUPPORTED | 1066 MDS_NOT_REQUIRED; 1067 1068 while (mds) { 1069 if (error) 1070 break; 1071 if (loop++) { 1072 error = SYSCTL_OUT(req, " ", 1); 1073 if (error) 1074 break; 1075 } 1076 if (mds & MDS_AVX512_4VNNIW_SUPPORTED) { 1077 mds &= ~MDS_AVX512_4VNNIW_SUPPORTED; 1078 error = SYSCTL_OUT(req, "AVX512_4VNNIW", 13); 1079 } else 1080 if (mds & MDS_AVX512_4FMAPS_SUPPORTED) { 1081 mds &= ~MDS_AVX512_4FMAPS_SUPPORTED; 1082 error = SYSCTL_OUT(req, "AVX512_4FMAPS", 13); 1083 } else 1084 if (mds & MDS_MD_CLEAR_SUPPORTED) { 1085 mds &= ~MDS_MD_CLEAR_SUPPORTED; 1086 error = SYSCTL_OUT(req, "MD_CLEAR", 8); 1087 } else 1088 if (mds & MDS_TSX_FORCE_ABORT_SUPPORTED) { 1089 mds &= ~MDS_TSX_FORCE_ABORT_SUPPORTED; 1090 error = SYSCTL_OUT(req, "TSX_FORCE_ABORT", 15); 1091 } else 1092 if (mds & MDS_NOT_REQUIRED) { 1093 mds &= ~MDS_NOT_REQUIRED; 1094 error = SYSCTL_OUT(req, "MDS_NOT_REQUIRED", 16); 1095 } 1096 } 1097 if (loop == 0) { 1098 error = SYSCTL_OUT(req, "NONE", 4); 1099 } 1100 1101 if (error || req->newptr == NULL) 1102 return error; 1103 if ((oidp->oid_kind & CTLFLAG_WR) == 0) 1104 return error; 1105 1106 /* 1107 * Change current operating mode 1108 */ 1109 len = req->newlen - req->newidx; 1110 if (len >= sizeof(buf)) { 1111 error = EINVAL; 1112 len = 0; 1113 } else { 1114 error = SYSCTL_IN(req, buf, len); 1115 } 1116 buf[len] = 0; 1117 iter = &buf[0]; 1118 mds = 0; 1119 1120 while (error == 0 && iter) { 1121 ptr = strsep(&iter, " ,\t\r\n"); 1122 if (*ptr == 0) 1123 continue; 1124 if (strcasecmp(ptr, "NONE") == 0) 1125 mds |= 0; 1126 else if (strcasecmp(ptr, "AVX512_4VNNIW") == 0) 1127 mds |= MDS_AVX512_4VNNIW_SUPPORTED; 1128 else if (strcasecmp(ptr, "AVX512_4FMAPS") == 0) 1129 mds |= MDS_AVX512_4FMAPS_SUPPORTED; 1130 else if (strcasecmp(ptr, "MD_CLEAR") == 0) 1131 mds |= MDS_MD_CLEAR_SUPPORTED; 1132 else if (strcasecmp(ptr, "TSX_FORCE_ABORT") == 0) 1133 mds |= MDS_TSX_FORCE_ABORT_SUPPORTED; 1134 else if (strcasecmp(ptr, "MDS_NOT_REQUIRED") == 0) 1135 mds |= MDS_NOT_REQUIRED; 1136 else 1137 error = ENOENT; 1138 } 1139 if (error == 0) { 1140 mds_mitigation = mds; 1141 mds_sysctl_changed(); 1142 } 1143 return error; 1144 } 1145 1146 SYSCTL_PROC(_machdep, OID_AUTO, mds_mitigation, 1147 CTLTYPE_STRING | CTLFLAG_RW, 1148 0, 0, sysctl_mds_mitigation, "A", "MDS exploit mitigation"); 1149 SYSCTL_PROC(_machdep, OID_AUTO, mds_support, 1150 CTLTYPE_STRING | CTLFLAG_RD, 1151 0, 0, sysctl_mds_mitigation, "A", "MDS supported features"); 1152 1153 /* 1154 * NOTE: Called at SI_BOOT2_MACHDEP and also when the microcode is 1155 * updated. Microcode updates must be applied to all cpus 1156 * for support to be recognized. 1157 */ 1158 static void 1159 mds_vm_setup(void *arg) 1160 { 1161 int inconsistent = 0; 1162 int supmask; 1163 1164 /* 1165 * Fetch tunable in auto mode 1166 */ 1167 if (mds_mitigation < 0) { 1168 TUNABLE_INT_FETCH("machdep.mds_mitigation", &mds_mitigation); 1169 } 1170 1171 if ((supmask = mds_check_support()) != 0) { 1172 /* 1173 * Must be supported on all cpus before we 1174 * can enable it. Returns silently if it 1175 * isn't. 1176 * 1177 * NOTE! arg != NULL indicates we were called 1178 * from cpuctl after a successful microcode 1179 * update. 1180 */ 1181 if (arg != NULL) { 1182 globaldata_t save_gd; 1183 int n; 1184 1185 save_gd = mycpu; 1186 for (n = 0; n < ncpus; ++n) { 1187 lwkt_setcpu_self(globaldata_find(n)); 1188 cpu_ccfence(); 1189 if (mds_check_support() != supmask) { 1190 inconsistent = 1; 1191 break; 1192 } 1193 } 1194 lwkt_setcpu_self(save_gd); 1195 cpu_ccfence(); 1196 } 1197 } 1198 1199 /* 1200 * Be silent while microcode is being loaded on various CPUs, 1201 * until all done. 1202 */ 1203 if (inconsistent) { 1204 mds_mitigation = -1; 1205 mds_support = 0; 1206 return; 1207 } 1208 1209 /* 1210 * IBRS support 1211 */ 1212 mds_support = supmask; 1213 1214 /* 1215 * Enable mds_mitigation, set defaults if -1, adjust 1216 * tuned value according to support if not. 1217 * 1218 * NOTE! MDS is not enabled by default. 1219 */ 1220 if (mds_support) { 1221 if (mds_mitigation < 0) { 1222 mds_mitigation = 0; 1223 1224 if ((mds_support & MDS_NOT_REQUIRED) == 0 && 1225 (mds_support & MDS_MD_CLEAR_SUPPORTED)) { 1226 /* mds_mitigation |= MDS_MD_CLEAR_SUPPORTED; */ 1227 } 1228 } 1229 } else { 1230 mds_mitigation = -1; 1231 } 1232 1233 /* 1234 * Disallow sysctl changes when there is no support (otherwise 1235 * the wrmsr will cause a protection fault). 1236 */ 1237 if (mds_mitigation < 0) 1238 sysctl___machdep_mds_mitigation.oid_kind &= ~CTLFLAG_WR; 1239 else 1240 sysctl___machdep_mds_mitigation.oid_kind |= CTLFLAG_WR; 1241 1242 mds_sysctl_changed(); 1243 } 1244 1245 /* 1246 * NOTE: Called at SI_BOOT2_MACHDEP and also when the microcode is 1247 * updated. Microcode updates must be applied to all cpus 1248 * for support to be recognized. 1249 */ 1250 void 1251 mitigation_vm_setup(void *arg) 1252 { 1253 spectre_vm_setup(arg); 1254 mds_vm_setup(arg); 1255 } 1256 1257 SYSINIT(mitigation_vm_setup, SI_BOOT2_MACHDEP, SI_ORDER_ANY, 1258 mitigation_vm_setup, NULL); 1259 1260 /* 1261 * platform-specific vmspace initialization (nothing for x86_64) 1262 */ 1263 void 1264 cpu_vmspace_alloc(struct vmspace *vm __unused) 1265 { 1266 } 1267 1268 void 1269 cpu_vmspace_free(struct vmspace *vm __unused) 1270 { 1271 } 1272 1273 int 1274 kvm_access_check(vm_offset_t saddr, vm_offset_t eaddr, int prot) 1275 { 1276 vm_offset_t addr; 1277 1278 if (saddr < KvaStart) 1279 return EFAULT; 1280 if (eaddr >= KvaEnd) 1281 return EFAULT; 1282 for (addr = saddr; addr < eaddr; addr += PAGE_SIZE) { 1283 if (pmap_kextract(addr) == 0) 1284 return EFAULT; 1285 } 1286 if (!kernacc((caddr_t)saddr, eaddr - saddr, prot)) 1287 return EFAULT; 1288 return 0; 1289 } 1290 1291 #if 0 1292 1293 void _test_frame_enter(struct trapframe *frame); 1294 void _test_frame_exit(struct trapframe *frame); 1295 1296 void 1297 _test_frame_enter(struct trapframe *frame) 1298 { 1299 thread_t td = curthread; 1300 1301 if (ISPL(frame->tf_cs) == SEL_UPL) { 1302 KKASSERT(td->td_lwp); 1303 KASSERT(td->td_lwp->lwp_md.md_regs == frame, 1304 ("_test_frame_exit: Frame mismatch %p %p", 1305 td->td_lwp->lwp_md.md_regs, frame)); 1306 td->td_lwp->lwp_saveusp = (void *)frame->tf_rsp; 1307 td->td_lwp->lwp_saveupc = (void *)frame->tf_rip; 1308 } 1309 if ((char *)frame < td->td_kstack || 1310 (char *)frame > td->td_kstack + td->td_kstack_size) { 1311 panic("_test_frame_exit: frame not on kstack %p kstack=%p", 1312 frame, td->td_kstack); 1313 } 1314 } 1315 1316 void 1317 _test_frame_exit(struct trapframe *frame) 1318 { 1319 thread_t td = curthread; 1320 1321 if (ISPL(frame->tf_cs) == SEL_UPL) { 1322 KKASSERT(td->td_lwp); 1323 KASSERT(td->td_lwp->lwp_md.md_regs == frame, 1324 ("_test_frame_exit: Frame mismatch %p %p", 1325 td->td_lwp->lwp_md.md_regs, frame)); 1326 if (td->td_lwp->lwp_saveusp != (void *)frame->tf_rsp) { 1327 kprintf("_test_frame_exit: %s:%d usp mismatch %p/%p\n", 1328 td->td_comm, td->td_proc->p_pid, 1329 td->td_lwp->lwp_saveusp, 1330 (void *)frame->tf_rsp); 1331 } 1332 if (td->td_lwp->lwp_saveupc != (void *)frame->tf_rip) { 1333 kprintf("_test_frame_exit: %s:%d upc mismatch %p/%p\n", 1334 td->td_comm, td->td_proc->p_pid, 1335 td->td_lwp->lwp_saveupc, 1336 (void *)frame->tf_rip); 1337 } 1338 1339 /* 1340 * adulterate the fields to catch entries that 1341 * don't run through test_frame_enter 1342 */ 1343 td->td_lwp->lwp_saveusp = 1344 (void *)~(intptr_t)td->td_lwp->lwp_saveusp; 1345 td->td_lwp->lwp_saveupc = 1346 (void *)~(intptr_t)td->td_lwp->lwp_saveupc; 1347 } 1348 if ((char *)frame < td->td_kstack || 1349 (char *)frame > td->td_kstack + td->td_kstack_size) { 1350 panic("_test_frame_exit: frame not on kstack %p kstack=%p", 1351 frame, td->td_kstack); 1352 } 1353 } 1354 1355 #endif 1356