1 /* 2 * Copyright (c) 2006 The DragonFly Project. All rights reserved. 3 * Copyright (c) 1990 William Jolitz. 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The DragonFly Project 8 * by Matthew Dillon <dillon@backplane.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in 18 * the documentation and/or other materials provided with the 19 * distribution. 20 * 3. Neither the name of The DragonFly Project nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific, prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 28 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 39 */ 40 41 #include "opt_debug_npx.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/bus.h> 46 #include <sys/kernel.h> 47 #include <sys/malloc.h> 48 #include <sys/module.h> 49 #include <sys/sysctl.h> 50 #include <sys/proc.h> 51 #include <sys/rman.h> 52 #ifdef NPX_DEBUG 53 #include <sys/syslog.h> 54 #endif 55 #include <sys/signalvar.h> 56 #include <sys/thread2.h> 57 58 #include <machine/cputypes.h> 59 #include <machine/frame.h> 60 #include <machine/md_var.h> 61 #include <machine/pcb.h> 62 #include <machine/psl.h> 63 #include <machine/specialreg.h> 64 #include <machine/segments.h> 65 #include <machine/globaldata.h> 66 67 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 68 #define fnclex() __asm("fnclex") 69 #define fninit() __asm("fninit") 70 #define fnop() __asm("fnop") 71 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 72 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 73 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 74 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 75 #ifndef CPU_DISABLE_SSE 76 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 77 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 78 #endif 79 80 typedef u_char bool_t; 81 #ifndef CPU_DISABLE_SSE 82 static void fpu_clean_state(void); 83 #endif 84 85 int cpu_fxsr = 0; 86 87 static struct krate badfprate = { 1 }; 88 89 /*static int npx_attach (device_t dev);*/ 90 static void fpusave (union savefpu *); 91 static void fpurstor (union savefpu *); 92 93 #ifndef CPU_DISABLE_SSE 94 int mmxopt = 1; 95 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0, 96 "MMX/XMM optimized bcopy/copyin/copyout support"); 97 #endif 98 99 static int hw_instruction_sse; 100 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 101 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 102 103 #if 0 104 /* 105 * Attach routine - announce which it is, and wire into system 106 */ 107 int 108 npx_attach(device_t dev) 109 { 110 npxinit(__INITIAL_FPUCW__); 111 return (0); 112 } 113 #endif 114 115 void 116 init_fpu(int supports_sse) 117 { 118 cpu_fxsr = hw_instruction_sse = supports_sse; 119 } 120 121 /* 122 * Initialize the floating point unit. 123 */ 124 void 125 npxinit(u_short control) 126 { 127 static union savefpu dummy __aligned(16); 128 129 /* 130 * fninit has the same h/w bugs as fnsave. Use the detoxified 131 * fnsave to throw away any junk in the fpu. npxsave() initializes 132 * the fpu and sets npxthread = NULL as important side effects. 133 */ 134 npxsave(&dummy); 135 crit_enter(); 136 /*stop_emulating();*/ 137 fldcw(&control); 138 fpusave(curthread->td_savefpu); 139 mdcpu->gd_npxthread = NULL; 140 /*start_emulating();*/ 141 crit_exit(); 142 } 143 144 /* 145 * Free coprocessor (if we have it). 146 */ 147 void 148 npxexit(void) 149 { 150 if (curthread == mdcpu->gd_npxthread) 151 npxsave(curthread->td_savefpu); 152 } 153 154 #if 0 155 /* 156 * The following mechanism is used to ensure that the FPE_... value 157 * that is passed as a trapcode to the signal handler of the user 158 * process does not have more than one bit set. 159 * 160 * Multiple bits may be set if the user process modifies the control 161 * word while a status word bit is already set. While this is a sign 162 * of bad coding, we have no choise than to narrow them down to one 163 * bit, since we must not send a trapcode that is not exactly one of 164 * the FPE_ macros. 165 * 166 * The mechanism has a static table with 127 entries. Each combination 167 * of the 7 FPU status word exception bits directly translates to a 168 * position in this table, where a single FPE_... value is stored. 169 * This FPE_... value stored there is considered the "most important" 170 * of the exception bits and will be sent as the signal code. The 171 * precedence of the bits is based upon Intel Document "Numerical 172 * Applications", Chapter "Special Computational Situations". 173 * 174 * The macro to choose one of these values does these steps: 1) Throw 175 * away status word bits that cannot be masked. 2) Throw away the bits 176 * currently masked in the control word, assuming the user isn't 177 * interested in them anymore. 3) Reinsert status word bit 7 (stack 178 * fault) if it is set, which cannot be masked but must be presered. 179 * 4) Use the remaining bits to point into the trapcode table. 180 * 181 * The 6 maskable bits in order of their preference, as stated in the 182 * above referenced Intel manual: 183 * 1 Invalid operation (FP_X_INV) 184 * 1a Stack underflow 185 * 1b Stack overflow 186 * 1c Operand of unsupported format 187 * 1d SNaN operand. 188 * 2 QNaN operand (not an exception, irrelavant here) 189 * 3 Any other invalid-operation not mentioned above or zero divide 190 * (FP_X_INV, FP_X_DZ) 191 * 4 Denormal operand (FP_X_DNML) 192 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 193 * 6 Inexact result (FP_X_IMP) 194 */ 195 static char fpetable[128] = { 196 0, 197 FPE_FLTINV, /* 1 - INV */ 198 FPE_FLTUND, /* 2 - DNML */ 199 FPE_FLTINV, /* 3 - INV | DNML */ 200 FPE_FLTDIV, /* 4 - DZ */ 201 FPE_FLTINV, /* 5 - INV | DZ */ 202 FPE_FLTDIV, /* 6 - DNML | DZ */ 203 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 204 FPE_FLTOVF, /* 8 - OFL */ 205 FPE_FLTINV, /* 9 - INV | OFL */ 206 FPE_FLTUND, /* A - DNML | OFL */ 207 FPE_FLTINV, /* B - INV | DNML | OFL */ 208 FPE_FLTDIV, /* C - DZ | OFL */ 209 FPE_FLTINV, /* D - INV | DZ | OFL */ 210 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 211 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 212 FPE_FLTUND, /* 10 - UFL */ 213 FPE_FLTINV, /* 11 - INV | UFL */ 214 FPE_FLTUND, /* 12 - DNML | UFL */ 215 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 216 FPE_FLTDIV, /* 14 - DZ | UFL */ 217 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 218 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 219 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 220 FPE_FLTOVF, /* 18 - OFL | UFL */ 221 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 222 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 223 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 224 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 225 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 226 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 227 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 228 FPE_FLTRES, /* 20 - IMP */ 229 FPE_FLTINV, /* 21 - INV | IMP */ 230 FPE_FLTUND, /* 22 - DNML | IMP */ 231 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 232 FPE_FLTDIV, /* 24 - DZ | IMP */ 233 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 234 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 235 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 236 FPE_FLTOVF, /* 28 - OFL | IMP */ 237 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 238 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 239 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 240 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 241 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 242 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 243 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 244 FPE_FLTUND, /* 30 - UFL | IMP */ 245 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 246 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 247 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 248 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 249 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 250 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 251 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 252 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 253 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 254 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 255 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 256 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 257 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 258 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 259 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 260 FPE_FLTSUB, /* 40 - STK */ 261 FPE_FLTSUB, /* 41 - INV | STK */ 262 FPE_FLTUND, /* 42 - DNML | STK */ 263 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 264 FPE_FLTDIV, /* 44 - DZ | STK */ 265 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 266 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 267 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 268 FPE_FLTOVF, /* 48 - OFL | STK */ 269 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 270 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 271 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 272 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 273 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 274 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 275 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 276 FPE_FLTUND, /* 50 - UFL | STK */ 277 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 278 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 279 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 280 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 281 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 282 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 283 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 284 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 285 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 286 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 287 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 288 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 289 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 290 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 291 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 292 FPE_FLTRES, /* 60 - IMP | STK */ 293 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 294 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 295 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 296 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 297 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 298 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 299 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 300 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 301 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 302 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 303 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 304 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 305 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 306 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 307 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 308 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 309 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 310 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 311 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 312 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 313 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 314 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 315 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 316 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 317 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 318 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 319 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 320 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 321 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 322 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 323 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 324 }; 325 #endif 326 327 /* 328 * Implement the device not available (DNA) exception. gd_npxthread had 329 * better be NULL. Restore the current thread's FP state and set gd_npxthread 330 * to curthread. 331 * 332 * Interrupts are enabled and preemption can occur. Enter a critical 333 * section to stabilize the FP state. 334 */ 335 int 336 npxdna(struct trapframe *frame) 337 { 338 thread_t td = curthread; 339 int didinit = 0; 340 341 if (mdcpu->gd_npxthread != NULL) { 342 kprintf("npxdna: npxthread = %p, curthread = %p\n", 343 mdcpu->gd_npxthread, td); 344 panic("npxdna"); 345 } 346 347 /* 348 * Setup the initial saved state if the thread has never before 349 * used the FP unit. This also occurs when a thread pushes a 350 * signal handler and uses FP in the handler. 351 */ 352 if ((curthread->td_flags & TDF_USINGFP) == 0) { 353 curthread->td_flags |= TDF_USINGFP; 354 npxinit(__INITIAL_FPUCW__); 355 didinit = 1; 356 } 357 358 /* 359 * The setting of gd_npxthread and the call to fpurstor() must not 360 * be preempted by an interrupt thread or we will take an npxdna 361 * trap and potentially save our current fpstate (which is garbage) 362 * and then restore the garbage rather then the originally saved 363 * fpstate. 364 */ 365 crit_enter(); 366 /*stop_emulating();*/ 367 /* 368 * Record new context early in case frstor causes an IRQ13. 369 */ 370 mdcpu->gd_npxthread = td; 371 /* 372 * The following frstor may cause an IRQ13 when the state being 373 * restored has a pending error. The error will appear to have been 374 * triggered by the current (npx) user instruction even when that 375 * instruction is a no-wait instruction that should not trigger an 376 * error (e.g., fnclex). On at least one 486 system all of the 377 * no-wait instructions are broken the same as frstor, so our 378 * treatment does not amplify the breakage. On at least one 379 * 386/Cyrix 387 system, fnclex works correctly while frstor and 380 * fnsave are broken, so our treatment breaks fnclex if it is the 381 * first FPU instruction after a context switch. 382 */ 383 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && cpu_fxsr) { 384 krateprintf(&badfprate, 385 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n", 386 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit); 387 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 388 lwpsignal(curproc, curthread->td_lwp, SIGFPE); 389 } 390 fpurstor(curthread->td_savefpu); 391 crit_exit(); 392 393 return (1); 394 } 395 396 /* 397 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 398 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 399 * any IRQ13 to be handled immediately, and then ignore it. This routine is 400 * often called at splhigh so it must not use many system services. In 401 * particular, it's much easier to install a special handler than to 402 * guarantee that it's safe to use npxintr() and its supporting code. 403 * 404 * WARNING! This call is made during a switch and the MP lock will be 405 * setup for the new target thread rather then the current thread, so we 406 * cannot do anything here that depends on the *_mplock() functions as 407 * we may trip over their assertions. 408 * 409 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 410 * kernel will always assume that the FP state is 'safe' (will not cause 411 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 412 * setup a custom save area before actually using the FP unit, but it will 413 * not bother calling fninit. This greatly improves kernel performance when 414 * it wishes to use the FP unit. 415 */ 416 void 417 npxsave(union savefpu *addr) 418 { 419 crit_enter(); 420 /*stop_emulating();*/ 421 fpusave(addr); 422 mdcpu->gd_npxthread = NULL; 423 fninit(); 424 /*start_emulating();*/ 425 crit_exit(); 426 } 427 428 static void 429 fpusave(union savefpu *addr) 430 { 431 if (cpu_fxsr) 432 fxsave(addr); 433 else 434 fnsave(addr); 435 } 436 437 /* 438 * Save the FP state to the mcontext structure. 439 * 440 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 441 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 442 */ 443 void 444 npxpush(mcontext_t *mctx) 445 { 446 thread_t td = curthread; 447 448 if (td->td_flags & TDF_USINGFP) { 449 if (mdcpu->gd_npxthread == td) { 450 /* 451 * XXX Note: This is a bit inefficient if the signal 452 * handler uses floating point, extra faults will 453 * occur. 454 */ 455 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 456 npxsave(td->td_savefpu); 457 } else { 458 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 459 } 460 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs)); 461 td->td_flags &= ~TDF_USINGFP; 462 mctx->mc_fpformat = 463 #ifndef CPU_DISABLE_SSE 464 (cpu_fxsr) ? _MC_FPFMT_XMM : 465 #endif 466 _MC_FPFMT_387; 467 } else { 468 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 469 mctx->mc_fpformat = _MC_FPFMT_NODEV; 470 } 471 } 472 473 /* 474 * Restore the FP state from the mcontext structure. 475 */ 476 void 477 npxpop(mcontext_t *mctx) 478 { 479 thread_t td = curthread; 480 481 switch(mctx->mc_ownedfp) { 482 case _MC_FPOWNED_NONE: 483 /* 484 * If the signal handler used the FP unit but the interrupted 485 * code did not, release the FP unit. Clear TDF_USINGFP will 486 * force the FP unit to reinit so the interrupted code sees 487 * a clean slate. 488 */ 489 if (td->td_flags & TDF_USINGFP) { 490 if (td == mdcpu->gd_npxthread) 491 npxsave(td->td_savefpu); 492 td->td_flags &= ~TDF_USINGFP; 493 } 494 break; 495 case _MC_FPOWNED_FPU: 496 case _MC_FPOWNED_PCB: 497 /* 498 * Clear ownership of the FP unit and restore our saved state. 499 * 500 * NOTE: The signal handler may have set-up some FP state and 501 * enabled the FP unit, so we have to restore no matter what. 502 * 503 * XXX: This is bit inefficient, if the code being returned 504 * to is actively using the FP this results in multiple 505 * kernel faults. 506 * 507 * WARNING: The saved state was exposed to userland and may 508 * have to be sanitized to avoid a GP fault in the kernel. 509 */ 510 if (td == mdcpu->gd_npxthread) 511 npxsave(td->td_savefpu); 512 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 513 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && 514 cpu_fxsr) { 515 krateprintf(&badfprate, 516 "pid %d (%s) signal return from user: " 517 "illegal FP MXCSR %08x\n", 518 td->td_proc->p_pid, 519 td->td_proc->p_comm, 520 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 521 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 522 } 523 td->td_flags |= TDF_USINGFP; 524 break; 525 } 526 } 527 528 529 #ifndef CPU_DISABLE_SSE 530 /* 531 * On AuthenticAMD processors, the fxrstor instruction does not restore 532 * the x87's stored last instruction pointer, last data pointer, and last 533 * opcode values, except in the rare case in which the exception summary 534 * (ES) bit in the x87 status word is set to 1. 535 * 536 * In order to avoid leaking this information across processes, we clean 537 * these values by performing a dummy load before executing fxrstor(). 538 */ 539 static double dummy_variable = 0.0; 540 static void 541 fpu_clean_state(void) 542 { 543 u_short status; 544 545 /* 546 * Clear the ES bit in the x87 status word if it is currently 547 * set, in order to avoid causing a fault in the upcoming load. 548 */ 549 fnstsw(&status); 550 if (status & 0x80) 551 fnclex(); 552 553 /* 554 * Load the dummy variable into the x87 stack. This mangles 555 * the x87 stack, but we don't care since we're about to call 556 * fxrstor() anyway. 557 */ 558 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable)); 559 } 560 #endif /* CPU_DISABLE_SSE */ 561 562 static void 563 fpurstor(union savefpu *addr) 564 { 565 #ifndef CPU_DISABLE_SSE 566 if (cpu_fxsr) { 567 fpu_clean_state(); 568 fxrstor(addr); 569 } else { 570 frstor(addr); 571 } 572 #else 573 frstor(addr); 574 #endif 575 } 576