1 /* 2 * Copyright (c) 2006 The DragonFly Project. All rights reserved. 3 * Copyright (c) 1990 William Jolitz. 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The DragonFly Project 8 * by Matthew Dillon <dillon@backplane.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in 18 * the documentation and/or other materials provided with the 19 * distribution. 20 * 3. Neither the name of The DragonFly Project nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific, prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 28 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 39 * $DragonFly: src/sys/platform/vkernel/i386/npx.c,v 1.8 2008/01/29 19:54:56 dillon Exp $ 40 */ 41 42 #include "opt_debug_npx.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/kernel.h> 48 #include <sys/malloc.h> 49 #include <sys/module.h> 50 #include <sys/sysctl.h> 51 #include <sys/proc.h> 52 #include <sys/rman.h> 53 #ifdef NPX_DEBUG 54 #include <sys/syslog.h> 55 #endif 56 #include <sys/signalvar.h> 57 #include <sys/thread2.h> 58 59 #ifndef SMP 60 #include <machine/asmacros.h> 61 #endif 62 #include <machine/cputypes.h> 63 #include <machine/frame.h> 64 #include <machine/md_var.h> 65 #include <machine/pcb.h> 66 #include <machine/psl.h> 67 #ifndef SMP 68 #include <machine/clock.h> 69 #endif 70 #include <machine/specialreg.h> 71 #include <machine/segments.h> 72 #include <machine/globaldata.h> 73 74 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 75 #define fnclex() __asm("fnclex") 76 #define fninit() __asm("fninit") 77 #define fnop() __asm("fnop") 78 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 79 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 80 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 81 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 82 #ifndef CPU_DISABLE_SSE 83 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 84 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 85 #endif 86 87 #ifndef CPU_DISABLE_SSE 88 #define GET_FPU_EXSW_PTR(td) \ 89 (cpu_fxsr ? \ 90 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \ 91 &(td)->td_savefpu->sv_87.sv_ex_sw) 92 #else /* CPU_DISABLE_SSE */ 93 #define GET_FPU_EXSW_PTR(td) \ 94 (&(td)->td_savefpu->sv_87.sv_ex_sw) 95 #endif /* CPU_DISABLE_SSE */ 96 97 typedef u_char bool_t; 98 #ifndef CPU_DISABLE_SSE 99 static void fpu_clean_state(void); 100 #endif 101 102 int cpu_fxsr = 0; 103 104 static struct krate badfprate = { 1 }; 105 106 /*static int npx_attach (device_t dev);*/ 107 static void fpusave (union savefpu *); 108 static void fpurstor (union savefpu *); 109 110 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE) 111 int mmxopt = 1; 112 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0, 113 "MMX/XMM optimized bcopy/copyin/copyout support"); 114 #endif 115 116 static int hw_instruction_sse; 117 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 118 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 119 120 #if 0 121 /* 122 * Attach routine - announce which it is, and wire into system 123 */ 124 int 125 npx_attach(device_t dev) 126 { 127 npxinit(__INITIAL_NPXCW__); 128 return (0); 129 } 130 #endif 131 132 void 133 init_fpu(int supports_sse) 134 { 135 cpu_fxsr = hw_instruction_sse = supports_sse; 136 } 137 138 /* 139 * Initialize the floating point unit. 140 */ 141 void 142 npxinit(u_short control) 143 { 144 static union savefpu dummy __aligned(16); 145 146 /* 147 * fninit has the same h/w bugs as fnsave. Use the detoxified 148 * fnsave to throw away any junk in the fpu. npxsave() initializes 149 * the fpu and sets npxthread = NULL as important side effects. 150 */ 151 npxsave(&dummy); 152 crit_enter(); 153 /*stop_emulating();*/ 154 fldcw(&control); 155 fpusave(curthread->td_savefpu); 156 mdcpu->gd_npxthread = NULL; 157 /*start_emulating();*/ 158 crit_exit(); 159 } 160 161 /* 162 * Free coprocessor (if we have it). 163 */ 164 void 165 npxexit(void) 166 { 167 if (curthread == mdcpu->gd_npxthread) 168 npxsave(curthread->td_savefpu); 169 } 170 171 #if 0 172 /* 173 * The following mechanism is used to ensure that the FPE_... value 174 * that is passed as a trapcode to the signal handler of the user 175 * process does not have more than one bit set. 176 * 177 * Multiple bits may be set if the user process modifies the control 178 * word while a status word bit is already set. While this is a sign 179 * of bad coding, we have no choise than to narrow them down to one 180 * bit, since we must not send a trapcode that is not exactly one of 181 * the FPE_ macros. 182 * 183 * The mechanism has a static table with 127 entries. Each combination 184 * of the 7 FPU status word exception bits directly translates to a 185 * position in this table, where a single FPE_... value is stored. 186 * This FPE_... value stored there is considered the "most important" 187 * of the exception bits and will be sent as the signal code. The 188 * precedence of the bits is based upon Intel Document "Numerical 189 * Applications", Chapter "Special Computational Situations". 190 * 191 * The macro to choose one of these values does these steps: 1) Throw 192 * away status word bits that cannot be masked. 2) Throw away the bits 193 * currently masked in the control word, assuming the user isn't 194 * interested in them anymore. 3) Reinsert status word bit 7 (stack 195 * fault) if it is set, which cannot be masked but must be presered. 196 * 4) Use the remaining bits to point into the trapcode table. 197 * 198 * The 6 maskable bits in order of their preference, as stated in the 199 * above referenced Intel manual: 200 * 1 Invalid operation (FP_X_INV) 201 * 1a Stack underflow 202 * 1b Stack overflow 203 * 1c Operand of unsupported format 204 * 1d SNaN operand. 205 * 2 QNaN operand (not an exception, irrelavant here) 206 * 3 Any other invalid-operation not mentioned above or zero divide 207 * (FP_X_INV, FP_X_DZ) 208 * 4 Denormal operand (FP_X_DNML) 209 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 210 * 6 Inexact result (FP_X_IMP) 211 */ 212 static char fpetable[128] = { 213 0, 214 FPE_FLTINV, /* 1 - INV */ 215 FPE_FLTUND, /* 2 - DNML */ 216 FPE_FLTINV, /* 3 - INV | DNML */ 217 FPE_FLTDIV, /* 4 - DZ */ 218 FPE_FLTINV, /* 5 - INV | DZ */ 219 FPE_FLTDIV, /* 6 - DNML | DZ */ 220 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 221 FPE_FLTOVF, /* 8 - OFL */ 222 FPE_FLTINV, /* 9 - INV | OFL */ 223 FPE_FLTUND, /* A - DNML | OFL */ 224 FPE_FLTINV, /* B - INV | DNML | OFL */ 225 FPE_FLTDIV, /* C - DZ | OFL */ 226 FPE_FLTINV, /* D - INV | DZ | OFL */ 227 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 228 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 229 FPE_FLTUND, /* 10 - UFL */ 230 FPE_FLTINV, /* 11 - INV | UFL */ 231 FPE_FLTUND, /* 12 - DNML | UFL */ 232 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 233 FPE_FLTDIV, /* 14 - DZ | UFL */ 234 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 235 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 236 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 237 FPE_FLTOVF, /* 18 - OFL | UFL */ 238 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 239 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 240 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 241 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 242 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 243 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 244 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 245 FPE_FLTRES, /* 20 - IMP */ 246 FPE_FLTINV, /* 21 - INV | IMP */ 247 FPE_FLTUND, /* 22 - DNML | IMP */ 248 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 249 FPE_FLTDIV, /* 24 - DZ | IMP */ 250 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 251 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 252 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 253 FPE_FLTOVF, /* 28 - OFL | IMP */ 254 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 255 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 256 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 257 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 258 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 259 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 260 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 261 FPE_FLTUND, /* 30 - UFL | IMP */ 262 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 263 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 264 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 265 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 266 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 267 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 268 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 269 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 270 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 271 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 272 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 273 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 274 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 275 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 276 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 277 FPE_FLTSUB, /* 40 - STK */ 278 FPE_FLTSUB, /* 41 - INV | STK */ 279 FPE_FLTUND, /* 42 - DNML | STK */ 280 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 281 FPE_FLTDIV, /* 44 - DZ | STK */ 282 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 283 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 284 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 285 FPE_FLTOVF, /* 48 - OFL | STK */ 286 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 287 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 288 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 289 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 290 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 291 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 292 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 293 FPE_FLTUND, /* 50 - UFL | STK */ 294 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 295 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 296 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 297 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 298 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 299 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 300 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 301 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 302 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 303 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 304 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 305 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 306 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 307 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 308 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 309 FPE_FLTRES, /* 60 - IMP | STK */ 310 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 311 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 312 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 313 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 314 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 315 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 316 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 317 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 318 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 319 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 320 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 321 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 322 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 323 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 324 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 325 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 326 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 327 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 328 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 329 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 330 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 331 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 332 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 333 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 334 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 335 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 336 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 337 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 338 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 339 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 340 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 341 }; 342 #endif 343 344 /* 345 * Implement the device not available (DNA) exception. gd_npxthread had 346 * better be NULL. Restore the current thread's FP state and set gd_npxthread 347 * to curthread. 348 * 349 * Interrupts are enabled and preemption can occur. Enter a critical 350 * section to stabilize the FP state. 351 */ 352 int 353 npxdna(struct trapframe *frame) 354 { 355 thread_t td = curthread; 356 u_long *exstat; 357 int didinit = 0; 358 359 if (mdcpu->gd_npxthread != NULL) { 360 kprintf("npxdna: npxthread = %p, curthread = %p\n", 361 mdcpu->gd_npxthread, td); 362 panic("npxdna"); 363 } 364 365 /* 366 * Setup the initial saved state if the thread has never before 367 * used the FP unit. This also occurs when a thread pushes a 368 * signal handler and uses FP in the handler. 369 */ 370 if ((curthread->td_flags & TDF_USINGFP) == 0) { 371 curthread->td_flags |= TDF_USINGFP; 372 npxinit(__INITIAL_NPXCW__); 373 didinit = 1; 374 } 375 376 /* 377 * The setting of gd_npxthread and the call to fpurstor() must not 378 * be preempted by an interrupt thread or we will take an npxdna 379 * trap and potentially save our current fpstate (which is garbage) 380 * and then restore the garbage rather then the originally saved 381 * fpstate. 382 */ 383 crit_enter(); 384 /*stop_emulating();*/ 385 /* 386 * Record new context early in case frstor causes an IRQ13. 387 */ 388 mdcpu->gd_npxthread = td; 389 exstat = GET_FPU_EXSW_PTR(td); 390 *exstat = 0; 391 /* 392 * The following frstor may cause an IRQ13 when the state being 393 * restored has a pending error. The error will appear to have been 394 * triggered by the current (npx) user instruction even when that 395 * instruction is a no-wait instruction that should not trigger an 396 * error (e.g., fnclex). On at least one 486 system all of the 397 * no-wait instructions are broken the same as frstor, so our 398 * treatment does not amplify the breakage. On at least one 399 * 386/Cyrix 387 system, fnclex works correctly while frstor and 400 * fnsave are broken, so our treatment breaks fnclex if it is the 401 * first FPU instruction after a context switch. 402 */ 403 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && cpu_fxsr) { 404 krateprintf(&badfprate, 405 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n", 406 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit); 407 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 408 lwpsignal(curproc, curthread->td_lwp, SIGFPE); 409 } 410 fpurstor(curthread->td_savefpu); 411 crit_exit(); 412 413 return (1); 414 } 415 416 /* 417 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 418 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 419 * any IRQ13 to be handled immediately, and then ignore it. This routine is 420 * often called at splhigh so it must not use many system services. In 421 * particular, it's much easier to install a special handler than to 422 * guarantee that it's safe to use npxintr() and its supporting code. 423 * 424 * WARNING! This call is made during a switch and the MP lock will be 425 * setup for the new target thread rather then the current thread, so we 426 * cannot do anything here that depends on the *_mplock() functions as 427 * we may trip over their assertions. 428 * 429 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 430 * kernel will always assume that the FP state is 'safe' (will not cause 431 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 432 * setup a custom save area before actually using the FP unit, but it will 433 * not bother calling fninit. This greatly improves kernel performance when 434 * it wishes to use the FP unit. 435 */ 436 void 437 npxsave(union savefpu *addr) 438 { 439 crit_enter(); 440 /*stop_emulating();*/ 441 fpusave(addr); 442 mdcpu->gd_npxthread = NULL; 443 fninit(); 444 /*start_emulating();*/ 445 crit_exit(); 446 } 447 448 static void 449 fpusave(union savefpu *addr) 450 { 451 if (cpu_fxsr) 452 fxsave(addr); 453 else 454 fnsave(addr); 455 } 456 457 /* 458 * Save the FP state to the mcontext structure. 459 * 460 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 461 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 462 */ 463 void 464 npxpush(mcontext_t *mctx) 465 { 466 thread_t td = curthread; 467 468 if (td->td_flags & TDF_USINGFP) { 469 if (mdcpu->gd_npxthread == td) { 470 /* 471 * XXX Note: This is a bit inefficient if the signal 472 * handler uses floating point, extra faults will 473 * occur. 474 */ 475 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 476 npxsave(td->td_savefpu); 477 } else { 478 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 479 } 480 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs)); 481 td->td_flags &= ~TDF_USINGFP; 482 mctx->mc_fpformat = 483 #ifndef CPU_DISABLE_SSE 484 (cpu_fxsr) ? _MC_FPFMT_XMM : 485 #endif 486 _MC_FPFMT_387; 487 } else { 488 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 489 mctx->mc_fpformat = _MC_FPFMT_NODEV; 490 } 491 } 492 493 /* 494 * Restore the FP state from the mcontext structure. 495 */ 496 void 497 npxpop(mcontext_t *mctx) 498 { 499 thread_t td = curthread; 500 501 switch(mctx->mc_ownedfp) { 502 case _MC_FPOWNED_NONE: 503 /* 504 * If the signal handler used the FP unit but the interrupted 505 * code did not, release the FP unit. Clear TDF_USINGFP will 506 * force the FP unit to reinit so the interrupted code sees 507 * a clean slate. 508 */ 509 if (td->td_flags & TDF_USINGFP) { 510 if (td == mdcpu->gd_npxthread) 511 npxsave(td->td_savefpu); 512 td->td_flags &= ~TDF_USINGFP; 513 } 514 break; 515 case _MC_FPOWNED_FPU: 516 case _MC_FPOWNED_PCB: 517 /* 518 * Clear ownership of the FP unit and restore our saved state. 519 * 520 * NOTE: The signal handler may have set-up some FP state and 521 * enabled the FP unit, so we have to restore no matter what. 522 * 523 * XXX: This is bit inefficient, if the code being returned 524 * to is actively using the FP this results in multiple 525 * kernel faults. 526 * 527 * WARNING: The saved state was exposed to userland and may 528 * have to be sanitized to avoid a GP fault in the kernel. 529 */ 530 if (td == mdcpu->gd_npxthread) 531 npxsave(td->td_savefpu); 532 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 533 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && 534 cpu_fxsr) { 535 krateprintf(&badfprate, 536 "pid %d (%s) signal return from user: " 537 "illegal FP MXCSR %08x\n", 538 td->td_proc->p_pid, 539 td->td_proc->p_comm, 540 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 541 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 542 } 543 td->td_flags |= TDF_USINGFP; 544 break; 545 } 546 } 547 548 549 #ifndef CPU_DISABLE_SSE 550 /* 551 * On AuthenticAMD processors, the fxrstor instruction does not restore 552 * the x87's stored last instruction pointer, last data pointer, and last 553 * opcode values, except in the rare case in which the exception summary 554 * (ES) bit in the x87 status word is set to 1. 555 * 556 * In order to avoid leaking this information across processes, we clean 557 * these values by performing a dummy load before executing fxrstor(). 558 */ 559 static double dummy_variable = 0.0; 560 static void 561 fpu_clean_state(void) 562 { 563 u_short status; 564 565 /* 566 * Clear the ES bit in the x87 status word if it is currently 567 * set, in order to avoid causing a fault in the upcoming load. 568 */ 569 fnstsw(&status); 570 if (status & 0x80) 571 fnclex(); 572 573 /* 574 * Load the dummy variable into the x87 stack. This mangles 575 * the x87 stack, but we don't care since we're about to call 576 * fxrstor() anyway. 577 */ 578 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable)); 579 } 580 #endif /* CPU_DISABLE_SSE */ 581 582 static void 583 fpurstor(union savefpu *addr) 584 { 585 #ifndef CPU_DISABLE_SSE 586 if (cpu_fxsr) { 587 fpu_clean_state(); 588 fxrstor(addr); 589 } else { 590 frstor(addr); 591 } 592 #else 593 frstor(addr); 594 #endif 595 } 596