1 /* 2 * Copyright (c) 2006 The DragonFly Project. All rights reserved. 3 * Copyright (c) 1990 William Jolitz. 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The DragonFly Project 8 * by Matthew Dillon <dillon@backplane.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in 18 * the documentation and/or other materials provided with the 19 * distribution. 20 * 3. Neither the name of The DragonFly Project nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific, prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 28 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 39 */ 40 41 #include "opt_debug_npx.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/bus.h> 46 #include <sys/kernel.h> 47 #include <sys/malloc.h> 48 #include <sys/module.h> 49 #include <sys/sysctl.h> 50 #include <sys/proc.h> 51 #include <sys/rman.h> 52 #ifdef NPX_DEBUG 53 #include <sys/syslog.h> 54 #endif 55 #include <sys/signalvar.h> 56 #include <sys/thread2.h> 57 58 #ifndef SMP 59 #include <machine/asmacros.h> 60 #endif 61 #include <machine/cputypes.h> 62 #include <machine/frame.h> 63 #include <machine/md_var.h> 64 #include <machine/pcb.h> 65 #include <machine/psl.h> 66 #ifndef SMP 67 #include <machine/clock.h> 68 #endif 69 #include <machine/specialreg.h> 70 #include <machine/segments.h> 71 #include <machine/globaldata.h> 72 73 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 74 #define fnclex() __asm("fnclex") 75 #define fninit() __asm("fninit") 76 #define fnop() __asm("fnop") 77 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 78 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 79 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 80 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 81 #ifndef CPU_DISABLE_SSE 82 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 83 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 84 #endif 85 86 typedef u_char bool_t; 87 #ifndef CPU_DISABLE_SSE 88 static void fpu_clean_state(void); 89 #endif 90 91 int cpu_fxsr = 0; 92 93 static struct krate badfprate = { 1 }; 94 95 /*static int npx_attach (device_t dev);*/ 96 static void fpusave (union savefpu *); 97 static void fpurstor (union savefpu *); 98 99 #ifndef CPU_DISABLE_SSE 100 int mmxopt = 1; 101 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0, 102 "MMX/XMM optimized bcopy/copyin/copyout support"); 103 #endif 104 105 static int hw_instruction_sse; 106 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 107 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 108 109 #if 0 110 /* 111 * Attach routine - announce which it is, and wire into system 112 */ 113 int 114 npx_attach(device_t dev) 115 { 116 npxinit(__INITIAL_NPXCW__); 117 return (0); 118 } 119 #endif 120 121 void 122 init_fpu(int supports_sse) 123 { 124 cpu_fxsr = hw_instruction_sse = supports_sse; 125 } 126 127 /* 128 * Initialize the floating point unit. 129 */ 130 void 131 npxinit(u_short control) 132 { 133 static union savefpu dummy __aligned(16); 134 135 /* 136 * fninit has the same h/w bugs as fnsave. Use the detoxified 137 * fnsave to throw away any junk in the fpu. npxsave() initializes 138 * the fpu and sets npxthread = NULL as important side effects. 139 */ 140 npxsave(&dummy); 141 crit_enter(); 142 /*stop_emulating();*/ 143 fldcw(&control); 144 fpusave(curthread->td_savefpu); 145 mdcpu->gd_npxthread = NULL; 146 /*start_emulating();*/ 147 crit_exit(); 148 } 149 150 /* 151 * Free coprocessor (if we have it). 152 */ 153 void 154 npxexit(void) 155 { 156 if (curthread == mdcpu->gd_npxthread) 157 npxsave(curthread->td_savefpu); 158 } 159 160 #if 0 161 /* 162 * The following mechanism is used to ensure that the FPE_... value 163 * that is passed as a trapcode to the signal handler of the user 164 * process does not have more than one bit set. 165 * 166 * Multiple bits may be set if the user process modifies the control 167 * word while a status word bit is already set. While this is a sign 168 * of bad coding, we have no choise than to narrow them down to one 169 * bit, since we must not send a trapcode that is not exactly one of 170 * the FPE_ macros. 171 * 172 * The mechanism has a static table with 127 entries. Each combination 173 * of the 7 FPU status word exception bits directly translates to a 174 * position in this table, where a single FPE_... value is stored. 175 * This FPE_... value stored there is considered the "most important" 176 * of the exception bits and will be sent as the signal code. The 177 * precedence of the bits is based upon Intel Document "Numerical 178 * Applications", Chapter "Special Computational Situations". 179 * 180 * The macro to choose one of these values does these steps: 1) Throw 181 * away status word bits that cannot be masked. 2) Throw away the bits 182 * currently masked in the control word, assuming the user isn't 183 * interested in them anymore. 3) Reinsert status word bit 7 (stack 184 * fault) if it is set, which cannot be masked but must be presered. 185 * 4) Use the remaining bits to point into the trapcode table. 186 * 187 * The 6 maskable bits in order of their preference, as stated in the 188 * above referenced Intel manual: 189 * 1 Invalid operation (FP_X_INV) 190 * 1a Stack underflow 191 * 1b Stack overflow 192 * 1c Operand of unsupported format 193 * 1d SNaN operand. 194 * 2 QNaN operand (not an exception, irrelavant here) 195 * 3 Any other invalid-operation not mentioned above or zero divide 196 * (FP_X_INV, FP_X_DZ) 197 * 4 Denormal operand (FP_X_DNML) 198 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 199 * 6 Inexact result (FP_X_IMP) 200 */ 201 static char fpetable[128] = { 202 0, 203 FPE_FLTINV, /* 1 - INV */ 204 FPE_FLTUND, /* 2 - DNML */ 205 FPE_FLTINV, /* 3 - INV | DNML */ 206 FPE_FLTDIV, /* 4 - DZ */ 207 FPE_FLTINV, /* 5 - INV | DZ */ 208 FPE_FLTDIV, /* 6 - DNML | DZ */ 209 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 210 FPE_FLTOVF, /* 8 - OFL */ 211 FPE_FLTINV, /* 9 - INV | OFL */ 212 FPE_FLTUND, /* A - DNML | OFL */ 213 FPE_FLTINV, /* B - INV | DNML | OFL */ 214 FPE_FLTDIV, /* C - DZ | OFL */ 215 FPE_FLTINV, /* D - INV | DZ | OFL */ 216 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 217 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 218 FPE_FLTUND, /* 10 - UFL */ 219 FPE_FLTINV, /* 11 - INV | UFL */ 220 FPE_FLTUND, /* 12 - DNML | UFL */ 221 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 222 FPE_FLTDIV, /* 14 - DZ | UFL */ 223 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 224 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 225 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 226 FPE_FLTOVF, /* 18 - OFL | UFL */ 227 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 228 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 229 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 230 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 231 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 232 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 233 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 234 FPE_FLTRES, /* 20 - IMP */ 235 FPE_FLTINV, /* 21 - INV | IMP */ 236 FPE_FLTUND, /* 22 - DNML | IMP */ 237 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 238 FPE_FLTDIV, /* 24 - DZ | IMP */ 239 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 240 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 241 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 242 FPE_FLTOVF, /* 28 - OFL | IMP */ 243 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 244 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 245 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 246 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 247 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 248 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 249 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 250 FPE_FLTUND, /* 30 - UFL | IMP */ 251 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 252 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 253 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 254 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 255 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 256 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 257 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 258 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 259 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 260 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 261 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 262 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 263 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 264 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 265 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 266 FPE_FLTSUB, /* 40 - STK */ 267 FPE_FLTSUB, /* 41 - INV | STK */ 268 FPE_FLTUND, /* 42 - DNML | STK */ 269 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 270 FPE_FLTDIV, /* 44 - DZ | STK */ 271 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 272 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 273 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 274 FPE_FLTOVF, /* 48 - OFL | STK */ 275 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 276 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 277 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 278 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 279 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 280 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 281 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 282 FPE_FLTUND, /* 50 - UFL | STK */ 283 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 284 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 285 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 286 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 287 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 288 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 289 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 290 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 291 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 292 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 293 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 294 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 295 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 296 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 297 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 298 FPE_FLTRES, /* 60 - IMP | STK */ 299 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 300 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 301 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 302 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 303 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 304 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 305 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 306 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 307 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 308 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 309 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 310 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 311 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 312 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 313 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 314 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 315 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 316 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 317 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 318 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 319 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 320 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 321 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 322 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 323 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 324 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 325 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 326 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 327 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 328 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 329 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 330 }; 331 #endif 332 333 /* 334 * Implement the device not available (DNA) exception. gd_npxthread had 335 * better be NULL. Restore the current thread's FP state and set gd_npxthread 336 * to curthread. 337 * 338 * Interrupts are enabled and preemption can occur. Enter a critical 339 * section to stabilize the FP state. 340 */ 341 int 342 npxdna(struct trapframe *frame) 343 { 344 thread_t td = curthread; 345 int didinit = 0; 346 347 if (mdcpu->gd_npxthread != NULL) { 348 kprintf("npxdna: npxthread = %p, curthread = %p\n", 349 mdcpu->gd_npxthread, td); 350 panic("npxdna"); 351 } 352 353 /* 354 * Setup the initial saved state if the thread has never before 355 * used the FP unit. This also occurs when a thread pushes a 356 * signal handler and uses FP in the handler. 357 */ 358 if ((curthread->td_flags & TDF_USINGFP) == 0) { 359 curthread->td_flags |= TDF_USINGFP; 360 npxinit(__INITIAL_NPXCW__); 361 didinit = 1; 362 } 363 364 /* 365 * The setting of gd_npxthread and the call to fpurstor() must not 366 * be preempted by an interrupt thread or we will take an npxdna 367 * trap and potentially save our current fpstate (which is garbage) 368 * and then restore the garbage rather then the originally saved 369 * fpstate. 370 */ 371 crit_enter(); 372 /*stop_emulating();*/ 373 /* 374 * Record new context early in case frstor causes an IRQ13. 375 */ 376 mdcpu->gd_npxthread = td; 377 /* 378 * The following frstor may cause an IRQ13 when the state being 379 * restored has a pending error. The error will appear to have been 380 * triggered by the current (npx) user instruction even when that 381 * instruction is a no-wait instruction that should not trigger an 382 * error (e.g., fnclex). On at least one 486 system all of the 383 * no-wait instructions are broken the same as frstor, so our 384 * treatment does not amplify the breakage. On at least one 385 * 386/Cyrix 387 system, fnclex works correctly while frstor and 386 * fnsave are broken, so our treatment breaks fnclex if it is the 387 * first FPU instruction after a context switch. 388 */ 389 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && cpu_fxsr) { 390 krateprintf(&badfprate, 391 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n", 392 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit); 393 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 394 lwpsignal(curproc, curthread->td_lwp, SIGFPE); 395 } 396 fpurstor(curthread->td_savefpu); 397 crit_exit(); 398 399 return (1); 400 } 401 402 /* 403 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 404 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 405 * any IRQ13 to be handled immediately, and then ignore it. This routine is 406 * often called at splhigh so it must not use many system services. In 407 * particular, it's much easier to install a special handler than to 408 * guarantee that it's safe to use npxintr() and its supporting code. 409 * 410 * WARNING! This call is made during a switch and the MP lock will be 411 * setup for the new target thread rather then the current thread, so we 412 * cannot do anything here that depends on the *_mplock() functions as 413 * we may trip over their assertions. 414 * 415 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 416 * kernel will always assume that the FP state is 'safe' (will not cause 417 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 418 * setup a custom save area before actually using the FP unit, but it will 419 * not bother calling fninit. This greatly improves kernel performance when 420 * it wishes to use the FP unit. 421 */ 422 void 423 npxsave(union savefpu *addr) 424 { 425 crit_enter(); 426 /*stop_emulating();*/ 427 fpusave(addr); 428 mdcpu->gd_npxthread = NULL; 429 fninit(); 430 /*start_emulating();*/ 431 crit_exit(); 432 } 433 434 static void 435 fpusave(union savefpu *addr) 436 { 437 if (cpu_fxsr) 438 fxsave(addr); 439 else 440 fnsave(addr); 441 } 442 443 /* 444 * Save the FP state to the mcontext structure. 445 * 446 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 447 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 448 */ 449 void 450 npxpush(mcontext_t *mctx) 451 { 452 thread_t td = curthread; 453 454 if (td->td_flags & TDF_USINGFP) { 455 if (mdcpu->gd_npxthread == td) { 456 /* 457 * XXX Note: This is a bit inefficient if the signal 458 * handler uses floating point, extra faults will 459 * occur. 460 */ 461 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 462 npxsave(td->td_savefpu); 463 } else { 464 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 465 } 466 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs)); 467 td->td_flags &= ~TDF_USINGFP; 468 mctx->mc_fpformat = 469 #ifndef CPU_DISABLE_SSE 470 (cpu_fxsr) ? _MC_FPFMT_XMM : 471 #endif 472 _MC_FPFMT_387; 473 } else { 474 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 475 mctx->mc_fpformat = _MC_FPFMT_NODEV; 476 } 477 } 478 479 /* 480 * Restore the FP state from the mcontext structure. 481 */ 482 void 483 npxpop(mcontext_t *mctx) 484 { 485 thread_t td = curthread; 486 487 switch(mctx->mc_ownedfp) { 488 case _MC_FPOWNED_NONE: 489 /* 490 * If the signal handler used the FP unit but the interrupted 491 * code did not, release the FP unit. Clear TDF_USINGFP will 492 * force the FP unit to reinit so the interrupted code sees 493 * a clean slate. 494 */ 495 if (td->td_flags & TDF_USINGFP) { 496 if (td == mdcpu->gd_npxthread) 497 npxsave(td->td_savefpu); 498 td->td_flags &= ~TDF_USINGFP; 499 } 500 break; 501 case _MC_FPOWNED_FPU: 502 case _MC_FPOWNED_PCB: 503 /* 504 * Clear ownership of the FP unit and restore our saved state. 505 * 506 * NOTE: The signal handler may have set-up some FP state and 507 * enabled the FP unit, so we have to restore no matter what. 508 * 509 * XXX: This is bit inefficient, if the code being returned 510 * to is actively using the FP this results in multiple 511 * kernel faults. 512 * 513 * WARNING: The saved state was exposed to userland and may 514 * have to be sanitized to avoid a GP fault in the kernel. 515 */ 516 if (td == mdcpu->gd_npxthread) 517 npxsave(td->td_savefpu); 518 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 519 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && 520 cpu_fxsr) { 521 krateprintf(&badfprate, 522 "pid %d (%s) signal return from user: " 523 "illegal FP MXCSR %08x\n", 524 td->td_proc->p_pid, 525 td->td_proc->p_comm, 526 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 527 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 528 } 529 td->td_flags |= TDF_USINGFP; 530 break; 531 } 532 } 533 534 535 #ifndef CPU_DISABLE_SSE 536 /* 537 * On AuthenticAMD processors, the fxrstor instruction does not restore 538 * the x87's stored last instruction pointer, last data pointer, and last 539 * opcode values, except in the rare case in which the exception summary 540 * (ES) bit in the x87 status word is set to 1. 541 * 542 * In order to avoid leaking this information across processes, we clean 543 * these values by performing a dummy load before executing fxrstor(). 544 */ 545 static double dummy_variable = 0.0; 546 static void 547 fpu_clean_state(void) 548 { 549 u_short status; 550 551 /* 552 * Clear the ES bit in the x87 status word if it is currently 553 * set, in order to avoid causing a fault in the upcoming load. 554 */ 555 fnstsw(&status); 556 if (status & 0x80) 557 fnclex(); 558 559 /* 560 * Load the dummy variable into the x87 stack. This mangles 561 * the x87 stack, but we don't care since we're about to call 562 * fxrstor() anyway. 563 */ 564 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable)); 565 } 566 #endif /* CPU_DISABLE_SSE */ 567 568 static void 569 fpurstor(union savefpu *addr) 570 { 571 #ifndef CPU_DISABLE_SSE 572 if (cpu_fxsr) { 573 fpu_clean_state(); 574 fxrstor(addr); 575 } else { 576 frstor(addr); 577 } 578 #else 579 frstor(addr); 580 #endif 581 } 582