1 /* 2 * Copyright (c) 2006 The DragonFly Project. All rights reserved. 3 * Copyright (c) 1990 William Jolitz. 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The DragonFly Project 8 * by Matthew Dillon <dillon@backplane.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in 18 * the documentation and/or other materials provided with the 19 * distribution. 20 * 3. Neither the name of The DragonFly Project nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific, prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 28 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/sysctl.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/signalvar.h> 51 #include <sys/thread2.h> 52 53 #include <machine/cputypes.h> 54 #include <machine/frame.h> 55 #include <machine/md_var.h> 56 #include <machine/pcb.h> 57 #include <machine/psl.h> 58 #include <machine/specialreg.h> 59 #include <machine/segments.h> 60 #include <machine/globaldata.h> 61 62 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 63 #define fnclex() __asm("fnclex") 64 #define fninit() __asm("fninit") 65 #define fnop() __asm("fnop") 66 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 67 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 68 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 69 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 70 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 71 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 72 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 73 74 static void fpu_clean_state(void); 75 /*static int npx_attach (device_t dev);*/ 76 77 static struct krate badfprate = { 1 }; 78 79 int cpu_fxsr = 0; 80 uint32_t npx_mxcsr_mask = 0xFFBF; 81 82 int mmxopt = 1; 83 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0, 84 "MMX/XMM optimized bcopy/copyin/copyout support"); 85 86 static int hw_instruction_sse; 87 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 88 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 89 90 #if 0 91 /* 92 * Attach routine - announce which it is, and wire into system 93 */ 94 static int 95 npx_attach(device_t dev) 96 { 97 npxinit(); 98 return (0); 99 } 100 #endif 101 102 void 103 init_fpu(int supports_sse) 104 { 105 cpu_fxsr = hw_instruction_sse = supports_sse; 106 npxprobemask(); 107 } 108 109 /* 110 * Probe the npx_mxcsr_mask 111 */ 112 void npxprobemask(void) 113 { 114 /*64-Byte alignment required for xsave*/ 115 static union savefpu dummy __aligned(64); 116 117 crit_enter(); 118 /*stop_emulating();*/ 119 fxsave(&dummy); 120 npx_mxcsr_mask = ((uint32_t *)&dummy)[7]; 121 /*stop_emulating();*/ 122 crit_exit(); 123 } 124 125 126 /* 127 * Initialize the floating point unit. 128 */ 129 void npxinit(void) 130 { 131 static union savefpu dummy __aligned(16); 132 u_short control = __INITIAL_FPUCW__; 133 u_int mxcsr = __INITIAL_MXCSR__; 134 135 /* 136 * fninit has the same h/w bugs as fnsave. Use the detoxified 137 * fnsave to throw away any junk in the fpu. npxsave() initializes 138 * the fpu and sets npxthread = NULL as important side effects. 139 */ 140 npxsave(&dummy); 141 crit_enter(); 142 /*stop_emulating();*/ 143 fldcw(&control); 144 ldmxcsr(mxcsr); 145 fpusave(curthread->td_savefpu, 0); 146 mdcpu->gd_npxthread = NULL; 147 /*start_emulating();*/ 148 crit_exit(); 149 } 150 151 /* 152 * Free coprocessor (if we have it). 153 */ 154 void 155 npxexit(void) 156 { 157 if (curthread == mdcpu->gd_npxthread) 158 npxsave(curthread->td_savefpu); 159 } 160 161 #if 0 162 /* 163 * The following mechanism is used to ensure that the FPE_... value 164 * that is passed as a trapcode to the signal handler of the user 165 * process does not have more than one bit set. 166 * 167 * Multiple bits may be set if the user process modifies the control 168 * word while a status word bit is already set. While this is a sign 169 * of bad coding, we have no choise than to narrow them down to one 170 * bit, since we must not send a trapcode that is not exactly one of 171 * the FPE_ macros. 172 * 173 * The mechanism has a static table with 127 entries. Each combination 174 * of the 7 FPU status word exception bits directly translates to a 175 * position in this table, where a single FPE_... value is stored. 176 * This FPE_... value stored there is considered the "most important" 177 * of the exception bits and will be sent as the signal code. The 178 * precedence of the bits is based upon Intel Document "Numerical 179 * Applications", Chapter "Special Computational Situations". 180 * 181 * The macro to choose one of these values does these steps: 1) Throw 182 * away status word bits that cannot be masked. 2) Throw away the bits 183 * currently masked in the control word, assuming the user isn't 184 * interested in them anymore. 3) Reinsert status word bit 7 (stack 185 * fault) if it is set, which cannot be masked but must be presered. 186 * 4) Use the remaining bits to point into the trapcode table. 187 * 188 * The 6 maskable bits in order of their preference, as stated in the 189 * above referenced Intel manual: 190 * 1 Invalid operation (FP_X_INV) 191 * 1a Stack underflow 192 * 1b Stack overflow 193 * 1c Operand of unsupported format 194 * 1d SNaN operand. 195 * 2 QNaN operand (not an exception, irrelavant here) 196 * 3 Any other invalid-operation not mentioned above or zero divide 197 * (FP_X_INV, FP_X_DZ) 198 * 4 Denormal operand (FP_X_DNML) 199 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 200 * 6 Inexact result (FP_X_IMP) 201 */ 202 static char fpetable[128] = { 203 0, 204 FPE_FLTINV, /* 1 - INV */ 205 FPE_FLTUND, /* 2 - DNML */ 206 FPE_FLTINV, /* 3 - INV | DNML */ 207 FPE_FLTDIV, /* 4 - DZ */ 208 FPE_FLTINV, /* 5 - INV | DZ */ 209 FPE_FLTDIV, /* 6 - DNML | DZ */ 210 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 211 FPE_FLTOVF, /* 8 - OFL */ 212 FPE_FLTINV, /* 9 - INV | OFL */ 213 FPE_FLTUND, /* A - DNML | OFL */ 214 FPE_FLTINV, /* B - INV | DNML | OFL */ 215 FPE_FLTDIV, /* C - DZ | OFL */ 216 FPE_FLTINV, /* D - INV | DZ | OFL */ 217 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 218 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 219 FPE_FLTUND, /* 10 - UFL */ 220 FPE_FLTINV, /* 11 - INV | UFL */ 221 FPE_FLTUND, /* 12 - DNML | UFL */ 222 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 223 FPE_FLTDIV, /* 14 - DZ | UFL */ 224 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 225 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 226 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 227 FPE_FLTOVF, /* 18 - OFL | UFL */ 228 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 229 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 230 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 231 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 232 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 233 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 234 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 235 FPE_FLTRES, /* 20 - IMP */ 236 FPE_FLTINV, /* 21 - INV | IMP */ 237 FPE_FLTUND, /* 22 - DNML | IMP */ 238 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 239 FPE_FLTDIV, /* 24 - DZ | IMP */ 240 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 241 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 242 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 243 FPE_FLTOVF, /* 28 - OFL | IMP */ 244 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 245 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 246 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 247 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 248 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 249 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 250 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 251 FPE_FLTUND, /* 30 - UFL | IMP */ 252 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 253 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 254 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 255 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 256 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 257 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 258 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 259 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 260 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 261 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 262 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 263 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 264 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 265 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 266 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 267 FPE_FLTSUB, /* 40 - STK */ 268 FPE_FLTSUB, /* 41 - INV | STK */ 269 FPE_FLTUND, /* 42 - DNML | STK */ 270 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 271 FPE_FLTDIV, /* 44 - DZ | STK */ 272 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 273 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 274 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 275 FPE_FLTOVF, /* 48 - OFL | STK */ 276 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 277 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 278 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 279 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 280 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 281 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 282 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 283 FPE_FLTUND, /* 50 - UFL | STK */ 284 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 285 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 286 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 287 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 288 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 289 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 290 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 291 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 292 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 293 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 294 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 295 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 296 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 297 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 298 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 299 FPE_FLTRES, /* 60 - IMP | STK */ 300 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 301 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 302 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 303 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 304 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 305 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 306 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 307 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 308 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 309 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 310 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 311 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 312 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 313 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 314 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 315 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 316 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 317 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 318 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 319 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 320 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 321 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 322 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 323 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 324 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 325 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 326 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 327 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 328 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 329 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 330 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 331 }; 332 #endif 333 334 /* 335 * Implement the device not available (DNA) exception. gd_npxthread had 336 * better be NULL. Restore the current thread's FP state and set gd_npxthread 337 * to curthread. 338 * 339 * Interrupts are enabled and preemption can occur. Enter a critical 340 * section to stabilize the FP state. 341 */ 342 int 343 npxdna(struct trapframe *frame) 344 { 345 thread_t td = curthread; 346 int didinit = 0; 347 348 if (mdcpu->gd_npxthread != NULL) { 349 kprintf("npxdna: npxthread = %p, curthread = %p\n", 350 mdcpu->gd_npxthread, td); 351 panic("npxdna"); 352 } 353 354 /* 355 * Setup the initial saved state if the thread has never before 356 * used the FP unit. This also occurs when a thread pushes a 357 * signal handler and uses FP in the handler. 358 */ 359 if ((curthread->td_flags & TDF_USINGFP) == 0) { 360 curthread->td_flags |= TDF_USINGFP; 361 npxinit(); 362 didinit = 1; 363 } 364 365 /* 366 * The setting of gd_npxthread and the call to fpurstor() must not 367 * be preempted by an interrupt thread or we will take an npxdna 368 * trap and potentially save our current fpstate (which is garbage) 369 * and then restore the garbage rather then the originally saved 370 * fpstate. 371 */ 372 crit_enter(); 373 /*stop_emulating();*/ 374 /* 375 * Record new context early in case frstor causes an IRQ13. 376 */ 377 mdcpu->gd_npxthread = td; 378 /* 379 * The following frstor may cause an IRQ13 when the state being 380 * restored has a pending error. The error will appear to have been 381 * triggered by the current (npx) user instruction even when that 382 * instruction is a no-wait instruction that should not trigger an 383 * error (e.g., fnclex). On at least one 486 system all of the 384 * no-wait instructions are broken the same as frstor, so our 385 * treatment does not amplify the breakage. On at least one 386 * 386/Cyrix 387 system, fnclex works correctly while frstor and 387 * fnsave are broken, so our treatment breaks fnclex if it is the 388 * first FPU instruction after a context switch. 389 */ 390 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && cpu_fxsr) { 391 krateprintf(&badfprate, 392 "FXRSTOR: illegal FP MXCSR %08x didinit = %d\n", 393 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit); 394 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 395 lwpsignal(curproc, curthread->td_lwp, SIGFPE); 396 } 397 fpurstor(curthread->td_savefpu, 0); 398 crit_exit(); 399 400 return (1); 401 } 402 403 /* 404 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 405 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 406 * any IRQ13 to be handled immediately, and then ignore it. This routine is 407 * often called at splhigh so it must not use many system services. In 408 * particular, it's much easier to install a special handler than to 409 * guarantee that it's safe to use npxintr() and its supporting code. 410 * 411 * WARNING! This call is made during a switch and the MP lock will be 412 * setup for the new target thread rather then the current thread, so we 413 * cannot do anything here that depends on the *_mplock() functions as 414 * we may trip over their assertions. 415 * 416 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 417 * kernel will always assume that the FP state is 'safe' (will not cause 418 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 419 * setup a custom save area before actually using the FP unit, but it will 420 * not bother calling fninit. This greatly improves kernel performance when 421 * it wishes to use the FP unit. 422 */ 423 void 424 npxsave(union savefpu *addr) 425 { 426 crit_enter(); 427 /*stop_emulating();*/ 428 fpusave(addr, 0); 429 mdcpu->gd_npxthread = NULL; 430 fninit(); 431 /*start_emulating();*/ 432 crit_exit(); 433 } 434 435 void 436 fpusave(union savefpu *addr, uint64_t mask __unused) 437 { 438 if (cpu_fxsr) 439 fxsave(addr); 440 else 441 fnsave(addr); 442 } 443 444 /* 445 * Save the FP state to the mcontext structure. 446 * 447 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 448 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 449 */ 450 void 451 npxpush(mcontext_t *mctx) 452 { 453 thread_t td = curthread; 454 455 if (td->td_flags & TDF_USINGFP) { 456 if (mdcpu->gd_npxthread == td) { 457 /* 458 * XXX Note: This is a bit inefficient if the signal 459 * handler uses floating point, extra faults will 460 * occur. 461 */ 462 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 463 npxsave(td->td_savefpu); 464 } else { 465 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 466 } 467 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs)); 468 td->td_flags &= ~TDF_USINGFP; 469 mctx->mc_fpformat = cpu_fxsr ? _MC_FPFMT_XMM : _MC_FPFMT_387; 470 } else { 471 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 472 mctx->mc_fpformat = _MC_FPFMT_NODEV; 473 } 474 } 475 476 /* 477 * Restore the FP state from the mcontext structure. 478 */ 479 void 480 npxpop(mcontext_t *mctx) 481 { 482 thread_t td = curthread; 483 484 switch(mctx->mc_ownedfp) { 485 case _MC_FPOWNED_NONE: 486 /* 487 * If the signal handler used the FP unit but the interrupted 488 * code did not, release the FP unit. Clear TDF_USINGFP will 489 * force the FP unit to reinit so the interrupted code sees 490 * a clean slate. 491 */ 492 if (td->td_flags & TDF_USINGFP) { 493 if (td == mdcpu->gd_npxthread) 494 npxsave(td->td_savefpu); 495 td->td_flags &= ~TDF_USINGFP; 496 } 497 break; 498 case _MC_FPOWNED_FPU: 499 case _MC_FPOWNED_PCB: 500 /* 501 * Clear ownership of the FP unit and restore our saved state. 502 * 503 * NOTE: The signal handler may have set-up some FP state and 504 * enabled the FP unit, so we have to restore no matter what. 505 * 506 * XXX: This is bit inefficient, if the code being returned 507 * to is actively using the FP this results in multiple 508 * kernel faults. 509 * 510 * WARNING: The saved state was exposed to userland and may 511 * have to be sanitized to avoid a GP fault in the kernel. 512 */ 513 if (td == mdcpu->gd_npxthread) 514 npxsave(td->td_savefpu); 515 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 516 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && 517 cpu_fxsr) { 518 krateprintf(&badfprate, 519 "pid %d (%s) signal return from user: " 520 "illegal FP MXCSR %08x\n", 521 td->td_proc->p_pid, 522 td->td_proc->p_comm, 523 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 524 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 525 } 526 td->td_flags |= TDF_USINGFP; 527 break; 528 } 529 } 530 531 /* 532 * On AuthenticAMD processors, the fxrstor instruction does not restore 533 * the x87's stored last instruction pointer, last data pointer, and last 534 * opcode values, except in the rare case in which the exception summary 535 * (ES) bit in the x87 status word is set to 1. 536 * 537 * In order to avoid leaking this information across processes, we clean 538 * these values by performing a dummy load before executing fxrstor(). 539 */ 540 static void 541 fpu_clean_state(void) 542 { 543 u_short status; 544 545 /* 546 * Clear the ES bit in the x87 status word if it is currently 547 * set, in order to avoid causing a fault in the upcoming load. 548 */ 549 fnstsw(&status); 550 if (status & 0x80) 551 fnclex(); 552 553 /* 554 * Load the dummy variable into the x87 stack. This mangles 555 * the x87 stack, but we don't care since we're about to call 556 * fxrstor() anyway. 557 */ 558 __asm __volatile("ffree %st(7); fldz"); 559 } 560 561 void 562 fpurstor(union savefpu *addr, uint64_t mask __unused) 563 { 564 if (cpu_fxsr) { 565 fpu_clean_state(); 566 fxrstor(addr); 567 } else { 568 frstor(addr); 569 } 570 } 571