1 /* 2 * Copyright (c) 2006 The DragonFly Project. All rights reserved. 3 * Copyright (c) 1990 William Jolitz. 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The DragonFly Project 8 * by Matthew Dillon <dillon@backplane.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in 18 * the documentation and/or other materials provided with the 19 * distribution. 20 * 3. Neither the name of The DragonFly Project nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific, prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 28 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/sysctl.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/signalvar.h> 51 #include <sys/thread2.h> 52 53 #include <machine/cputypes.h> 54 #include <machine/frame.h> 55 #include <machine/md_var.h> 56 #include <machine/pcb.h> 57 #include <machine/psl.h> 58 #include <machine/specialreg.h> 59 #include <machine/segments.h> 60 #include <machine/globaldata.h> 61 62 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 63 #define fnclex() __asm("fnclex") 64 #define fninit() __asm("fninit") 65 #define fnop() __asm("fnop") 66 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 67 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 68 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 69 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 70 #ifndef CPU_DISABLE_SSE 71 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 72 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 73 #endif 74 75 typedef u_char bool_t; 76 #ifndef CPU_DISABLE_SSE 77 static void fpu_clean_state(void); 78 #endif 79 80 int cpu_fxsr = 0; 81 82 static struct krate badfprate = { 1 }; 83 84 /*static int npx_attach (device_t dev);*/ 85 static void fpusave (union savefpu *); 86 static void fpurstor (union savefpu *); 87 88 #ifndef CPU_DISABLE_SSE 89 int mmxopt = 1; 90 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0, 91 "MMX/XMM optimized bcopy/copyin/copyout support"); 92 #endif 93 94 static int hw_instruction_sse; 95 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 96 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 97 98 #if 0 99 /* 100 * Attach routine - announce which it is, and wire into system 101 */ 102 int 103 npx_attach(device_t dev) 104 { 105 npxinit(__INITIAL_FPUCW__); 106 return (0); 107 } 108 #endif 109 110 void 111 init_fpu(int supports_sse) 112 { 113 cpu_fxsr = hw_instruction_sse = supports_sse; 114 } 115 116 /* 117 * Initialize the floating point unit. 118 */ 119 void 120 npxinit(u_short control) 121 { 122 static union savefpu dummy __aligned(16); 123 124 /* 125 * fninit has the same h/w bugs as fnsave. Use the detoxified 126 * fnsave to throw away any junk in the fpu. npxsave() initializes 127 * the fpu and sets npxthread = NULL as important side effects. 128 */ 129 npxsave(&dummy); 130 crit_enter(); 131 /*stop_emulating();*/ 132 fldcw(&control); 133 fpusave(curthread->td_savefpu); 134 mdcpu->gd_npxthread = NULL; 135 /*start_emulating();*/ 136 crit_exit(); 137 } 138 139 /* 140 * Free coprocessor (if we have it). 141 */ 142 void 143 npxexit(void) 144 { 145 if (curthread == mdcpu->gd_npxthread) 146 npxsave(curthread->td_savefpu); 147 } 148 149 #if 0 150 /* 151 * The following mechanism is used to ensure that the FPE_... value 152 * that is passed as a trapcode to the signal handler of the user 153 * process does not have more than one bit set. 154 * 155 * Multiple bits may be set if the user process modifies the control 156 * word while a status word bit is already set. While this is a sign 157 * of bad coding, we have no choise than to narrow them down to one 158 * bit, since we must not send a trapcode that is not exactly one of 159 * the FPE_ macros. 160 * 161 * The mechanism has a static table with 127 entries. Each combination 162 * of the 7 FPU status word exception bits directly translates to a 163 * position in this table, where a single FPE_... value is stored. 164 * This FPE_... value stored there is considered the "most important" 165 * of the exception bits and will be sent as the signal code. The 166 * precedence of the bits is based upon Intel Document "Numerical 167 * Applications", Chapter "Special Computational Situations". 168 * 169 * The macro to choose one of these values does these steps: 1) Throw 170 * away status word bits that cannot be masked. 2) Throw away the bits 171 * currently masked in the control word, assuming the user isn't 172 * interested in them anymore. 3) Reinsert status word bit 7 (stack 173 * fault) if it is set, which cannot be masked but must be presered. 174 * 4) Use the remaining bits to point into the trapcode table. 175 * 176 * The 6 maskable bits in order of their preference, as stated in the 177 * above referenced Intel manual: 178 * 1 Invalid operation (FP_X_INV) 179 * 1a Stack underflow 180 * 1b Stack overflow 181 * 1c Operand of unsupported format 182 * 1d SNaN operand. 183 * 2 QNaN operand (not an exception, irrelavant here) 184 * 3 Any other invalid-operation not mentioned above or zero divide 185 * (FP_X_INV, FP_X_DZ) 186 * 4 Denormal operand (FP_X_DNML) 187 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 188 * 6 Inexact result (FP_X_IMP) 189 */ 190 static char fpetable[128] = { 191 0, 192 FPE_FLTINV, /* 1 - INV */ 193 FPE_FLTUND, /* 2 - DNML */ 194 FPE_FLTINV, /* 3 - INV | DNML */ 195 FPE_FLTDIV, /* 4 - DZ */ 196 FPE_FLTINV, /* 5 - INV | DZ */ 197 FPE_FLTDIV, /* 6 - DNML | DZ */ 198 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 199 FPE_FLTOVF, /* 8 - OFL */ 200 FPE_FLTINV, /* 9 - INV | OFL */ 201 FPE_FLTUND, /* A - DNML | OFL */ 202 FPE_FLTINV, /* B - INV | DNML | OFL */ 203 FPE_FLTDIV, /* C - DZ | OFL */ 204 FPE_FLTINV, /* D - INV | DZ | OFL */ 205 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 206 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 207 FPE_FLTUND, /* 10 - UFL */ 208 FPE_FLTINV, /* 11 - INV | UFL */ 209 FPE_FLTUND, /* 12 - DNML | UFL */ 210 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 211 FPE_FLTDIV, /* 14 - DZ | UFL */ 212 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 213 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 214 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 215 FPE_FLTOVF, /* 18 - OFL | UFL */ 216 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 217 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 218 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 219 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 220 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 221 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 222 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 223 FPE_FLTRES, /* 20 - IMP */ 224 FPE_FLTINV, /* 21 - INV | IMP */ 225 FPE_FLTUND, /* 22 - DNML | IMP */ 226 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 227 FPE_FLTDIV, /* 24 - DZ | IMP */ 228 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 229 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 230 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 231 FPE_FLTOVF, /* 28 - OFL | IMP */ 232 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 233 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 234 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 235 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 236 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 237 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 238 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 239 FPE_FLTUND, /* 30 - UFL | IMP */ 240 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 241 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 242 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 243 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 244 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 245 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 246 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 247 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 248 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 249 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 250 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 251 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 252 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 253 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 254 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 255 FPE_FLTSUB, /* 40 - STK */ 256 FPE_FLTSUB, /* 41 - INV | STK */ 257 FPE_FLTUND, /* 42 - DNML | STK */ 258 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 259 FPE_FLTDIV, /* 44 - DZ | STK */ 260 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 261 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 262 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 263 FPE_FLTOVF, /* 48 - OFL | STK */ 264 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 265 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 266 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 267 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 268 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 269 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 270 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 271 FPE_FLTUND, /* 50 - UFL | STK */ 272 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 273 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 274 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 275 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 276 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 277 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 278 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 279 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 280 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 281 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 282 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 283 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 284 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 285 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 286 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 287 FPE_FLTRES, /* 60 - IMP | STK */ 288 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 289 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 290 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 291 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 292 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 293 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 294 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 295 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 296 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 297 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 298 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 299 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 300 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 301 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 302 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 303 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 304 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 305 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 306 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 307 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 308 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 309 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 310 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 311 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 312 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 313 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 314 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 315 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 316 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 317 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 318 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 319 }; 320 #endif 321 322 /* 323 * Implement the device not available (DNA) exception. gd_npxthread had 324 * better be NULL. Restore the current thread's FP state and set gd_npxthread 325 * to curthread. 326 * 327 * Interrupts are enabled and preemption can occur. Enter a critical 328 * section to stabilize the FP state. 329 */ 330 int 331 npxdna(struct trapframe *frame) 332 { 333 thread_t td = curthread; 334 int didinit = 0; 335 336 if (mdcpu->gd_npxthread != NULL) { 337 kprintf("npxdna: npxthread = %p, curthread = %p\n", 338 mdcpu->gd_npxthread, td); 339 panic("npxdna"); 340 } 341 342 /* 343 * Setup the initial saved state if the thread has never before 344 * used the FP unit. This also occurs when a thread pushes a 345 * signal handler and uses FP in the handler. 346 */ 347 if ((curthread->td_flags & TDF_USINGFP) == 0) { 348 curthread->td_flags |= TDF_USINGFP; 349 npxinit(__INITIAL_FPUCW__); 350 didinit = 1; 351 } 352 353 /* 354 * The setting of gd_npxthread and the call to fpurstor() must not 355 * be preempted by an interrupt thread or we will take an npxdna 356 * trap and potentially save our current fpstate (which is garbage) 357 * and then restore the garbage rather then the originally saved 358 * fpstate. 359 */ 360 crit_enter(); 361 /*stop_emulating();*/ 362 /* 363 * Record new context early in case frstor causes an IRQ13. 364 */ 365 mdcpu->gd_npxthread = td; 366 /* 367 * The following frstor may cause an IRQ13 when the state being 368 * restored has a pending error. The error will appear to have been 369 * triggered by the current (npx) user instruction even when that 370 * instruction is a no-wait instruction that should not trigger an 371 * error (e.g., fnclex). On at least one 486 system all of the 372 * no-wait instructions are broken the same as frstor, so our 373 * treatment does not amplify the breakage. On at least one 374 * 386/Cyrix 387 system, fnclex works correctly while frstor and 375 * fnsave are broken, so our treatment breaks fnclex if it is the 376 * first FPU instruction after a context switch. 377 */ 378 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && cpu_fxsr) { 379 krateprintf(&badfprate, 380 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n", 381 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit); 382 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 383 lwpsignal(curproc, curthread->td_lwp, SIGFPE); 384 } 385 fpurstor(curthread->td_savefpu); 386 crit_exit(); 387 388 return (1); 389 } 390 391 /* 392 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 393 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 394 * any IRQ13 to be handled immediately, and then ignore it. This routine is 395 * often called at splhigh so it must not use many system services. In 396 * particular, it's much easier to install a special handler than to 397 * guarantee that it's safe to use npxintr() and its supporting code. 398 * 399 * WARNING! This call is made during a switch and the MP lock will be 400 * setup for the new target thread rather then the current thread, so we 401 * cannot do anything here that depends on the *_mplock() functions as 402 * we may trip over their assertions. 403 * 404 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 405 * kernel will always assume that the FP state is 'safe' (will not cause 406 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 407 * setup a custom save area before actually using the FP unit, but it will 408 * not bother calling fninit. This greatly improves kernel performance when 409 * it wishes to use the FP unit. 410 */ 411 void 412 npxsave(union savefpu *addr) 413 { 414 crit_enter(); 415 /*stop_emulating();*/ 416 fpusave(addr); 417 mdcpu->gd_npxthread = NULL; 418 fninit(); 419 /*start_emulating();*/ 420 crit_exit(); 421 } 422 423 static void 424 fpusave(union savefpu *addr) 425 { 426 if (cpu_fxsr) 427 fxsave(addr); 428 else 429 fnsave(addr); 430 } 431 432 /* 433 * Save the FP state to the mcontext structure. 434 * 435 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 436 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 437 */ 438 void 439 npxpush(mcontext_t *mctx) 440 { 441 thread_t td = curthread; 442 443 if (td->td_flags & TDF_USINGFP) { 444 if (mdcpu->gd_npxthread == td) { 445 /* 446 * XXX Note: This is a bit inefficient if the signal 447 * handler uses floating point, extra faults will 448 * occur. 449 */ 450 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 451 npxsave(td->td_savefpu); 452 } else { 453 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 454 } 455 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs)); 456 td->td_flags &= ~TDF_USINGFP; 457 mctx->mc_fpformat = 458 #ifndef CPU_DISABLE_SSE 459 (cpu_fxsr) ? _MC_FPFMT_XMM : 460 #endif 461 _MC_FPFMT_387; 462 } else { 463 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 464 mctx->mc_fpformat = _MC_FPFMT_NODEV; 465 } 466 } 467 468 /* 469 * Restore the FP state from the mcontext structure. 470 */ 471 void 472 npxpop(mcontext_t *mctx) 473 { 474 thread_t td = curthread; 475 476 switch(mctx->mc_ownedfp) { 477 case _MC_FPOWNED_NONE: 478 /* 479 * If the signal handler used the FP unit but the interrupted 480 * code did not, release the FP unit. Clear TDF_USINGFP will 481 * force the FP unit to reinit so the interrupted code sees 482 * a clean slate. 483 */ 484 if (td->td_flags & TDF_USINGFP) { 485 if (td == mdcpu->gd_npxthread) 486 npxsave(td->td_savefpu); 487 td->td_flags &= ~TDF_USINGFP; 488 } 489 break; 490 case _MC_FPOWNED_FPU: 491 case _MC_FPOWNED_PCB: 492 /* 493 * Clear ownership of the FP unit and restore our saved state. 494 * 495 * NOTE: The signal handler may have set-up some FP state and 496 * enabled the FP unit, so we have to restore no matter what. 497 * 498 * XXX: This is bit inefficient, if the code being returned 499 * to is actively using the FP this results in multiple 500 * kernel faults. 501 * 502 * WARNING: The saved state was exposed to userland and may 503 * have to be sanitized to avoid a GP fault in the kernel. 504 */ 505 if (td == mdcpu->gd_npxthread) 506 npxsave(td->td_savefpu); 507 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 508 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && 509 cpu_fxsr) { 510 krateprintf(&badfprate, 511 "pid %d (%s) signal return from user: " 512 "illegal FP MXCSR %08x\n", 513 td->td_proc->p_pid, 514 td->td_proc->p_comm, 515 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 516 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 517 } 518 td->td_flags |= TDF_USINGFP; 519 break; 520 } 521 } 522 523 524 #ifndef CPU_DISABLE_SSE 525 /* 526 * On AuthenticAMD processors, the fxrstor instruction does not restore 527 * the x87's stored last instruction pointer, last data pointer, and last 528 * opcode values, except in the rare case in which the exception summary 529 * (ES) bit in the x87 status word is set to 1. 530 * 531 * In order to avoid leaking this information across processes, we clean 532 * these values by performing a dummy load before executing fxrstor(). 533 */ 534 static double dummy_variable = 0.0; 535 static void 536 fpu_clean_state(void) 537 { 538 u_short status; 539 540 /* 541 * Clear the ES bit in the x87 status word if it is currently 542 * set, in order to avoid causing a fault in the upcoming load. 543 */ 544 fnstsw(&status); 545 if (status & 0x80) 546 fnclex(); 547 548 /* 549 * Load the dummy variable into the x87 stack. This mangles 550 * the x87 stack, but we don't care since we're about to call 551 * fxrstor() anyway. 552 */ 553 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable)); 554 } 555 #endif /* CPU_DISABLE_SSE */ 556 557 static void 558 fpurstor(union savefpu *addr) 559 { 560 #ifndef CPU_DISABLE_SSE 561 if (cpu_fxsr) { 562 fpu_clean_state(); 563 fxrstor(addr); 564 } else { 565 frstor(addr); 566 } 567 #else 568 frstor(addr); 569 #endif 570 } 571