1 /* 2 * Copyright (c) 2006 The DragonFly Project. All rights reserved. 3 * Copyright (c) 1990 William Jolitz. 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The DragonFly Project 8 * by Matthew Dillon <dillon@backplane.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in 18 * the documentation and/or other materials provided with the 19 * distribution. 20 * 3. Neither the name of The DragonFly Project nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific, prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 28 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 38 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/sysctl.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/signalvar.h> 51 #include <sys/thread2.h> 52 53 #include <machine/cputypes.h> 54 #include <machine/frame.h> 55 #include <machine/md_var.h> 56 #include <machine/pcb.h> 57 #include <machine/psl.h> 58 #include <machine/specialreg.h> 59 #include <machine/segments.h> 60 #include <machine/globaldata.h> 61 62 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 63 #define fnclex() __asm("fnclex") 64 #define fninit() __asm("fninit") 65 #define fnop() __asm("fnop") 66 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 67 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 68 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 69 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 70 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 71 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 72 73 typedef u_char bool_t; 74 static void fpu_clean_state(void); 75 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 76 77 int cpu_fxsr = 0; 78 79 static struct krate badfprate = { 1 }; 80 81 /*static int npx_attach (device_t dev);*/ 82 static void fpusave (union savefpu *); 83 static void fpurstor (union savefpu *); 84 85 uint32_t npx_mxcsr_mask = 0xFFBF; 86 87 int mmxopt = 1; 88 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0, 89 "MMX/XMM optimized bcopy/copyin/copyout support"); 90 91 static int hw_instruction_sse; 92 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 93 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 94 95 #if 0 96 /* 97 * Attach routine - announce which it is, and wire into system 98 */ 99 int 100 npx_attach(device_t dev) 101 { 102 npxinit(); 103 return (0); 104 } 105 #endif 106 107 void 108 init_fpu(int supports_sse) 109 { 110 cpu_fxsr = hw_instruction_sse = supports_sse; 111 npxprobemask(); 112 } 113 114 /* 115 * Probe the npx_mxcsr_mask 116 */ 117 void npxprobemask(void) 118 { 119 /*64-Byte alignment required for xsave*/ 120 static union savefpu dummy __aligned(64); 121 122 crit_enter(); 123 /*stop_emulating();*/ 124 fxsave(&dummy); 125 npx_mxcsr_mask = ((uint32_t *)&dummy)[7]; 126 /*stop_emulating();*/ 127 crit_exit(); 128 } 129 130 131 /* 132 * Initialize the floating point unit. 133 */ 134 void npxinit(void) 135 { 136 static union savefpu dummy __aligned(16); 137 u_short control = __INITIAL_FPUCW__; 138 u_int mxcsr = __INITIAL_MXCSR__; 139 140 /* 141 * fninit has the same h/w bugs as fnsave. Use the detoxified 142 * fnsave to throw away any junk in the fpu. npxsave() initializes 143 * the fpu and sets npxthread = NULL as important side effects. 144 */ 145 npxsave(&dummy); 146 crit_enter(); 147 /*stop_emulating();*/ 148 fldcw(&control); 149 ldmxcsr(mxcsr); 150 fpusave(curthread->td_savefpu); 151 mdcpu->gd_npxthread = NULL; 152 /*start_emulating();*/ 153 crit_exit(); 154 } 155 156 /* 157 * Free coprocessor (if we have it). 158 */ 159 void 160 npxexit(void) 161 { 162 if (curthread == mdcpu->gd_npxthread) 163 npxsave(curthread->td_savefpu); 164 } 165 166 #if 0 167 /* 168 * The following mechanism is used to ensure that the FPE_... value 169 * that is passed as a trapcode to the signal handler of the user 170 * process does not have more than one bit set. 171 * 172 * Multiple bits may be set if the user process modifies the control 173 * word while a status word bit is already set. While this is a sign 174 * of bad coding, we have no choise than to narrow them down to one 175 * bit, since we must not send a trapcode that is not exactly one of 176 * the FPE_ macros. 177 * 178 * The mechanism has a static table with 127 entries. Each combination 179 * of the 7 FPU status word exception bits directly translates to a 180 * position in this table, where a single FPE_... value is stored. 181 * This FPE_... value stored there is considered the "most important" 182 * of the exception bits and will be sent as the signal code. The 183 * precedence of the bits is based upon Intel Document "Numerical 184 * Applications", Chapter "Special Computational Situations". 185 * 186 * The macro to choose one of these values does these steps: 1) Throw 187 * away status word bits that cannot be masked. 2) Throw away the bits 188 * currently masked in the control word, assuming the user isn't 189 * interested in them anymore. 3) Reinsert status word bit 7 (stack 190 * fault) if it is set, which cannot be masked but must be presered. 191 * 4) Use the remaining bits to point into the trapcode table. 192 * 193 * The 6 maskable bits in order of their preference, as stated in the 194 * above referenced Intel manual: 195 * 1 Invalid operation (FP_X_INV) 196 * 1a Stack underflow 197 * 1b Stack overflow 198 * 1c Operand of unsupported format 199 * 1d SNaN operand. 200 * 2 QNaN operand (not an exception, irrelavant here) 201 * 3 Any other invalid-operation not mentioned above or zero divide 202 * (FP_X_INV, FP_X_DZ) 203 * 4 Denormal operand (FP_X_DNML) 204 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 205 * 6 Inexact result (FP_X_IMP) 206 */ 207 static char fpetable[128] = { 208 0, 209 FPE_FLTINV, /* 1 - INV */ 210 FPE_FLTUND, /* 2 - DNML */ 211 FPE_FLTINV, /* 3 - INV | DNML */ 212 FPE_FLTDIV, /* 4 - DZ */ 213 FPE_FLTINV, /* 5 - INV | DZ */ 214 FPE_FLTDIV, /* 6 - DNML | DZ */ 215 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 216 FPE_FLTOVF, /* 8 - OFL */ 217 FPE_FLTINV, /* 9 - INV | OFL */ 218 FPE_FLTUND, /* A - DNML | OFL */ 219 FPE_FLTINV, /* B - INV | DNML | OFL */ 220 FPE_FLTDIV, /* C - DZ | OFL */ 221 FPE_FLTINV, /* D - INV | DZ | OFL */ 222 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 223 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 224 FPE_FLTUND, /* 10 - UFL */ 225 FPE_FLTINV, /* 11 - INV | UFL */ 226 FPE_FLTUND, /* 12 - DNML | UFL */ 227 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 228 FPE_FLTDIV, /* 14 - DZ | UFL */ 229 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 230 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 231 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 232 FPE_FLTOVF, /* 18 - OFL | UFL */ 233 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 234 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 235 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 236 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 237 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 238 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 239 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 240 FPE_FLTRES, /* 20 - IMP */ 241 FPE_FLTINV, /* 21 - INV | IMP */ 242 FPE_FLTUND, /* 22 - DNML | IMP */ 243 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 244 FPE_FLTDIV, /* 24 - DZ | IMP */ 245 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 246 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 247 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 248 FPE_FLTOVF, /* 28 - OFL | IMP */ 249 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 250 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 251 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 252 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 253 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 254 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 255 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 256 FPE_FLTUND, /* 30 - UFL | IMP */ 257 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 258 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 259 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 260 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 261 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 262 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 263 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 264 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 265 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 266 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 267 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 268 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 269 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 270 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 271 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 272 FPE_FLTSUB, /* 40 - STK */ 273 FPE_FLTSUB, /* 41 - INV | STK */ 274 FPE_FLTUND, /* 42 - DNML | STK */ 275 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 276 FPE_FLTDIV, /* 44 - DZ | STK */ 277 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 278 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 279 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 280 FPE_FLTOVF, /* 48 - OFL | STK */ 281 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 282 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 283 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 284 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 285 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 286 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 287 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 288 FPE_FLTUND, /* 50 - UFL | STK */ 289 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 290 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 291 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 292 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 293 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 294 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 295 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 296 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 297 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 298 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 299 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 300 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 301 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 302 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 303 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 304 FPE_FLTRES, /* 60 - IMP | STK */ 305 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 306 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 307 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 308 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 309 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 310 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 311 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 312 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 313 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 314 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 315 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 316 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 317 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 318 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 319 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 320 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 321 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 322 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 323 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 324 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 325 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 326 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 327 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 328 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 329 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 330 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 331 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 332 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 333 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 334 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 335 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 336 }; 337 #endif 338 339 /* 340 * Implement the device not available (DNA) exception. gd_npxthread had 341 * better be NULL. Restore the current thread's FP state and set gd_npxthread 342 * to curthread. 343 * 344 * Interrupts are enabled and preemption can occur. Enter a critical 345 * section to stabilize the FP state. 346 */ 347 int 348 npxdna(struct trapframe *frame) 349 { 350 thread_t td = curthread; 351 int didinit = 0; 352 353 if (mdcpu->gd_npxthread != NULL) { 354 kprintf("npxdna: npxthread = %p, curthread = %p\n", 355 mdcpu->gd_npxthread, td); 356 panic("npxdna"); 357 } 358 359 /* 360 * Setup the initial saved state if the thread has never before 361 * used the FP unit. This also occurs when a thread pushes a 362 * signal handler and uses FP in the handler. 363 */ 364 if ((curthread->td_flags & TDF_USINGFP) == 0) { 365 curthread->td_flags |= TDF_USINGFP; 366 npxinit(); 367 didinit = 1; 368 } 369 370 /* 371 * The setting of gd_npxthread and the call to fpurstor() must not 372 * be preempted by an interrupt thread or we will take an npxdna 373 * trap and potentially save our current fpstate (which is garbage) 374 * and then restore the garbage rather then the originally saved 375 * fpstate. 376 */ 377 crit_enter(); 378 /*stop_emulating();*/ 379 /* 380 * Record new context early in case frstor causes an IRQ13. 381 */ 382 mdcpu->gd_npxthread = td; 383 /* 384 * The following frstor may cause an IRQ13 when the state being 385 * restored has a pending error. The error will appear to have been 386 * triggered by the current (npx) user instruction even when that 387 * instruction is a no-wait instruction that should not trigger an 388 * error (e.g., fnclex). On at least one 486 system all of the 389 * no-wait instructions are broken the same as frstor, so our 390 * treatment does not amplify the breakage. On at least one 391 * 386/Cyrix 387 system, fnclex works correctly while frstor and 392 * fnsave are broken, so our treatment breaks fnclex if it is the 393 * first FPU instruction after a context switch. 394 */ 395 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && cpu_fxsr) { 396 krateprintf(&badfprate, 397 "FXRSTR: illegal FP MXCSR %08x didinit = %d\n", 398 td->td_savefpu->sv_xmm.sv_env.en_mxcsr, didinit); 399 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 400 lwpsignal(curproc, curthread->td_lwp, SIGFPE); 401 } 402 fpurstor(curthread->td_savefpu); 403 crit_exit(); 404 405 return (1); 406 } 407 408 /* 409 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error 410 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 411 * any IRQ13 to be handled immediately, and then ignore it. This routine is 412 * often called at splhigh so it must not use many system services. In 413 * particular, it's much easier to install a special handler than to 414 * guarantee that it's safe to use npxintr() and its supporting code. 415 * 416 * WARNING! This call is made during a switch and the MP lock will be 417 * setup for the new target thread rather then the current thread, so we 418 * cannot do anything here that depends on the *_mplock() functions as 419 * we may trip over their assertions. 420 * 421 * WARNING! When using fxsave we MUST fninit after saving the FP state. The 422 * kernel will always assume that the FP state is 'safe' (will not cause 423 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still 424 * setup a custom save area before actually using the FP unit, but it will 425 * not bother calling fninit. This greatly improves kernel performance when 426 * it wishes to use the FP unit. 427 */ 428 void 429 npxsave(union savefpu *addr) 430 { 431 crit_enter(); 432 /*stop_emulating();*/ 433 fpusave(addr); 434 mdcpu->gd_npxthread = NULL; 435 fninit(); 436 /*start_emulating();*/ 437 crit_exit(); 438 } 439 440 static void 441 fpusave(union savefpu *addr) 442 { 443 if (cpu_fxsr) 444 fxsave(addr); 445 else 446 fnsave(addr); 447 } 448 449 /* 450 * Save the FP state to the mcontext structure. 451 * 452 * WARNING: If you want to try to npxsave() directly to mctx->mc_fpregs, 453 * then it MUST be 16-byte aligned. Currently this is not guarenteed. 454 */ 455 void 456 npxpush(mcontext_t *mctx) 457 { 458 thread_t td = curthread; 459 460 if (td->td_flags & TDF_USINGFP) { 461 if (mdcpu->gd_npxthread == td) { 462 /* 463 * XXX Note: This is a bit inefficient if the signal 464 * handler uses floating point, extra faults will 465 * occur. 466 */ 467 mctx->mc_ownedfp = _MC_FPOWNED_FPU; 468 npxsave(td->td_savefpu); 469 } else { 470 mctx->mc_ownedfp = _MC_FPOWNED_PCB; 471 } 472 bcopy(td->td_savefpu, mctx->mc_fpregs, sizeof(mctx->mc_fpregs)); 473 td->td_flags &= ~TDF_USINGFP; 474 mctx->mc_fpformat = cpu_fxsr ? _MC_FPFMT_XMM : _MC_FPFMT_387; 475 } else { 476 mctx->mc_ownedfp = _MC_FPOWNED_NONE; 477 mctx->mc_fpformat = _MC_FPFMT_NODEV; 478 } 479 } 480 481 /* 482 * Restore the FP state from the mcontext structure. 483 */ 484 void 485 npxpop(mcontext_t *mctx) 486 { 487 thread_t td = curthread; 488 489 switch(mctx->mc_ownedfp) { 490 case _MC_FPOWNED_NONE: 491 /* 492 * If the signal handler used the FP unit but the interrupted 493 * code did not, release the FP unit. Clear TDF_USINGFP will 494 * force the FP unit to reinit so the interrupted code sees 495 * a clean slate. 496 */ 497 if (td->td_flags & TDF_USINGFP) { 498 if (td == mdcpu->gd_npxthread) 499 npxsave(td->td_savefpu); 500 td->td_flags &= ~TDF_USINGFP; 501 } 502 break; 503 case _MC_FPOWNED_FPU: 504 case _MC_FPOWNED_PCB: 505 /* 506 * Clear ownership of the FP unit and restore our saved state. 507 * 508 * NOTE: The signal handler may have set-up some FP state and 509 * enabled the FP unit, so we have to restore no matter what. 510 * 511 * XXX: This is bit inefficient, if the code being returned 512 * to is actively using the FP this results in multiple 513 * kernel faults. 514 * 515 * WARNING: The saved state was exposed to userland and may 516 * have to be sanitized to avoid a GP fault in the kernel. 517 */ 518 if (td == mdcpu->gd_npxthread) 519 npxsave(td->td_savefpu); 520 bcopy(mctx->mc_fpregs, td->td_savefpu, sizeof(*td->td_savefpu)); 521 if ((td->td_savefpu->sv_xmm.sv_env.en_mxcsr & ~0xFFBF) && 522 cpu_fxsr) { 523 krateprintf(&badfprate, 524 "pid %d (%s) signal return from user: " 525 "illegal FP MXCSR %08x\n", 526 td->td_proc->p_pid, 527 td->td_proc->p_comm, 528 td->td_savefpu->sv_xmm.sv_env.en_mxcsr); 529 td->td_savefpu->sv_xmm.sv_env.en_mxcsr &= 0xFFBF; 530 } 531 td->td_flags |= TDF_USINGFP; 532 break; 533 } 534 } 535 536 /* 537 * On AuthenticAMD processors, the fxrstor instruction does not restore 538 * the x87's stored last instruction pointer, last data pointer, and last 539 * opcode values, except in the rare case in which the exception summary 540 * (ES) bit in the x87 status word is set to 1. 541 * 542 * In order to avoid leaking this information across processes, we clean 543 * these values by performing a dummy load before executing fxrstor(). 544 */ 545 static double dummy_variable = 0.0; 546 static void 547 fpu_clean_state(void) 548 { 549 u_short status; 550 551 /* 552 * Clear the ES bit in the x87 status word if it is currently 553 * set, in order to avoid causing a fault in the upcoming load. 554 */ 555 fnstsw(&status); 556 if (status & 0x80) 557 fnclex(); 558 559 /* 560 * Load the dummy variable into the x87 stack. This mangles 561 * the x87 stack, but we don't care since we're about to call 562 * fxrstor() anyway. 563 */ 564 __asm __volatile("ffree %%st(7); fldl %0" : : "m" (dummy_variable)); 565 } 566 567 static void 568 fpurstor(union savefpu *addr) 569 { 570 if (cpu_fxsr) { 571 fpu_clean_state(); 572 fxrstor(addr); 573 } else { 574 frstor(addr); 575 } 576 } 577