1/* 2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved. 3 * Copyright (c) 2008 Jordan Gordeev. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Matthew Dillon <dillon@backplane.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * Copyright (c) 1990 The Regents of the University of California. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * William Jolitz. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. Neither the name of the University nor the names of its contributors 50 * may be used to endorse or promote products derived from this software 51 * without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $ 66 */ 67 68//#include "use_npx.h" 69 70#include <sys/rtprio.h> 71 72#include <machine/asmacros.h> 73#include <machine/segments.h> 74 75#include <machine/pmap.h> 76#include <machine/lock.h> 77 78#define CHECKNZ(expr, scratch_reg) \ 79 movq expr, scratch_reg; testq scratch_reg, scratch_reg; jnz 7f; int $3; 7: 80 81#include "assym.s" 82 83#define MPLOCKED lock ; 84 85 .data 86 87 .globl panic 88 .globl lwkt_switch_return 89 90#if defined(SWTCH_OPTIM_STATS) 91 .globl swtch_optim_stats, tlb_flush_count 92swtch_optim_stats: .long 0 /* number of _swtch_optims */ 93tlb_flush_count: .long 0 94#endif 95 96 .text 97 98 99/* 100 * cpu_heavy_switch(struct thread *next_thread) 101 * 102 * Switch from the current thread to a new thread. This entry 103 * is normally called via the thread->td_switch function, and will 104 * only be called when the current thread is a heavy weight process. 105 * 106 * Some instructions have been reordered to reduce pipeline stalls. 107 * 108 * YYY disable interrupts once giant is removed. 109 */ 110ENTRY(cpu_heavy_switch) 111 /* 112 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15). 113 */ 114 movq PCPU(curthread),%rcx 115 /* On top of the stack is the return adress. */ 116 movq (%rsp),%rax /* (reorder optimization) */ 117 movq TD_PCB(%rcx),%rdx /* RDX = PCB */ 118 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */ 119 movq %rbx,PCB_RBX(%rdx) 120 movq %rsp,PCB_RSP(%rdx) 121 movq %rbp,PCB_RBP(%rdx) 122 movq %r12,PCB_R12(%rdx) 123 movq %r13,PCB_R13(%rdx) 124 movq %r14,PCB_R14(%rdx) 125 movq %r15,PCB_R15(%rdx) 126 127 /* 128 * Clear the cpu bit in the pmap active mask. The restore 129 * function will set the bit in the pmap active mask. 130 * 131 * Special case: when switching between threads sharing the 132 * same vmspace if we avoid clearing the bit we do not have 133 * to reload %cr3 (if we clear the bit we could race page 134 * table ops done by other threads and would have to reload 135 * %cr3, because those ops will not know to IPI us). 136 */ 137 movq %rcx,%rbx /* RBX = oldthread */ 138 movq TD_LWP(%rcx),%rcx /* RCX = oldlwp */ 139 movq TD_LWP(%rdi),%r13 /* R13 = newlwp */ 140 movq LWP_VMSPACE(%rcx), %rcx /* RCX = oldvmspace */ 141 testq %r13,%r13 /* might not be a heavy */ 142 jz 1f 143 cmpq LWP_VMSPACE(%r13),%rcx /* same vmspace? */ 144 je 2f 1451: 146 movq PCPU(other_cpus)+0, %rax 147 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+0(%rcx) 148 movq PCPU(other_cpus)+8, %rax 149 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+8(%rcx) 150 movq PCPU(other_cpus)+16, %rax 151 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+16(%rcx) 152 movq PCPU(other_cpus)+24, %rax 153 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+24(%rcx) 1542: 155 156 /* 157 * Push the LWKT switch restore function, which resumes a heavy 158 * weight process. Note that the LWKT switcher is based on 159 * TD_SP, while the heavy weight process switcher is based on 160 * PCB_RSP. TD_SP is usually two ints pushed relative to 161 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore. 162 */ 163 pushfq 164 movq $cpu_heavy_restore, %rax 165 pushq %rax 166 movq %rsp,TD_SP(%rbx) 167 168 /* 169 * Save debug regs if necessary 170 */ 171 movq PCB_FLAGS(%rdx),%rax 172 andq $PCB_DBREGS,%rax 173 jz 1f /* no, skip over */ 174 movq %dr7,%rax /* yes, do the save */ 175 movq %rax,PCB_DR7(%rdx) 176 /* JG correct value? */ 177 andq $0x0000fc00, %rax /* disable all watchpoints */ 178 movq %rax,%dr7 179 movq %dr6,%rax 180 movq %rax,PCB_DR6(%rdx) 181 movq %dr3,%rax 182 movq %rax,PCB_DR3(%rdx) 183 movq %dr2,%rax 184 movq %rax,PCB_DR2(%rdx) 185 movq %dr1,%rax 186 movq %rax,PCB_DR1(%rdx) 187 movq %dr0,%rax 188 movq %rax,PCB_DR0(%rdx) 1891: 190 191#if 1 192 /* 193 * Save the FP state if we have used the FP. Note that calling 194 * npxsave will NULL out PCPU(npxthread). 195 */ 196 cmpq %rbx,PCPU(npxthread) 197 jne 1f 198 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 199 movq TD_SAVEFPU(%rbx),%rdi 200 call npxsave /* do it in a big C function */ 201 movq %r12,%rdi /* restore %rdi */ 2021: 203#endif 204 205 /* 206 * Switch to the next thread, which was passed as an argument 207 * to cpu_heavy_switch(). The argument is in %rdi. 208 * Set the current thread, load the stack pointer, 209 * and 'ret' into the switch-restore function. 210 * 211 * The switch restore function expects the new thread to be in %rax 212 * and the old one to be in %rbx. 213 * 214 * There is a one-instruction window where curthread is the new 215 * thread but %rsp still points to the old thread's stack, but 216 * we are protected by a critical section so it is ok. 217 */ 218 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */ 219 movq %rax,PCPU(curthread) 220 movq TD_SP(%rax),%rsp 221 CHECKNZ((%rsp), %r9) 222 ret 223END(cpu_heavy_switch) 224 225/* 226 * cpu_exit_switch(struct thread *next) 227 * 228 * The switch function is changed to this when a thread is going away 229 * for good. We have to ensure that the MMU state is not cached, and 230 * we don't bother saving the existing thread state before switching. 231 * 232 * At this point we are in a critical section and this cpu owns the 233 * thread's token, which serves as an interlock until the switchout is 234 * complete. 235 */ 236ENTRY(cpu_exit_switch) 237 /* 238 * Get us out of the vmspace 239 */ 240#if 0 241 movq KPML4phys,%rcx 242 movq %cr3,%rax 243 cmpq %rcx,%rax 244 je 1f 245 /* JG no increment of statistics counters? see cpu_heavy_restore */ 246 movq %rcx,%cr3 2471: 248#endif 249 movq PCPU(curthread),%rbx 250 251 /* 252 * If this is a process/lwp, deactivate the pmap after we've 253 * switched it out. 254 */ 255 movq TD_LWP(%rbx),%rcx 256 testq %rcx,%rcx 257 jz 2f 258 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 259 movq PCPU(other_cpus)+0, %rax 260 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+0(%rcx) 261 movq PCPU(other_cpus)+8, %rax 262 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+8(%rcx) 263 movq PCPU(other_cpus)+16, %rax 264 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+16(%rcx) 265 movq PCPU(other_cpus)+24, %rax 266 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+24(%rcx) 2672: 268 /* 269 * Switch to the next thread. RET into the restore function, which 270 * expects the new thread in RAX and the old in RBX. 271 * 272 * There is a one-instruction window where curthread is the new 273 * thread but %rsp still points to the old thread's stack, but 274 * we are protected by a critical section so it is ok. 275 */ 276 movq %rdi,%rax 277 movq %rax,PCPU(curthread) 278 movq TD_SP(%rax),%rsp 279 CHECKNZ((%rsp), %r9) 280 ret 281END(cpu_exit_switch) 282 283/* 284 * cpu_heavy_restore() (current thread in %rax on entry, %rbx is old thread) 285 * 286 * Restore the thread after an LWKT switch. This entry is normally 287 * called via the LWKT switch restore function, which was pulled 288 * off the thread stack and jumped to. 289 * 290 * This entry is only called if the thread was previously saved 291 * using cpu_heavy_switch() (the heavy weight process thread switcher), 292 * or when a new process is initially scheduled. 293 * 294 * NOTE: The lwp may be in any state, not necessarily LSRUN, because 295 * a preemption switch may interrupt the process and then return via 296 * cpu_heavy_restore. 297 * 298 * YYY theoretically we do not have to restore everything here, a lot 299 * of this junk can wait until we return to usermode. But for now 300 * we restore everything. 301 * 302 * YYY the PCB crap is really crap, it makes startup a bitch because 303 * we can't switch away. 304 * 305 * YYY note: spl check is done in mi_switch when it splx()'s. 306 */ 307 308ENTRY(cpu_heavy_restore) 309 popfq 310 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 311 312#if defined(SWTCH_OPTIM_STATS) 313 incl _swtch_optim_stats 314#endif 315 /* 316 * Tell the pmap that our cpu is using the VMSPACE now. We cannot 317 * safely test/reload %cr3 until after we have set the bit in the 318 * pmap (remember, we do not hold the MP lock in the switch code). 319 */ 320 movq TD_LWP(%rax),%rcx 321 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 322 323 movq PCPU(cpumask)+0, %rsi 324 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+0(%rcx) 325 movq PCPU(cpumask)+8, %rsi 326 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+8(%rcx) 327 movq PCPU(cpumask)+16, %rsi 328 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+16(%rcx) 329 movq PCPU(cpumask)+24, %rsi 330 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+24(%rcx) 331 332 movl VM_PMAP+PM_ACTIVE_LOCK(%rcx),%esi 333 testl $CPULOCK_EXCL,%esi 334 jz 1f 335 336 movq %rax,%r12 /* save newthread ptr */ 337 movq %rcx,%rdi /* (found to be set) */ 338 call pmap_interlock_wait /* pmap_interlock_wait(%rdi:vm) */ 339 movq %r12,%rax 340 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 3411: 342 /* 343 * Restore the MMU address space. If it is the same as the last 344 * thread we don't have to invalidate the tlb (i.e. reload cr3). 345 * YYY which naturally also means that the PM_ACTIVE bit had better 346 * already have been set before we set it above, check? YYY 347 */ 348#if 0 349 movq %cr3,%rsi 350 movq PCB_CR3(%rdx),%rcx 351 cmpq %rsi,%rcx 352 je 4f 353#if defined(SWTCH_OPTIM_STATS) 354 decl _swtch_optim_stats 355 incl _tlb_flush_count 356#endif 357 movq %rcx,%cr3 3584: 359#endif 360 /* 361 * NOTE: %rbx is the previous thread and %rax is the new thread. 362 * %rbx is retained throughout so we can return it. 363 * 364 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 365 */ 366 367#if 0 368 /* 369 * Deal with the PCB extension, restore the private tss 370 */ 371 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */ 372 movq $1,%rcx /* maybe mark use of a private tss */ 373 testq %rdi,%rdi 374#if 0 /* JG */ 375 jnz 2f 376#endif 377 378 /* JG 379 * Going back to the common_tss. We may need to update TSS_ESP0 380 * which sets the top of the supervisor stack when entering from 381 * usermode. The PCB is at the top of the stack but we need another 382 * 16 bytes to take vm86 into account. 383 */ 384 leaq -16(%rdx),%rcx 385 movq %rcx, PCPU(common_tss) + TSS_RSP0 386 movq %rcx, PCPU(rsp0) 387 388#if 0 /* JG */ 389 cmpl $0,PCPU(private_tss) /* don't have to reload if */ 390 je 3f /* already using the common TSS */ 391 392 /* JG? */ 393 subq %rcx,%rcx /* unmark use of private tss */ 394 395 /* 396 * Get the address of the common TSS descriptor for the ltr. 397 * There is no way to get the address of a segment-accessed variable 398 * so we store a self-referential pointer at the base of the per-cpu 399 * data area and add the appropriate offset. 400 */ 401 /* JG movl? */ 402 movq $gd_common_tssd, %rdi 403 /* JG name for "%gs:0"? */ 404 addq %gs:0, %rdi 405 406 /* 407 * Move the correct TSS descriptor into the GDT slot, then reload 408 * ltr. 409 */ 4102: 411 /* JG */ 412 movl %rcx,PCPU(private_tss) /* mark/unmark private tss */ 413 movq PCPU(tss_gdt), %rcx /* entry in GDT */ 414 movq 0(%rdi), %rax 415 movq %rax, 0(%rcx) 416 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */ 417 ltr %si 418#endif 419 4203: 421#endif 422#if 0 423 /* 424 * Restore the user %gs and %fs 425 */ 426 movq PCB_FSBASE(%rdx),%r9 427 cmpq PCPU(user_fs),%r9 428 je 4f 429 movq %rdx,%r10 430 movq %r9,PCPU(user_fs) 431 movl $MSR_FSBASE,%ecx 432 movl PCB_FSBASE(%r10),%eax 433 movl PCB_FSBASE+4(%r10),%edx 434 wrmsr 435 movq %r10,%rdx 4364: 437 movq PCB_GSBASE(%rdx),%r9 438 cmpq PCPU(user_gs),%r9 439 je 5f 440 movq %rdx,%r10 441 movq %r9,PCPU(user_gs) 442 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */ 443 movl PCB_GSBASE(%r10),%eax 444 movl PCB_GSBASE+4(%r10),%edx 445 wrmsr 446 movq %r10,%rdx 4475: 448#endif 449 450 /* 451 * Restore general registers. %rbx is restored later. 452 */ 453 movq PCB_RSP(%rdx), %rsp 454 movq PCB_RBP(%rdx), %rbp 455 movq PCB_R12(%rdx), %r12 456 movq PCB_R13(%rdx), %r13 457 movq PCB_R14(%rdx), %r14 458 movq PCB_R15(%rdx), %r15 459 movq PCB_RIP(%rdx), %rax 460 movq %rax, (%rsp) 461 462#if 0 463 /* 464 * Restore the user LDT if we have one 465 */ 466 cmpl $0, PCB_USERLDT(%edx) 467 jnz 1f 468 movl _default_ldt,%eax 469 cmpl PCPU(currentldt),%eax 470 je 2f 471 lldt _default_ldt 472 movl %eax,PCPU(currentldt) 473 jmp 2f 4741: pushl %edx 475 call set_user_ldt 476 popl %edx 4772: 478#endif 479#if 0 480 /* 481 * Restore the user TLS if we have one 482 */ 483 pushl %edx 484 call set_user_TLS 485 popl %edx 486#endif 487 488 /* 489 * Restore the DEBUG register state if necessary. 490 */ 491 movq PCB_FLAGS(%rdx),%rax 492 andq $PCB_DBREGS,%rax 493 jz 1f /* no, skip over */ 494 movq PCB_DR6(%rdx),%rax /* yes, do the restore */ 495 movq %rax,%dr6 496 movq PCB_DR3(%rdx),%rax 497 movq %rax,%dr3 498 movq PCB_DR2(%rdx),%rax 499 movq %rax,%dr2 500 movq PCB_DR1(%rdx),%rax 501 movq %rax,%dr1 502 movq PCB_DR0(%rdx),%rax 503 movq %rax,%dr0 504 movq %dr7,%rax /* load dr7 so as not to disturb */ 505 /* JG correct value? */ 506 andq $0x0000fc00,%rax /* reserved bits */ 507 /* JG we've got more registers on x86_64 */ 508 movq PCB_DR7(%rdx),%rcx 509 /* JG correct value? */ 510 andq $~0x0000fc00,%rcx 511 orq %rcx,%rax 512 movq %rax,%dr7 5131: 514 movq %rbx,%rax 515 movq PCB_RBX(%rdx),%rbx 516 517 CHECKNZ((%rsp), %r9) 518 ret 519END(cpu_heavy_restore) 520 521/* 522 * savectx(struct pcb *pcb) 523 * 524 * Update pcb, saving current processor state. 525 */ 526ENTRY(savectx) 527 /* fetch PCB */ 528 /* JG use %rdi instead of %rcx everywhere? */ 529 movq %rdi,%rcx 530 531 /* caller's return address - child won't execute this routine */ 532 movq (%rsp),%rax 533 movq %rax,PCB_RIP(%rcx) 534 movq %rbx,PCB_RBX(%rcx) 535 movq %rsp,PCB_RSP(%rcx) 536 movq %rbp,PCB_RBP(%rcx) 537 movq %r12,PCB_R12(%rcx) 538 movq %r13,PCB_R13(%rcx) 539 movq %r14,PCB_R14(%rcx) 540 movq %r15,PCB_R15(%rcx) 541 542#if 1 543 /* 544 * If npxthread == NULL, then the npx h/w state is irrelevant and the 545 * state had better already be in the pcb. This is true for forks 546 * but not for dumps (the old book-keeping with FP flags in the pcb 547 * always lost for dumps because the dump pcb has 0 flags). 548 * 549 * If npxthread != NULL, then we have to save the npx h/w state to 550 * npxthread's pcb and copy it to the requested pcb, or save to the 551 * requested pcb and reload. Copying is easier because we would 552 * have to handle h/w bugs for reloading. We used to lose the 553 * parent's npx state for forks by forgetting to reload. 554 */ 555 movq PCPU(npxthread),%rax 556 testq %rax,%rax 557 jz 1f 558 559 pushq %rcx /* target pcb */ 560 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */ 561 pushq %rax 562 563 movq %rax,%rdi 564 call npxsave 565 566 popq %rax 567 popq %rcx 568 569 movq $PCB_SAVEFPU_SIZE,%rdx 570 leaq PCB_SAVEFPU(%rcx),%rcx 571 movq %rcx,%rsi 572 movq %rax,%rdi 573 call bcopy 574#endif 575 5761: 577 CHECKNZ((%rsp), %r9) 578 ret 579END(savectx) 580 581/* 582 * cpu_idle_restore() (current thread in %rax on entry) (one-time execution) 583 * (old thread is %rbx on entry) 584 * 585 * Don't bother setting up any regs other than %rbp so backtraces 586 * don't die. This restore function is used to bootstrap into the 587 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for 588 * switching. 589 * 590 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3. 591 * This only occurs during system boot so no special handling is 592 * required for migration. 593 * 594 * If we are an AP we have to call ap_init() before jumping to 595 * cpu_idle(). ap_init() will synchronize with the BP and finish 596 * setting up various ncpu-dependant globaldata fields. This may 597 * happen on UP as well as SMP if we happen to be simulating multiple 598 * cpus. 599 */ 600ENTRY(cpu_idle_restore) 601 /* cli */ 602 /* JG xor? */ 603 movl $0,%ebp 604 /* JG push RBP? */ 605 pushq $0 606 cmpl $0,PCPU(cpuid) 607 je 1f 608 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 609 orl $TDF_RUNNING,TD_FLAGS(%rax) /* manual, no switch_return */ 610 call ap_init 611 /* sti */ 612 jmp cpu_idle 613 614 /* 615 * cpu 0's idle thread entry for the first time must use normal 616 * lwkt_switch_return() semantics or a pending cpu migration on 617 * thread0 will deadlock. 618 */ 6191: 620 pushq %rax 621 movq %rbx,%rdi 622 call lwkt_switch_return 623 popq %rax 624 jmp cpu_idle 625END(cpu_idle_restore) 626 627/* 628 * cpu_kthread_restore() (current thread is %rax on entry) (one-time execution) 629 * (old thread is %rbx on entry) 630 * 631 * Don't bother setting up any regs other then %rbp so backtraces 632 * don't die. This restore function is used to bootstrap into an 633 * LWKT based kernel thread only. cpu_lwkt_switch() will be used 634 * after this. 635 * 636 * Because this switch target does not 'return' to lwkt_switch() 637 * we have to call lwkt_switch_return(otd) to clean up otd. 638 * otd is in %ebx. 639 * 640 * Since all of our context is on the stack we are reentrant and 641 * we can release our critical section and enable interrupts early. 642 */ 643ENTRY(cpu_kthread_restore) 644 /*sti*/ 645 movq TD_PCB(%rax),%r13 646 movq $0,%rbp 647 648 /* 649 * rax and rbx come from the switchout code. Call 650 * lwkt_switch_return(otd). 651 * 652 * NOTE: unlike i386, the %rsi and %rdi are not call-saved regs. 653 */ 654 pushq %rax 655 movq %rbx,%rdi 656 call lwkt_switch_return 657 popq %rax 658 decl TD_CRITCOUNT(%rax) 659 movq PCB_R12(%r13),%rdi /* argument to RBX function */ 660 movq PCB_RBX(%r13),%rax /* thread function */ 661 /* note: top of stack return address inherited by function */ 662 CHECKNZ(%rax, %r9) 663 jmp *%rax 664END(cpu_kthread_restore) 665 666/* 667 * cpu_lwkt_switch(struct thread *) 668 * 669 * Standard LWKT switching function. Only non-scratch registers are 670 * saved and we don't bother with the MMU state or anything else. 671 * 672 * This function is always called while in a critical section. 673 * 674 * There is a one-instruction window where curthread is the new 675 * thread but %rsp still points to the old thread's stack, but 676 * we are protected by a critical section so it is ok. 677 * 678 * YYY BGL, SPL 679 */ 680ENTRY(cpu_lwkt_switch) 681 pushq %rbp /* JG note: GDB hacked to locate ebp relative to td_sp */ 682 /* JG we've got more registers on x86_64 */ 683 pushq %rbx 684 movq PCPU(curthread),%rbx 685 pushq %r12 686 pushq %r13 687 pushq %r14 688 pushq %r15 689 pushfq 690 691#if 1 692 /* 693 * Save the FP state if we have used the FP. Note that calling 694 * npxsave will NULL out PCPU(npxthread). 695 * 696 * We have to deal with the FP state for LWKT threads in case they 697 * happen to get preempted or block while doing an optimized 698 * bzero/bcopy/memcpy. 699 */ 700 cmpq %rbx,PCPU(npxthread) 701 jne 1f 702 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 703 movq TD_SAVEFPU(%rbx),%rdi 704 call npxsave /* do it in a big C function */ 705 movq %r12,%rdi /* restore %rdi */ 7061: 707#endif 708 709 movq %rdi,%rax /* switch to this thread */ 710 pushq $cpu_lwkt_restore 711 movq %rsp,TD_SP(%rbx) 712 movq %rax,PCPU(curthread) 713 movq TD_SP(%rax),%rsp 714 715 /* 716 * %rax contains new thread, %rbx contains old thread. 717 */ 718 CHECKNZ((%rsp), %r9) 719 ret 720END(cpu_lwkt_switch) 721 722/* 723 * cpu_lwkt_restore() (current thread in %rax on entry) 724 * 725 * Standard LWKT restore function. This function is always called 726 * while in a critical section. 727 * 728 * Warning: due to preemption the restore function can be used to 729 * 'return' to the original thread. Interrupt disablement must be 730 * protected through the switch so we cannot run splz here. 731 */ 732ENTRY(cpu_lwkt_restore) 733 /* 734 * NOTE: %rbx is the previous thread and %eax is the new thread. 735 * %rbx is retained throughout so we can return it. 736 * 737 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 738 */ 739 movq %rbx,%rax 740 popfq 741 popq %r15 742 popq %r14 743 popq %r13 744 popq %r12 745 popq %rbx 746 popq %rbp 747 ret 748END(cpu_lwkt_restore) 749 750/* 751 * bootstrap_idle() 752 * 753 * Make AP become the idle loop. 754 */ 755ENTRY(bootstrap_idle) 756 movq PCPU(curthread),%rax 757 movq %rax,%rbx 758 movq TD_SP(%rax),%rsp 759 ret 760END(bootstrap_idle) 761