1/* 2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved. 3 * Copyright (c) 2008 Jordan Gordeev. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Matthew Dillon <dillon@backplane.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * Copyright (c) 1990 The Regents of the University of California. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * William Jolitz. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the University of 52 * California, Berkeley and its contributors. 53 * 4. Neither the name of the University nor the names of its contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 67 * SUCH DAMAGE. 68 * 69 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $ 70 */ 71 72//#include "use_npx.h" 73 74#include <sys/rtprio.h> 75 76#include <machine/asmacros.h> 77#include <machine/segments.h> 78 79#include <machine/pmap.h> 80#include <machine/lock.h> 81 82#define CHECKNZ(expr, scratch_reg) \ 83 movq expr, scratch_reg; testq scratch_reg, scratch_reg; jnz 7f; int $3; 7: 84 85#include "assym.s" 86 87#define MPLOCKED lock ; 88 89 .data 90 91 .globl panic 92 .globl lwkt_switch_return 93 94#if defined(SWTCH_OPTIM_STATS) 95 .globl swtch_optim_stats, tlb_flush_count 96swtch_optim_stats: .long 0 /* number of _swtch_optims */ 97tlb_flush_count: .long 0 98#endif 99 100 .text 101 102 103/* 104 * cpu_heavy_switch(struct thread *next_thread) 105 * 106 * Switch from the current thread to a new thread. This entry 107 * is normally called via the thread->td_switch function, and will 108 * only be called when the current thread is a heavy weight process. 109 * 110 * Some instructions have been reordered to reduce pipeline stalls. 111 * 112 * YYY disable interrupts once giant is removed. 113 */ 114ENTRY(cpu_heavy_switch) 115 /* 116 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15). 117 */ 118 movq PCPU(curthread),%rcx 119 /* On top of the stack is the return adress. */ 120 movq (%rsp),%rax /* (reorder optimization) */ 121 movq TD_PCB(%rcx),%rdx /* RDX = PCB */ 122 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */ 123 movq %rbx,PCB_RBX(%rdx) 124 movq %rsp,PCB_RSP(%rdx) 125 movq %rbp,PCB_RBP(%rdx) 126 movq %r12,PCB_R12(%rdx) 127 movq %r13,PCB_R13(%rdx) 128 movq %r14,PCB_R14(%rdx) 129 movq %r15,PCB_R15(%rdx) 130 131 /* 132 * Clear the cpu bit in the pmap active mask. The restore 133 * function will set the bit in the pmap active mask. 134 * 135 * Special case: when switching between threads sharing the 136 * same vmspace if we avoid clearing the bit we do not have 137 * to reload %cr3 (if we clear the bit we could race page 138 * table ops done by other threads and would have to reload 139 * %cr3, because those ops will not know to IPI us). 140 */ 141 movq %rcx,%rbx /* RBX = oldthread */ 142 movq TD_LWP(%rcx),%rcx /* RCX = oldlwp */ 143 movq TD_LWP(%rdi),%r13 /* R13 = newlwp */ 144 movq LWP_VMSPACE(%rcx), %rcx /* RCX = oldvmspace */ 145 testq %r13,%r13 /* might not be a heavy */ 146 jz 1f 147 cmpq LWP_VMSPACE(%r13),%rcx /* same vmspace? */ 148 je 2f 1491: 150 movslq PCPU(cpuid), %rax 151 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx) 1522: 153 154 /* 155 * Push the LWKT switch restore function, which resumes a heavy 156 * weight process. Note that the LWKT switcher is based on 157 * TD_SP, while the heavy weight process switcher is based on 158 * PCB_RSP. TD_SP is usually two ints pushed relative to 159 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore. 160 */ 161 pushfq 162 movq $cpu_heavy_restore, %rax 163 pushq %rax 164 movq %rsp,TD_SP(%rbx) 165 166 /* 167 * Save debug regs if necessary 168 */ 169 movq PCB_FLAGS(%rdx),%rax 170 andq $PCB_DBREGS,%rax 171 jz 1f /* no, skip over */ 172 movq %dr7,%rax /* yes, do the save */ 173 movq %rax,PCB_DR7(%rdx) 174 /* JG correct value? */ 175 andq $0x0000fc00, %rax /* disable all watchpoints */ 176 movq %rax,%dr7 177 movq %dr6,%rax 178 movq %rax,PCB_DR6(%rdx) 179 movq %dr3,%rax 180 movq %rax,PCB_DR3(%rdx) 181 movq %dr2,%rax 182 movq %rax,PCB_DR2(%rdx) 183 movq %dr1,%rax 184 movq %rax,PCB_DR1(%rdx) 185 movq %dr0,%rax 186 movq %rax,PCB_DR0(%rdx) 1871: 188 189#if 1 190 /* 191 * Save the FP state if we have used the FP. Note that calling 192 * npxsave will NULL out PCPU(npxthread). 193 */ 194 cmpq %rbx,PCPU(npxthread) 195 jne 1f 196 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 197 movq TD_SAVEFPU(%rbx),%rdi 198 call npxsave /* do it in a big C function */ 199 movq %r12,%rdi /* restore %rdi */ 2001: 201#endif 202 203 /* 204 * Switch to the next thread, which was passed as an argument 205 * to cpu_heavy_switch(). The argument is in %rdi. 206 * Set the current thread, load the stack pointer, 207 * and 'ret' into the switch-restore function. 208 * 209 * The switch restore function expects the new thread to be in %rax 210 * and the old one to be in %rbx. 211 * 212 * There is a one-instruction window where curthread is the new 213 * thread but %rsp still points to the old thread's stack, but 214 * we are protected by a critical section so it is ok. 215 */ 216 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */ 217 movq %rax,PCPU(curthread) 218 movq TD_SP(%rax),%rsp 219 CHECKNZ((%rsp), %r9) 220 ret 221 222/* 223 * cpu_exit_switch(struct thread *next) 224 * 225 * The switch function is changed to this when a thread is going away 226 * for good. We have to ensure that the MMU state is not cached, and 227 * we don't bother saving the existing thread state before switching. 228 * 229 * At this point we are in a critical section and this cpu owns the 230 * thread's token, which serves as an interlock until the switchout is 231 * complete. 232 */ 233ENTRY(cpu_exit_switch) 234 /* 235 * Get us out of the vmspace 236 */ 237#if 0 238 movq KPML4phys,%rcx 239 movq %cr3,%rax 240 cmpq %rcx,%rax 241 je 1f 242 /* JG no increment of statistics counters? see cpu_heavy_restore */ 243 movq %rcx,%cr3 2441: 245#endif 246 movq PCPU(curthread),%rbx 247 248 /* 249 * If this is a process/lwp, deactivate the pmap after we've 250 * switched it out. 251 */ 252 movq TD_LWP(%rbx),%rcx 253 testq %rcx,%rcx 254 jz 2f 255 movslq PCPU(cpuid), %rax 256 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 257 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx) 2582: 259 /* 260 * Switch to the next thread. RET into the restore function, which 261 * expects the new thread in RAX and the old in RBX. 262 * 263 * There is a one-instruction window where curthread is the new 264 * thread but %rsp still points to the old thread's stack, but 265 * we are protected by a critical section so it is ok. 266 */ 267 movq %rdi,%rax 268 movq %rax,PCPU(curthread) 269 movq TD_SP(%rax),%rsp 270 CHECKNZ((%rsp), %r9) 271 ret 272 273/* 274 * cpu_heavy_restore() (current thread in %rax on entry) 275 * 276 * Restore the thread after an LWKT switch. This entry is normally 277 * called via the LWKT switch restore function, which was pulled 278 * off the thread stack and jumped to. 279 * 280 * This entry is only called if the thread was previously saved 281 * using cpu_heavy_switch() (the heavy weight process thread switcher), 282 * or when a new process is initially scheduled. 283 * 284 * NOTE: The lwp may be in any state, not necessarily LSRUN, because 285 * a preemption switch may interrupt the process and then return via 286 * cpu_heavy_restore. 287 * 288 * YYY theoretically we do not have to restore everything here, a lot 289 * of this junk can wait until we return to usermode. But for now 290 * we restore everything. 291 * 292 * YYY the PCB crap is really crap, it makes startup a bitch because 293 * we can't switch away. 294 * 295 * YYY note: spl check is done in mi_switch when it splx()'s. 296 */ 297 298ENTRY(cpu_heavy_restore) 299 popfq 300 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 301 302#if defined(SWTCH_OPTIM_STATS) 303 incl _swtch_optim_stats 304#endif 305 /* 306 * Tell the pmap that our cpu is using the VMSPACE now. We cannot 307 * safely test/reload %cr3 until after we have set the bit in the 308 * pmap (remember, we do not hold the MP lock in the switch code). 309 */ 310 movq TD_LWP(%rax),%rcx 311 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 312 movq %rax,%r12 /* save newthread ptr */ 3131: 314 movq VM_PMAP+PM_ACTIVE(%rcx),%rax /* old contents */ 315 movq PCPU(cpumask),%rsi /* new contents */ 316 orq %rax,%rsi 317 MPLOCKED cmpxchgq %rsi,VM_PMAP+PM_ACTIVE(%rcx) 318 jnz 1b 319 320 btq $CPUMASK_BIT,%rax 321 jnc 2f 322 323 movq %rcx,%rdi /* (found to be set) */ 324 call pmap_interlock_wait /* pmap_interlock_wait(%rdi:vm) */ 325 movq %r12,%rax 326 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 3272: 328 movq %r12,%rax 329 /* 330 * Restore the MMU address space. If it is the same as the last 331 * thread we don't have to invalidate the tlb (i.e. reload cr3). 332 * YYY which naturally also means that the PM_ACTIVE bit had better 333 * already have been set before we set it above, check? YYY 334 */ 335#if 0 336 movq %cr3,%rsi 337 movq PCB_CR3(%rdx),%rcx 338 cmpq %rsi,%rcx 339 je 4f 340#if defined(SWTCH_OPTIM_STATS) 341 decl _swtch_optim_stats 342 incl _tlb_flush_count 343#endif 344 movq %rcx,%cr3 3454: 346#endif 347 /* 348 * NOTE: %rbx is the previous thread and %eax is the new thread. 349 * %rbx is retained throughout so we can return it. 350 * 351 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 352 */ 353 354#if 0 355 /* 356 * Deal with the PCB extension, restore the private tss 357 */ 358 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */ 359 movq $1,%rcx /* maybe mark use of a private tss */ 360 testq %rdi,%rdi 361#if JG 362 jnz 2f 363#endif 364 365 /* JG 366 * Going back to the common_tss. We may need to update TSS_ESP0 367 * which sets the top of the supervisor stack when entering from 368 * usermode. The PCB is at the top of the stack but we need another 369 * 16 bytes to take vm86 into account. 370 */ 371 leaq -16(%rdx),%rcx 372 movq %rcx, PCPU(common_tss) + TSS_RSP0 373 movq %rcx, PCPU(rsp0) 374 375#if JG 376 cmpl $0,PCPU(private_tss) /* don't have to reload if */ 377 je 3f /* already using the common TSS */ 378 379 /* JG? */ 380 subq %rcx,%rcx /* unmark use of private tss */ 381 382 /* 383 * Get the address of the common TSS descriptor for the ltr. 384 * There is no way to get the address of a segment-accessed variable 385 * so we store a self-referential pointer at the base of the per-cpu 386 * data area and add the appropriate offset. 387 */ 388 /* JG movl? */ 389 movq $gd_common_tssd, %rdi 390 /* JG name for "%gs:0"? */ 391 addq %gs:0, %rdi 392 393 /* 394 * Move the correct TSS descriptor into the GDT slot, then reload 395 * ltr. 396 */ 3972: 398 /* JG */ 399 movl %rcx,PCPU(private_tss) /* mark/unmark private tss */ 400 movq PCPU(tss_gdt), %rcx /* entry in GDT */ 401 movq 0(%rdi), %rax 402 movq %rax, 0(%rcx) 403 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */ 404 ltr %si 405#endif 406 4073: 408#endif 409#if 0 410 /* 411 * Restore the user %gs and %fs 412 */ 413 movq PCB_FSBASE(%rdx),%r9 414 cmpq PCPU(user_fs),%r9 415 je 4f 416 movq %rdx,%r10 417 movq %r9,PCPU(user_fs) 418 movl $MSR_FSBASE,%ecx 419 movl PCB_FSBASE(%r10),%eax 420 movl PCB_FSBASE+4(%r10),%edx 421 wrmsr 422 movq %r10,%rdx 4234: 424 movq PCB_GSBASE(%rdx),%r9 425 cmpq PCPU(user_gs),%r9 426 je 5f 427 movq %rdx,%r10 428 movq %r9,PCPU(user_gs) 429 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */ 430 movl PCB_GSBASE(%r10),%eax 431 movl PCB_GSBASE+4(%r10),%edx 432 wrmsr 433 movq %r10,%rdx 4345: 435#endif 436 437 /* 438 * Restore general registers. %rbx is restored later. 439 */ 440 movq PCB_RSP(%rdx), %rsp 441 movq PCB_RBP(%rdx), %rbp 442 movq PCB_R12(%rdx), %r12 443 movq PCB_R13(%rdx), %r13 444 movq PCB_R14(%rdx), %r14 445 movq PCB_R15(%rdx), %r15 446 movq PCB_RIP(%rdx), %rax 447 movq %rax, (%rsp) 448 449#if 0 450 /* 451 * Restore the user LDT if we have one 452 */ 453 cmpl $0, PCB_USERLDT(%edx) 454 jnz 1f 455 movl _default_ldt,%eax 456 cmpl PCPU(currentldt),%eax 457 je 2f 458 lldt _default_ldt 459 movl %eax,PCPU(currentldt) 460 jmp 2f 4611: pushl %edx 462 call set_user_ldt 463 popl %edx 4642: 465#endif 466#if 0 467 /* 468 * Restore the user TLS if we have one 469 */ 470 pushl %edx 471 call set_user_TLS 472 popl %edx 473#endif 474 475 /* 476 * Restore the DEBUG register state if necessary. 477 */ 478 movq PCB_FLAGS(%rdx),%rax 479 andq $PCB_DBREGS,%rax 480 jz 1f /* no, skip over */ 481 movq PCB_DR6(%rdx),%rax /* yes, do the restore */ 482 movq %rax,%dr6 483 movq PCB_DR3(%rdx),%rax 484 movq %rax,%dr3 485 movq PCB_DR2(%rdx),%rax 486 movq %rax,%dr2 487 movq PCB_DR1(%rdx),%rax 488 movq %rax,%dr1 489 movq PCB_DR0(%rdx),%rax 490 movq %rax,%dr0 491 movq %dr7,%rax /* load dr7 so as not to disturb */ 492 /* JG correct value? */ 493 andq $0x0000fc00,%rax /* reserved bits */ 494 /* JG we've got more registers on x86_64 */ 495 movq PCB_DR7(%rdx),%rcx 496 /* JG correct value? */ 497 andq $~0x0000fc00,%rcx 498 orq %rcx,%rax 499 movq %rax,%dr7 5001: 501 movq %rbx,%rax 502 movq PCB_RBX(%rdx),%rbx 503 504 CHECKNZ((%rsp), %r9) 505 ret 506 507/* 508 * savectx(struct pcb *pcb) 509 * 510 * Update pcb, saving current processor state. 511 */ 512ENTRY(savectx) 513 /* fetch PCB */ 514 /* JG use %rdi instead of %rcx everywhere? */ 515 movq %rdi,%rcx 516 517 /* caller's return address - child won't execute this routine */ 518 movq (%rsp),%rax 519 movq %rax,PCB_RIP(%rcx) 520 movq %rbx,PCB_RBX(%rcx) 521 movq %rsp,PCB_RSP(%rcx) 522 movq %rbp,PCB_RBP(%rcx) 523 movq %r12,PCB_R12(%rcx) 524 movq %r13,PCB_R13(%rcx) 525 movq %r14,PCB_R14(%rcx) 526 movq %r15,PCB_R15(%rcx) 527 528#if 1 529 /* 530 * If npxthread == NULL, then the npx h/w state is irrelevant and the 531 * state had better already be in the pcb. This is true for forks 532 * but not for dumps (the old book-keeping with FP flags in the pcb 533 * always lost for dumps because the dump pcb has 0 flags). 534 * 535 * If npxthread != NULL, then we have to save the npx h/w state to 536 * npxthread's pcb and copy it to the requested pcb, or save to the 537 * requested pcb and reload. Copying is easier because we would 538 * have to handle h/w bugs for reloading. We used to lose the 539 * parent's npx state for forks by forgetting to reload. 540 */ 541 movq PCPU(npxthread),%rax 542 testq %rax,%rax 543 jz 1f 544 545 pushq %rcx /* target pcb */ 546 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */ 547 pushq %rax 548 549 movq %rax,%rdi 550 call npxsave 551 552 popq %rax 553 popq %rcx 554 555 movq $PCB_SAVEFPU_SIZE,%rdx 556 leaq PCB_SAVEFPU(%rcx),%rcx 557 movq %rcx,%rsi 558 movq %rax,%rdi 559 call bcopy 560#endif 561 5621: 563 CHECKNZ((%rsp), %r9) 564 ret 565 566/* 567 * cpu_idle_restore() (current thread in %rax on entry) (one-time execution) 568 * 569 * Don't bother setting up any regs other than %rbp so backtraces 570 * don't die. This restore function is used to bootstrap into the 571 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for 572 * switching. 573 * 574 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3. 575 * This only occurs during system boot so no special handling is 576 * required for migration. 577 * 578 * If we are an AP we have to call ap_init() before jumping to 579 * cpu_idle(). ap_init() will synchronize with the BP and finish 580 * setting up various ncpu-dependant globaldata fields. This may 581 * happen on UP as well as SMP if we happen to be simulating multiple 582 * cpus. 583 */ 584ENTRY(cpu_idle_restore) 585 /* cli */ 586 /* JG xor? */ 587 movl $0,%ebp 588 /* JG push RBP? */ 589 pushq $0 590 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 591 orl $TDF_RUNNING,TD_FLAGS(%rax) /* manual, no switch_return */ 592 cmpl $0,PCPU(cpuid) 593 je 1f 594 call ap_init 5951: 596 /* sti */ 597 jmp cpu_idle 598 599/* 600 * cpu_kthread_restore() (current thread is %rax on entry) (one-time execution) 601 * 602 * Don't bother setting up any regs other then %rbp so backtraces 603 * don't die. This restore function is used to bootstrap into an 604 * LWKT based kernel thread only. cpu_lwkt_switch() will be used 605 * after this. 606 * 607 * Because this switch target does not 'return' to lwkt_switch() 608 * we have to call lwkt_switch_return(otd) to clean up otd. 609 * otd is in %ebx. 610 * 611 * Since all of our context is on the stack we are reentrant and 612 * we can release our critical section and enable interrupts early. 613 */ 614ENTRY(cpu_kthread_restore) 615 /*sti*/ 616 movq TD_PCB(%rax),%r13 617 movq $0,%rbp 618 619 /* 620 * rax and rbx come from the switchout code. Call 621 * lwkt_switch_return(otd). 622 * 623 * NOTE: unlike i386, %rsi and %rdi are not call-saved regs. 624 */ 625 pushq %rax 626 movq %rbx,%rdi 627 call lwkt_switch_return 628 popq %rax 629 decl TD_CRITCOUNT(%rax) 630 movq PCB_R12(%r13),%rdi /* argument to RBX function */ 631 movq PCB_RBX(%r13),%rax /* thread function */ 632 /* note: top of stack return address inherited by function */ 633 CHECKNZ(%rax, %r9) 634 jmp *%rax 635 636/* 637 * cpu_lwkt_switch(struct thread *) 638 * 639 * Standard LWKT switching function. Only non-scratch registers are 640 * saved and we don't bother with the MMU state or anything else. 641 * 642 * This function is always called while in a critical section. 643 * 644 * There is a one-instruction window where curthread is the new 645 * thread but %rsp still points to the old thread's stack, but 646 * we are protected by a critical section so it is ok. 647 * 648 * YYY BGL, SPL 649 */ 650ENTRY(cpu_lwkt_switch) 651 pushq %rbp /* JG note: GDB hacked to locate ebp relative to td_sp */ 652 /* JG we've got more registers on x86_64 */ 653 pushq %rbx 654 movq PCPU(curthread),%rbx 655 pushq %r12 656 pushq %r13 657 pushq %r14 658 pushq %r15 659 pushfq 660 661#if 1 662 /* 663 * Save the FP state if we have used the FP. Note that calling 664 * npxsave will NULL out PCPU(npxthread). 665 * 666 * We have to deal with the FP state for LWKT threads in case they 667 * happen to get preempted or block while doing an optimized 668 * bzero/bcopy/memcpy. 669 */ 670 cmpq %rbx,PCPU(npxthread) 671 jne 1f 672 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 673 movq TD_SAVEFPU(%rbx),%rdi 674 call npxsave /* do it in a big C function */ 675 movq %r12,%rdi /* restore %rdi */ 6761: 677#endif 678 679 movq %rdi,%rax /* switch to this thread */ 680 pushq $cpu_lwkt_restore 681 movq %rsp,TD_SP(%rbx) 682 movq %rax,PCPU(curthread) 683 movq TD_SP(%rax),%rsp 684 685 /* 686 * %rax contains new thread, %rbx contains old thread. 687 */ 688 CHECKNZ((%rsp), %r9) 689 ret 690 691/* 692 * cpu_lwkt_restore() (current thread in %rax on entry) 693 * 694 * Standard LWKT restore function. This function is always called 695 * while in a critical section. 696 * 697 * Warning: due to preemption the restore function can be used to 698 * 'return' to the original thread. Interrupt disablement must be 699 * protected through the switch so we cannot run splz here. 700 */ 701ENTRY(cpu_lwkt_restore) 702 /* 703 * NOTE: %rbx is the previous thread and %eax is the new thread. 704 * %rbx is retained throughout so we can return it. 705 * 706 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 707 */ 708 movq %rbx,%rax 709 popfq 710 popq %r15 711 popq %r14 712 popq %r13 713 popq %r12 714 popq %rbx 715 popq %rbp 716 ret 717 718/* 719 * bootstrap_idle() 720 * 721 * Make AP become the idle loop. 722 */ 723ENTRY(bootstrap_idle) 724 movq PCPU(curthread),%rax 725 movq %rax,%rbx 726 movq TD_SP(%rax),%rsp 727 ret 728