1/* 2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved. 3 * Copyright (c) 2008 Jordan Gordeev. 4 * 5 * This code is derived from software contributed to The DragonFly Project 6 * by Matthew Dillon <dillon@backplane.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * Copyright (c) 1990 The Regents of the University of California. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * William Jolitz. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the University of 52 * California, Berkeley and its contributors. 53 * 4. Neither the name of the University nor the names of its contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 67 * SUCH DAMAGE. 68 * 69 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $ 70 */ 71 72//#include "use_npx.h" 73 74#include <sys/rtprio.h> 75 76#include <machine/asmacros.h> 77#include <machine/segments.h> 78 79#include <machine/pmap.h> 80#include <machine/lock.h> 81 82#define CHECKNZ(expr, scratch_reg) \ 83 movq expr, scratch_reg; testq scratch_reg, scratch_reg; jnz 7f; int $3; 7: 84 85#include "assym.s" 86 87#if defined(SMP) 88#define MPLOCKED lock ; 89#else 90#define MPLOCKED 91#endif 92 93 .data 94 95 .globl panic 96 .globl lwkt_switch_return 97 98#if defined(SWTCH_OPTIM_STATS) 99 .globl swtch_optim_stats, tlb_flush_count 100swtch_optim_stats: .long 0 /* number of _swtch_optims */ 101tlb_flush_count: .long 0 102#endif 103 104 .text 105 106 107/* 108 * cpu_heavy_switch(struct thread *next_thread) 109 * 110 * Switch from the current thread to a new thread. This entry 111 * is normally called via the thread->td_switch function, and will 112 * only be called when the current thread is a heavy weight process. 113 * 114 * Some instructions have been reordered to reduce pipeline stalls. 115 * 116 * YYY disable interrupts once giant is removed. 117 */ 118ENTRY(cpu_heavy_switch) 119 /* 120 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15). 121 */ 122 movq PCPU(curthread),%rcx 123 /* On top of the stack is the return adress. */ 124 movq (%rsp),%rax /* (reorder optimization) */ 125 movq TD_PCB(%rcx),%rdx /* RDX = PCB */ 126 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */ 127 movq %rbx,PCB_RBX(%rdx) 128 movq %rsp,PCB_RSP(%rdx) 129 movq %rbp,PCB_RBP(%rdx) 130 movq %r12,PCB_R12(%rdx) 131 movq %r13,PCB_R13(%rdx) 132 movq %r14,PCB_R14(%rdx) 133 movq %r15,PCB_R15(%rdx) 134 135 movq %rcx,%rbx /* RBX = curthread */ 136 movq TD_LWP(%rcx),%rcx 137 movslq PCPU(cpuid), %rax 138 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 139 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx) 140 141 /* 142 * Push the LWKT switch restore function, which resumes a heavy 143 * weight process. Note that the LWKT switcher is based on 144 * TD_SP, while the heavy weight process switcher is based on 145 * PCB_RSP. TD_SP is usually two ints pushed relative to 146 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore. 147 */ 148 pushfq 149 movq $cpu_heavy_restore, %rax 150 pushq %rax 151 movq %rsp,TD_SP(%rbx) 152 153 /* 154 * Save debug regs if necessary 155 */ 156 movq PCB_FLAGS(%rdx),%rax 157 andq $PCB_DBREGS,%rax 158 jz 1f /* no, skip over */ 159 movq %dr7,%rax /* yes, do the save */ 160 movq %rax,PCB_DR7(%rdx) 161 /* JG correct value? */ 162 andq $0x0000fc00, %rax /* disable all watchpoints */ 163 movq %rax,%dr7 164 movq %dr6,%rax 165 movq %rax,PCB_DR6(%rdx) 166 movq %dr3,%rax 167 movq %rax,PCB_DR3(%rdx) 168 movq %dr2,%rax 169 movq %rax,PCB_DR2(%rdx) 170 movq %dr1,%rax 171 movq %rax,PCB_DR1(%rdx) 172 movq %dr0,%rax 173 movq %rax,PCB_DR0(%rdx) 1741: 175 176#if 1 177 /* 178 * Save the FP state if we have used the FP. Note that calling 179 * npxsave will NULL out PCPU(npxthread). 180 */ 181 cmpq %rbx,PCPU(npxthread) 182 jne 1f 183 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 184 movq TD_SAVEFPU(%rbx),%rdi 185 call npxsave /* do it in a big C function */ 186 movq %r12,%rdi /* restore %rdi */ 1871: 188#endif 189 190 /* 191 * Switch to the next thread, which was passed as an argument 192 * to cpu_heavy_switch(). The argument is in %rdi. 193 * Set the current thread, load the stack pointer, 194 * and 'ret' into the switch-restore function. 195 * 196 * The switch restore function expects the new thread to be in %rax 197 * and the old one to be in %rbx. 198 * 199 * There is a one-instruction window where curthread is the new 200 * thread but %rsp still points to the old thread's stack, but 201 * we are protected by a critical section so it is ok. 202 */ 203 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */ 204 movq %rax,PCPU(curthread) 205 movq TD_SP(%rax),%rsp 206 CHECKNZ((%rsp), %r9) 207 ret 208 209/* 210 * cpu_exit_switch(struct thread *next) 211 * 212 * The switch function is changed to this when a thread is going away 213 * for good. We have to ensure that the MMU state is not cached, and 214 * we don't bother saving the existing thread state before switching. 215 * 216 * At this point we are in a critical section and this cpu owns the 217 * thread's token, which serves as an interlock until the switchout is 218 * complete. 219 */ 220ENTRY(cpu_exit_switch) 221 /* 222 * Get us out of the vmspace 223 */ 224#if 0 225 movq KPML4phys,%rcx 226 movq %cr3,%rax 227 cmpq %rcx,%rax 228 je 1f 229 /* JG no increment of statistics counters? see cpu_heavy_restore */ 230 movq %rcx,%cr3 2311: 232#endif 233 movq PCPU(curthread),%rbx 234 235 /* 236 * If this is a process/lwp, deactivate the pmap after we've 237 * switched it out. 238 */ 239 movq TD_LWP(%rbx),%rcx 240 testq %rcx,%rcx 241 jz 2f 242 movslq PCPU(cpuid), %rax 243 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 244 MPLOCKED btrq %rax, VM_PMAP+PM_ACTIVE(%rcx) 2452: 246 /* 247 * Switch to the next thread. RET into the restore function, which 248 * expects the new thread in RAX and the old in RBX. 249 * 250 * There is a one-instruction window where curthread is the new 251 * thread but %rsp still points to the old thread's stack, but 252 * we are protected by a critical section so it is ok. 253 */ 254 movq %rdi,%rax 255 movq %rax,PCPU(curthread) 256 movq TD_SP(%rax),%rsp 257 CHECKNZ((%rsp), %r9) 258 ret 259 260/* 261 * cpu_heavy_restore() (current thread in %rax on entry) 262 * 263 * Restore the thread after an LWKT switch. This entry is normally 264 * called via the LWKT switch restore function, which was pulled 265 * off the thread stack and jumped to. 266 * 267 * This entry is only called if the thread was previously saved 268 * using cpu_heavy_switch() (the heavy weight process thread switcher), 269 * or when a new process is initially scheduled. 270 * 271 * NOTE: The lwp may be in any state, not necessarily LSRUN, because 272 * a preemption switch may interrupt the process and then return via 273 * cpu_heavy_restore. 274 * 275 * YYY theoretically we do not have to restore everything here, a lot 276 * of this junk can wait until we return to usermode. But for now 277 * we restore everything. 278 * 279 * YYY the PCB crap is really crap, it makes startup a bitch because 280 * we can't switch away. 281 * 282 * YYY note: spl check is done in mi_switch when it splx()'s. 283 */ 284 285ENTRY(cpu_heavy_restore) 286 popfq 287 movq TD_PCB(%rax),%rdx /* RDX = PCB */ 288 movq TD_LWP(%rax),%rcx 289 290#if defined(SWTCH_OPTIM_STATS) 291 incl _swtch_optim_stats 292#endif 293 /* 294 * Tell the pmap that our cpu is using the VMSPACE now. We cannot 295 * safely test/reload %cr3 until after we have set the bit in the 296 * pmap (remember, we do not hold the MP lock in the switch code). 297 */ 298 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */ 299 movslq PCPU(cpuid), %rsi 300 MPLOCKED btsq %rsi, VM_PMAP+PM_ACTIVE(%rcx) 301 302 /* 303 * Restore the MMU address space. If it is the same as the last 304 * thread we don't have to invalidate the tlb (i.e. reload cr3). 305 * YYY which naturally also means that the PM_ACTIVE bit had better 306 * already have been set before we set it above, check? YYY 307 */ 308#if 0 309 movq %cr3,%rsi 310 movq PCB_CR3(%rdx),%rcx 311 cmpq %rsi,%rcx 312 je 4f 313#if defined(SWTCH_OPTIM_STATS) 314 decl _swtch_optim_stats 315 incl _tlb_flush_count 316#endif 317 movq %rcx,%cr3 3184: 319#endif 320 /* 321 * NOTE: %rbx is the previous thread and %eax is the new thread. 322 * %rbx is retained throughout so we can return it. 323 * 324 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 325 */ 326 327#if 0 328 /* 329 * Deal with the PCB extension, restore the private tss 330 */ 331 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */ 332 movq $1,%rcx /* maybe mark use of a private tss */ 333 testq %rdi,%rdi 334#if JG 335 jnz 2f 336#endif 337 338 /* JG 339 * Going back to the common_tss. We may need to update TSS_ESP0 340 * which sets the top of the supervisor stack when entering from 341 * usermode. The PCB is at the top of the stack but we need another 342 * 16 bytes to take vm86 into account. 343 */ 344 leaq -16(%rdx),%rcx 345 movq %rcx, PCPU(common_tss) + TSS_RSP0 346 movq %rcx, PCPU(rsp0) 347 348#if JG 349 cmpl $0,PCPU(private_tss) /* don't have to reload if */ 350 je 3f /* already using the common TSS */ 351 352 /* JG? */ 353 subq %rcx,%rcx /* unmark use of private tss */ 354 355 /* 356 * Get the address of the common TSS descriptor for the ltr. 357 * There is no way to get the address of a segment-accessed variable 358 * so we store a self-referential pointer at the base of the per-cpu 359 * data area and add the appropriate offset. 360 */ 361 /* JG movl? */ 362 movq $gd_common_tssd, %rdi 363 /* JG name for "%gs:0"? */ 364 addq %gs:0, %rdi 365 366 /* 367 * Move the correct TSS descriptor into the GDT slot, then reload 368 * ltr. 369 */ 3702: 371 /* JG */ 372 movl %rcx,PCPU(private_tss) /* mark/unmark private tss */ 373 movq PCPU(tss_gdt), %rcx /* entry in GDT */ 374 movq 0(%rdi), %rax 375 movq %rax, 0(%rcx) 376 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */ 377 ltr %si 378#endif 379 3803: 381#endif 382#if 0 383 /* 384 * Restore the user %gs and %fs 385 */ 386 movq PCB_FSBASE(%rdx),%r9 387 cmpq PCPU(user_fs),%r9 388 je 4f 389 movq %rdx,%r10 390 movq %r9,PCPU(user_fs) 391 movl $MSR_FSBASE,%ecx 392 movl PCB_FSBASE(%r10),%eax 393 movl PCB_FSBASE+4(%r10),%edx 394 wrmsr 395 movq %r10,%rdx 3964: 397 movq PCB_GSBASE(%rdx),%r9 398 cmpq PCPU(user_gs),%r9 399 je 5f 400 movq %rdx,%r10 401 movq %r9,PCPU(user_gs) 402 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */ 403 movl PCB_GSBASE(%r10),%eax 404 movl PCB_GSBASE+4(%r10),%edx 405 wrmsr 406 movq %r10,%rdx 4075: 408#endif 409 410 /* 411 * Restore general registers. %rbx is restored later. 412 */ 413 movq PCB_RSP(%rdx), %rsp 414 movq PCB_RBP(%rdx), %rbp 415 movq PCB_R12(%rdx), %r12 416 movq PCB_R13(%rdx), %r13 417 movq PCB_R14(%rdx), %r14 418 movq PCB_R15(%rdx), %r15 419 movq PCB_RIP(%rdx), %rax 420 movq %rax, (%rsp) 421 422#if 0 423 /* 424 * Restore the user LDT if we have one 425 */ 426 cmpl $0, PCB_USERLDT(%edx) 427 jnz 1f 428 movl _default_ldt,%eax 429 cmpl PCPU(currentldt),%eax 430 je 2f 431 lldt _default_ldt 432 movl %eax,PCPU(currentldt) 433 jmp 2f 4341: pushl %edx 435 call set_user_ldt 436 popl %edx 4372: 438#endif 439#if 0 440 /* 441 * Restore the user TLS if we have one 442 */ 443 pushl %edx 444 call set_user_TLS 445 popl %edx 446#endif 447 448 /* 449 * Restore the DEBUG register state if necessary. 450 */ 451 movq PCB_FLAGS(%rdx),%rax 452 andq $PCB_DBREGS,%rax 453 jz 1f /* no, skip over */ 454 movq PCB_DR6(%rdx),%rax /* yes, do the restore */ 455 movq %rax,%dr6 456 movq PCB_DR3(%rdx),%rax 457 movq %rax,%dr3 458 movq PCB_DR2(%rdx),%rax 459 movq %rax,%dr2 460 movq PCB_DR1(%rdx),%rax 461 movq %rax,%dr1 462 movq PCB_DR0(%rdx),%rax 463 movq %rax,%dr0 464 movq %dr7,%rax /* load dr7 so as not to disturb */ 465 /* JG correct value? */ 466 andq $0x0000fc00,%rax /* reserved bits */ 467 /* JG we've got more registers on x86_64 */ 468 movq PCB_DR7(%rdx),%rcx 469 /* JG correct value? */ 470 andq $~0x0000fc00,%rcx 471 orq %rcx,%rax 472 movq %rax,%dr7 4731: 474 movq %rbx,%rax 475 movq PCB_RBX(%rdx),%rbx 476 477 CHECKNZ((%rsp), %r9) 478 ret 479 480/* 481 * savectx(struct pcb *pcb) 482 * 483 * Update pcb, saving current processor state. 484 */ 485ENTRY(savectx) 486 /* fetch PCB */ 487 /* JG use %rdi instead of %rcx everywhere? */ 488 movq %rdi,%rcx 489 490 /* caller's return address - child won't execute this routine */ 491 movq (%rsp),%rax 492 movq %rax,PCB_RIP(%rcx) 493 movq %rbx,PCB_RBX(%rcx) 494 movq %rsp,PCB_RSP(%rcx) 495 movq %rbp,PCB_RBP(%rcx) 496 movq %r12,PCB_R12(%rcx) 497 movq %r13,PCB_R13(%rcx) 498 movq %r14,PCB_R14(%rcx) 499 movq %r15,PCB_R15(%rcx) 500 501#if 1 502 /* 503 * If npxthread == NULL, then the npx h/w state is irrelevant and the 504 * state had better already be in the pcb. This is true for forks 505 * but not for dumps (the old book-keeping with FP flags in the pcb 506 * always lost for dumps because the dump pcb has 0 flags). 507 * 508 * If npxthread != NULL, then we have to save the npx h/w state to 509 * npxthread's pcb and copy it to the requested pcb, or save to the 510 * requested pcb and reload. Copying is easier because we would 511 * have to handle h/w bugs for reloading. We used to lose the 512 * parent's npx state for forks by forgetting to reload. 513 */ 514 movq PCPU(npxthread),%rax 515 testq %rax,%rax 516 jz 1f 517 518 pushq %rcx /* target pcb */ 519 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */ 520 pushq %rax 521 522 movq %rax,%rdi 523 call npxsave 524 525 popq %rax 526 popq %rcx 527 528 movq $PCB_SAVEFPU_SIZE,%rdx 529 leaq PCB_SAVEFPU(%rcx),%rcx 530 movq %rcx,%rsi 531 movq %rax,%rdi 532 call bcopy 533#endif 534 5351: 536 CHECKNZ((%rsp), %r9) 537 ret 538 539/* 540 * cpu_idle_restore() (current thread in %rax on entry) (one-time execution) 541 * 542 * Don't bother setting up any regs other than %rbp so backtraces 543 * don't die. This restore function is used to bootstrap into the 544 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for 545 * switching. 546 * 547 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3. 548 * This only occurs during system boot so no special handling is 549 * required for migration. 550 * 551 * If we are an AP we have to call ap_init() before jumping to 552 * cpu_idle(). ap_init() will synchronize with the BP and finish 553 * setting up various ncpu-dependant globaldata fields. This may 554 * happen on UP as well as SMP if we happen to be simulating multiple 555 * cpus. 556 */ 557ENTRY(cpu_idle_restore) 558 /* cli */ 559 /* JG xor? */ 560 movl $0,%ebp 561 /* JG push RBP? */ 562 pushq $0 563 andl $~TDF_RUNNING,TD_FLAGS(%rbx) 564 orl $TDF_RUNNING,TD_FLAGS(%rax) /* manual, no switch_return */ 565#ifdef SMP 566 cmpl $0,PCPU(cpuid) 567 je 1f 568 call ap_init 5691: 570#endif 571 /* sti */ 572 jmp cpu_idle 573 574/* 575 * cpu_kthread_restore() (current thread is %rax on entry) (one-time execution) 576 * 577 * Don't bother setting up any regs other then %rbp so backtraces 578 * don't die. This restore function is used to bootstrap into an 579 * LWKT based kernel thread only. cpu_lwkt_switch() will be used 580 * after this. 581 * 582 * Because this switch target does not 'return' to lwkt_switch() 583 * we have to call lwkt_switch_return(otd) to clean up otd. 584 * otd is in %ebx. 585 * 586 * Since all of our context is on the stack we are reentrant and 587 * we can release our critical section and enable interrupts early. 588 */ 589ENTRY(cpu_kthread_restore) 590 /*sti*/ 591 movq TD_PCB(%rax),%r13 592 movq $0,%rbp 593 594 /* 595 * rax and rbx come from the switchout code. Call 596 * lwkt_switch_return(otd). 597 * 598 * NOTE: unlike i386, %rsi and %rdi are not call-saved regs. 599 */ 600 pushq %rax 601 movq %rbx,%rdi 602 call lwkt_switch_return 603 popq %rax 604 decl TD_CRITCOUNT(%rax) 605 movq PCB_R12(%r13),%rdi /* argument to RBX function */ 606 movq PCB_RBX(%r13),%rax /* thread function */ 607 /* note: top of stack return address inherited by function */ 608 CHECKNZ(%rax, %r9) 609 jmp *%rax 610 611/* 612 * cpu_lwkt_switch(struct thread *) 613 * 614 * Standard LWKT switching function. Only non-scratch registers are 615 * saved and we don't bother with the MMU state or anything else. 616 * 617 * This function is always called while in a critical section. 618 * 619 * There is a one-instruction window where curthread is the new 620 * thread but %rsp still points to the old thread's stack, but 621 * we are protected by a critical section so it is ok. 622 * 623 * YYY BGL, SPL 624 */ 625ENTRY(cpu_lwkt_switch) 626 pushq %rbp /* JG note: GDB hacked to locate ebp relative to td_sp */ 627 /* JG we've got more registers on x86_64 */ 628 pushq %rbx 629 movq PCPU(curthread),%rbx 630 pushq %r12 631 pushq %r13 632 pushq %r14 633 pushq %r15 634 pushfq 635 636#if 1 637 /* 638 * Save the FP state if we have used the FP. Note that calling 639 * npxsave will NULL out PCPU(npxthread). 640 * 641 * We have to deal with the FP state for LWKT threads in case they 642 * happen to get preempted or block while doing an optimized 643 * bzero/bcopy/memcpy. 644 */ 645 cmpq %rbx,PCPU(npxthread) 646 jne 1f 647 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */ 648 movq TD_SAVEFPU(%rbx),%rdi 649 call npxsave /* do it in a big C function */ 650 movq %r12,%rdi /* restore %rdi */ 6511: 652#endif 653 654 movq %rdi,%rax /* switch to this thread */ 655 pushq $cpu_lwkt_restore 656 movq %rsp,TD_SP(%rbx) 657 movq %rax,PCPU(curthread) 658 movq TD_SP(%rax),%rsp 659 660 /* 661 * %rax contains new thread, %rbx contains old thread. 662 */ 663 CHECKNZ((%rsp), %r9) 664 ret 665 666/* 667 * cpu_lwkt_restore() (current thread in %rax on entry) 668 * 669 * Standard LWKT restore function. This function is always called 670 * while in a critical section. 671 * 672 * Warning: due to preemption the restore function can be used to 673 * 'return' to the original thread. Interrupt disablement must be 674 * protected through the switch so we cannot run splz here. 675 */ 676ENTRY(cpu_lwkt_restore) 677 /* 678 * NOTE: %rbx is the previous thread and %eax is the new thread. 679 * %rbx is retained throughout so we can return it. 680 * 681 * lwkt_switch[_return] is responsible for handling TDF_RUNNING. 682 */ 683 movq %rbx,%rax 684 popfq 685 popq %r15 686 popq %r14 687 popq %r13 688 popq %r12 689 popq %rbx 690 popq %rbp 691 ret 692 693/* 694 * bootstrap_idle() 695 * 696 * Make AP become the idle loop. 697 */ 698ENTRY(bootstrap_idle) 699 movq PCPU(curthread),%rax 700 movq %rax,%rbx 701 movq TD_SP(%rax),%rsp 702 ret 703