1 /* 2 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/sys/machintr.h,v 1.7 2007/04/30 16:46:01 dillon Exp $ 35 */ 36 /* 37 * This module defines the ABI for the machine-independant cpu interrupt 38 * vector and masking layer. 39 */ 40 41 #ifndef _SYS_MACHINTR_H_ 42 #define _SYS_MACHINTR_H_ 43 44 #ifdef _KERNEL 45 46 #ifndef _SYS_BUS_H_ 47 #include <sys/bus.h> 48 #endif 49 50 struct rman; 51 52 enum machintr_type { MACHINTR_GENERIC, MACHINTR_ICU, MACHINTR_IOAPIC }; 53 54 #define MACHINTR_VECTOR_SETUP 1 55 #define MACHINTR_VECTOR_TEARDOWN 2 56 57 /* 58 * Machine interrupt ABIs - registered at boot-time 59 */ 60 struct machintr_abi { 61 enum machintr_type type; 62 63 void (*intr_disable)(int); /* hardware disable intr */ 64 void (*intr_enable)(int); /* hardware enable intr */ 65 void (*intr_setup)(int, int); /* setup intr */ 66 void (*intr_teardown)(int); /* tear down intr */ 67 void (*intr_config) /* config intr */ 68 (int, enum intr_trigger, enum intr_polarity); 69 int (*intr_cpuid)(int); /* intr target cpu */ 70 71 int (*msi_alloc) /* alloc count intrs on cpu */ 72 (int intrs[], int count, int cpuid); 73 void (*msi_release) /* release count intrs on cpu */ 74 (const int intrs[], int count, int cpuid); 75 void (*msi_map) /* addr/data for intr on cpu */ 76 (int intr, uint64_t *addr, uint32_t *data, int cpuid); 77 78 void (*finalize)(void); /* final before ints enabled */ 79 void (*cleanup)(void); /* cleanup */ 80 void (*setdefault)(void); /* set default vectors */ 81 void (*stabilize)(void); /* stable before ints enabled */ 82 void (*initmap)(void); /* init irq mapping */ 83 void (*rman_setup)(struct rman *); /* setup rman */ 84 }; 85 86 #define machintr_intr_enable(intr) MachIntrABI.intr_enable(intr) 87 #define machintr_intr_disable(intr) MachIntrABI.intr_disable(intr) 88 #define machintr_intr_setup(intr, flags) \ 89 MachIntrABI.intr_setup((intr), (flags)) 90 #define machintr_intr_teardown(intr) \ 91 MachIntrABI.intr_teardown((intr)) 92 93 #define machintr_intr_config(intr, trig, pola) \ 94 MachIntrABI.intr_config((intr), (trig), (pola)) 95 #define machintr_intr_cpuid(intr) MachIntrABI.intr_cpuid((intr)) 96 97 extern struct machintr_abi MachIntrABI; 98 99 #endif /* _KERNEL */ 100 101 #endif /* _SYS_MACHINTR_H_ */ 102