1 /*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: src/tools/tools/ath/common/dumpregs_5212.c,v 1.2 2009/03/12 00:03:55 sam Exp $ 30 */ 31 #include "diag.h" 32 33 #include "ah.h" 34 #include "ah_internal.h" 35 #include "ar5212/ar5212reg.h" 36 #include "ar5212/ar5212phy.h" 37 38 #include "dumpregs.h" 39 40 #define N(a) (sizeof(a) / sizeof(a[0])) 41 42 #define MAC5212 SREV(4,5), SREV(16,0) 43 #define MAC5213 SREV(5,9), SREV(16,0) 44 45 static struct dumpreg ar5212regs[] = { 46 DEFBASIC(AR_CR, "CR"), 47 DEFBASIC(AR_RXDP, "RXDP"), 48 DEFBASICfmt(AR_CFG, "CFG", 49 "\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\6AP_ADHOC\11PHOK\12EEBS"), 50 DEFBASIC(AR_IER, "IER"), 51 DEFBASIC(AR_TXCFG, "TXCFG"), 52 DEFBASICfmt(AR_RXCFG, "RXCFG", 53 "\20\6JUMBO_ENA\7JUMBO_WRAP\10SLEEP_DEBUG"), 54 DEFBASIC(AR_MIBC, "MIBC"), 55 DEFBASIC(AR_TOPS, "TOPS"), 56 DEFBASIC(AR_RXNPTO, "RXNPTO"), 57 DEFBASIC(AR_TXNPTO, "TXNPTO"), 58 DEFBASIC(AR_RPGTO, "RPGTO"), 59 DEFBASIC(AR_RPCNT, "RPCNT"), 60 DEFBASIC(AR_MACMISC, "MACMISC"), 61 DEFBASIC(AR_SPC_0, "SPC_0"), 62 DEFBASIC(AR_SPC_1, "SPC_1"), 63 64 DEFINTfmt(AR_ISR, "ISR", 65 "\20\1RXOK\2RXDESC\3RXERR\4RXNOPKT\5RXEOL\6RXORN\7TXOK\10TXDESC" 66 "\11TXERR\12TXNOPKT\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM" 67 "\21SWBA\22BRSSI\23BMISS\24HIUERR\25BNR\26RXCHIRP\27RXDOPPL\30BCNMISS" 68 "\31TIM\32GPIO\33QCBROVF\34QCBRURN\35QTRIG"), 69 DEFINT(AR_ISR_S0, "ISR_S0"), 70 DEFINT(AR_ISR_S1, "ISR_S1"), 71 DEFINTfmt(AR_ISR_S2, "ISR_S2", 72 "\20\21MCABT\22SSERR\23DPERR\24TIM\25CABEND\26DTIMSYNC\27BCNTO" 73 "\30CABTO\31DTIM"), 74 DEFINT(AR_ISR_S3, "ISR_S3"), 75 DEFINT(AR_ISR_S4, "ISR_S4"), 76 DEFINTfmt(AR_IMR, "IMR", 77 "\20\1RXOK\2RXDESC\3RXERR\4RXNOPKT\5RXEOL\6RXORN\7TXOK\10TXDESC" 78 "\11TXERR\12TXNOPKT\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM" 79 "\21SWBA\22BRSSI\23BMISS\24HIUERR\25BNR\26RXCHIRP\27RXDOPPL\30BCNMISS" 80 "\31TIM\32GPIO\33QCBROVF\34QCBRURN\35QTRIG"), 81 DEFINT(AR_IMR_S0, "IMR_S0"), 82 DEFINT(AR_IMR_S1, "IMR_S1"), 83 DEFINTfmt(AR_IMR_S2, "IMR_S2", 84 "\20\21MCABT\22SSERR\23DPERR\24TIM\25CABEND\26DTIMSYNC\27BCNTO" 85 "\30CABTO\31DTIM"), 86 DEFINT(AR_IMR_S3, "IMR_S3"), 87 DEFINT(AR_IMR_S4, "IMR_S4"), 88 /* NB: don't read the RAC so we don't affect operation */ 89 DEFVOID(AR_ISR_RAC, "ISR_RAC"), 90 DEFINT(AR_ISR_S0_S, "ISR_S0_S"), 91 DEFINT(AR_ISR_S1_S, "ISR_S1_S"), 92 DEFINT(AR_ISR_S2_S, "ISR_S2_S"), 93 DEFINT(AR_ISR_S3_S, "ISR_S3_S"), 94 DEFINT(AR_ISR_S4_S, "ISR_S4_S"), 95 96 DEFBASIC(AR_DMADBG_0, "DMADBG0"), 97 DEFBASIC(AR_DMADBG_1, "DMADBG1"), 98 DEFBASIC(AR_DMADBG_2, "DMADBG2"), 99 DEFBASIC(AR_DMADBG_3, "DMADBG3"), 100 DEFBASIC(AR_DMADBG_4, "DMADBG4"), 101 DEFBASIC(AR_DMADBG_5, "DMADBG5"), 102 DEFBASIC(AR_DMADBG_6, "DMADBG6"), 103 DEFBASIC(AR_DMADBG_7, "DMADBG7"), 104 105 DEFBASIC(AR_DCM_A, "DCM_A"), 106 DEFBASIC(AR_DCM_D, "DCM_D"), 107 DEFBASIC(AR_DCCFG, "DCCFG"), 108 DEFBASIC(AR_CCFG, "CCFG"), 109 DEFBASIC(AR_CCUCFG, "CCUCFG"), 110 DEFBASIC(AR_CPC_0, "CPC0"), 111 DEFBASIC(AR_CPC_1, "CPC1"), 112 DEFBASIC(AR_CPC_2, "CPC2"), 113 DEFBASIC(AR_CPC_3, "CPC3"), 114 DEFBASIC(AR_CPCOVF, "CPCOVF"), 115 116 DEFQCU(AR_Q0_TXDP, "Q0_TXDP"), 117 DEFQCU(AR_Q1_TXDP, "Q1_TXDP"), 118 DEFQCU(AR_Q2_TXDP, "Q2_TXDP"), 119 DEFQCU(AR_Q3_TXDP, "Q3_TXDP"), 120 DEFQCU(AR_Q4_TXDP, "Q4_TXDP"), 121 DEFQCU(AR_Q5_TXDP, "Q5_TXDP"), 122 DEFQCU(AR_Q6_TXDP, "Q6_TXDP"), 123 DEFQCU(AR_Q7_TXDP, "Q7_TXDP"), 124 DEFQCU(AR_Q8_TXDP, "Q8_TXDP"), 125 DEFQCU(AR_Q9_TXDP, "Q9_TXDP"), 126 127 DEFQCU(AR_Q_TXE, "Q_TXE"), 128 DEFQCU(AR_Q_TXD, "Q_TXD"), 129 130 DEFQCU(AR_Q0_CBRCFG, "Q0_CBR"), 131 DEFQCU(AR_Q1_CBRCFG, "Q1_CBR"), 132 DEFQCU(AR_Q2_CBRCFG, "Q2_CBR"), 133 DEFQCU(AR_Q3_CBRCFG, "Q3_CBR"), 134 DEFQCU(AR_Q4_CBRCFG, "Q4_CBR"), 135 DEFQCU(AR_Q5_CBRCFG, "Q5_CBR"), 136 DEFQCU(AR_Q6_CBRCFG, "Q6_CBR"), 137 DEFQCU(AR_Q7_CBRCFG, "Q7_CBR"), 138 DEFQCU(AR_Q8_CBRCFG, "Q8_CBR"), 139 DEFQCU(AR_Q9_CBRCFG, "Q9_CBR"), 140 141 DEFQCU(AR_Q0_RDYTIMECFG, "Q0_RDYT"), 142 DEFQCU(AR_Q1_RDYTIMECFG, "Q1_RDYT"), 143 DEFQCU(AR_Q2_RDYTIMECFG, "Q2_RDYT"), 144 DEFQCU(AR_Q3_RDYTIMECFG, "Q3_RDYT"), 145 DEFQCU(AR_Q4_RDYTIMECFG, "Q4_RDYT"), 146 DEFQCU(AR_Q5_RDYTIMECFG, "Q5_RDYT"), 147 DEFQCU(AR_Q6_RDYTIMECFG, "Q6_RDYT"), 148 DEFQCU(AR_Q7_RDYTIMECFG, "Q7_RDYT"), 149 DEFQCU(AR_Q8_RDYTIMECFG, "Q8_RDYT"), 150 DEFQCU(AR_Q9_RDYTIMECFG, "Q9_RDYT"), 151 152 DEFQCU(AR_Q_ONESHOTARM_SC, "Q_ONESHOTARM_SC"), 153 DEFQCU(AR_Q_ONESHOTARM_CC, "Q_ONESHOTARM_CC"), 154 155 DEFQCU(AR_Q0_MISC, "Q0_MISC"), 156 DEFQCU(AR_Q1_MISC, "Q1_MISC"), 157 DEFQCU(AR_Q2_MISC, "Q2_MISC"), 158 DEFQCU(AR_Q3_MISC, "Q3_MISC"), 159 DEFQCU(AR_Q4_MISC, "Q4_MISC"), 160 DEFQCU(AR_Q5_MISC, "Q5_MISC"), 161 DEFQCU(AR_Q6_MISC, "Q6_MISC"), 162 DEFQCU(AR_Q7_MISC, "Q7_MISC"), 163 DEFQCU(AR_Q8_MISC, "Q8_MISC"), 164 DEFQCU(AR_Q9_MISC, "Q9_MISC"), 165 166 DEFQCU(AR_Q0_STS, "Q0_STS"), 167 DEFQCU(AR_Q1_STS, "Q1_STS"), 168 DEFQCU(AR_Q2_STS, "Q2_STS"), 169 DEFQCU(AR_Q3_STS, "Q3_STS"), 170 DEFQCU(AR_Q4_STS, "Q4_STS"), 171 DEFQCU(AR_Q5_STS, "Q5_STS"), 172 DEFQCU(AR_Q6_STS, "Q6_STS"), 173 DEFQCU(AR_Q7_STS, "Q7_STS"), 174 DEFQCU(AR_Q8_STS, "Q8_STS"), 175 DEFQCU(AR_Q9_STS, "Q9_STS"), 176 177 DEFQCU(AR_Q_RDYTIMESHDN, "Q_RDYTIMSHD"), 178 179 DEFQCU(AR_Q_CBBS, "Q_CBBS"), 180 DEFQCU(AR_Q_CBBA, "Q_CBBA"), 181 DEFQCU(AR_Q_CBC, "Q_CBC"), 182 183 DEFDCU(AR_D0_QCUMASK, "D0_MASK"), 184 DEFDCU(AR_D1_QCUMASK, "D1_MASK"), 185 DEFDCU(AR_D2_QCUMASK, "D2_MASK"), 186 DEFDCU(AR_D3_QCUMASK, "D3_MASK"), 187 DEFDCU(AR_D4_QCUMASK, "D4_MASK"), 188 DEFDCU(AR_D5_QCUMASK, "D5_MASK"), 189 DEFDCU(AR_D6_QCUMASK, "D6_MASK"), 190 DEFDCU(AR_D7_QCUMASK, "D7_MASK"), 191 DEFDCU(AR_D8_QCUMASK, "D8_MASK"), 192 DEFDCU(AR_D9_QCUMASK, "D9_MASK"), 193 194 DEFDCU(AR_D0_LCL_IFS, "D0_IFS"), 195 DEFDCU(AR_D1_LCL_IFS, "D1_IFS"), 196 DEFDCU(AR_D2_LCL_IFS, "D2_IFS"), 197 DEFDCU(AR_D3_LCL_IFS, "D3_IFS"), 198 DEFDCU(AR_D4_LCL_IFS, "D4_IFS"), 199 DEFDCU(AR_D5_LCL_IFS, "D5_IFS"), 200 DEFDCU(AR_D6_LCL_IFS, "D6_IFS"), 201 DEFDCU(AR_D7_LCL_IFS, "D7_IFS"), 202 DEFDCU(AR_D8_LCL_IFS, "D8_IFS"), 203 DEFDCU(AR_D9_LCL_IFS, "D9_IFS"), 204 205 DEFDCU(AR_D0_RETRY_LIMIT, "D0_RTRY"), 206 DEFDCU(AR_D1_RETRY_LIMIT, "D1_RTRY"), 207 DEFDCU(AR_D2_RETRY_LIMIT, "D2_RTRY"), 208 DEFDCU(AR_D3_RETRY_LIMIT, "D3_RTRY"), 209 DEFDCU(AR_D4_RETRY_LIMIT, "D4_RTRY"), 210 DEFDCU(AR_D5_RETRY_LIMIT, "D5_RTRY"), 211 DEFDCU(AR_D6_RETRY_LIMIT, "D6_RTRY"), 212 DEFDCU(AR_D7_RETRY_LIMIT, "D7_RTRY"), 213 DEFDCU(AR_D8_RETRY_LIMIT, "D8_RTRY"), 214 DEFDCU(AR_D9_RETRY_LIMIT, "D9_RTRY"), 215 216 DEFDCU(AR_D0_CHNTIME, "D0_CHNT"), 217 DEFDCU(AR_D1_CHNTIME, "D1_CHNT"), 218 DEFDCU(AR_D2_CHNTIME, "D2_CHNT"), 219 DEFDCU(AR_D3_CHNTIME, "D3_CHNT"), 220 DEFDCU(AR_D4_CHNTIME, "D4_CHNT"), 221 DEFDCU(AR_D5_CHNTIME, "D5_CHNT"), 222 DEFDCU(AR_D6_CHNTIME, "D6_CHNT"), 223 DEFDCU(AR_D7_CHNTIME, "D7_CHNT"), 224 DEFDCU(AR_D8_CHNTIME, "D8_CHNT"), 225 DEFDCU(AR_D9_CHNTIME, "D9_CHNT"), 226 227 DEFDCU(AR_D0_MISC, "D0_MISC"), 228 DEFDCU(AR_D1_MISC, "D1_MISC"), 229 DEFDCU(AR_D2_MISC, "D2_MISC"), 230 DEFDCU(AR_D3_MISC, "D3_MISC"), 231 DEFDCU(AR_D4_MISC, "D4_MISC"), 232 DEFDCU(AR_D5_MISC, "D5_MISC"), 233 DEFDCU(AR_D6_MISC, "D6_MISC"), 234 DEFDCU(AR_D7_MISC, "D7_MISC"), 235 DEFDCU(AR_D8_MISC, "D8_MISC"), 236 DEFDCU(AR_D9_MISC, "D9_MISC"), 237 238 _DEFREG(AR_D_SEQNUM, "D_SEQ", DUMP_BASIC | DUMP_DCU), 239 DEFBASIC(AR_D_GBL_IFS_SIFS, "D_SIFS"), 240 DEFBASIC(AR_D_GBL_IFS_SLOT, "D_SLOT"), 241 DEFBASIC(AR_D_GBL_IFS_EIFS, "D_EIFS"), 242 DEFBASIC(AR_D_GBL_IFS_MISC, "D_MISC"), 243 DEFBASIC(AR_D_FPCTL, "D_FPCTL"), 244 DEFBASIC(AR_D_TXPSE, "D_TXPSE"), 245 DEFVOID(AR_D_TXBLK_CMD, "D_CMD"), 246 #if 0 247 DEFVOID(AR_D_TXBLK_DATA, "D_DATA"), 248 #endif 249 DEFVOID(AR_D_TXBLK_CLR, "D_CLR"), 250 DEFVOID(AR_D_TXBLK_SET, "D_SET"), 251 DEFBASIC(AR_RC, "RC"), 252 DEFBASICfmt(AR_SCR, "SCR", 253 "\20\22SLDTP\23SLDWP\24SLEPOL\25MIBIE"), 254 DEFBASIC(AR_INTPEND, "INTPEND"), 255 DEFBASIC(AR_SFR, "SFR"), 256 DEFBASIC(AR_PCICFG, "PCICFG"), 257 DEFBASIC(AR_GPIOCR, "GPIOCR"), 258 DEFBASIC(AR_GPIODO, "GPIODO"), 259 DEFBASIC(AR_GPIODI, "GPIODI"), 260 DEFBASIC(AR_SREV, "SREV"), 261 262 DEFBASICx(AR_PCIE_PMC, "PCIEPMC", SREV(4,8), SREV(13,7)), 263 DEFBASICx(AR_PCIE_SERDES, "SERDES", SREV(4,8), SREV(13,7)), 264 DEFBASICx(AR_PCIE_SERDES2, "SERDES2", SREV(4,8), SREV(13,7)), 265 DEFVOID(AR_EEPROM_ADDR, "EEADDR"), 266 DEFVOID(AR_EEPROM_DATA, "EEDATA"), 267 DEFVOID(AR_EEPROM_CMD, "EECMD"), 268 DEFVOID(AR_EEPROM_STS, "EESTS"), 269 DEFVOID(AR_EEPROM_CFG, "EECFG"), 270 DEFBASIC(AR_STA_ID0, "STA_ID0"), 271 DEFBASICfmt(AR_STA_ID1, "STA_ID1", 272 "\20\21STA_AP\22ADHOC\23PWR_SAV\24KSRCHDIS\25PCF\26USE_DEFANT" 273 "\27UPD_DEFANT\30RTS_USE_DEF\31ACKCTS_6MB\32BASE_RATE11B\33USE_DA_SG" 274 "\34CRPT_MIC_ENABLE\35KSRCH_MODE\36PRE_SEQNUM\37CBCIV_ENDIAN" 275 "\40MCAST_KSRCH"), 276 DEFBASIC(AR_BSS_ID0, "BSS_ID0"), 277 DEFBASIC(AR_BSS_ID1, "BSS_ID1"), 278 DEFBASIC(AR_SLOT_TIME, "SLOTTIME"), 279 DEFBASIC(AR_TIME_OUT, "TIME_OUT"), 280 DEFBASIC(AR_RSSI_THR, "RSSI_THR"), 281 DEFBASIC(AR_USEC, "USEC"), 282 DEFBASIC(AR_BEACON, "BEACON"), 283 DEFBASIC(AR_CFP_PERIOD, "CFP_PER"), 284 DEFBASIC(AR_TIMER0, "TIMER0"), 285 DEFBASIC(AR_TIMER1, "TIMER1"), 286 DEFBASIC(AR_TIMER2, "TIMER2"), 287 DEFBASIC(AR_TIMER3, "TIMER3"), 288 DEFBASIC(AR_CFP_DUR, "CFP_DUR"), 289 DEFBASICfmt(AR_RX_FILTER, "RXFILTER", 290 "\20\1UCAST\2MCAST\3BCAST\4CONTROL\5BEACON\6PROM\7XR_POLL\10PROBE_REQ"), 291 DEFBASIC(AR_MCAST_FIL0, "MCAST_0"), 292 DEFBASIC(AR_MCAST_FIL1, "MCAST_1"), 293 DEFBASICfmt(AR_DIAG_SW, "DIAG_SW", 294 "\20\1CACHE_ACK\2ACK_DIS\3CTS_DIS\4ENCRYPT_DIS\5DECRYPT_DIS\6RX_DIS" 295 "\7CORR_FCS\10CHAN_INFO\11EN_SCRAMSD\22FRAME_NV0\25RX_CLR_HI" 296 "\26IGNORE_CS\27CHAN_IDLE\30PHEAR_ME"), 297 DEFBASIC(AR_TSF_L32, "TSF_L32"), 298 DEFBASIC(AR_TSF_U32, "TSF_U32"), 299 DEFBASIC(AR_TST_ADDAC, "TST_ADAC"), 300 DEFBASIC(AR_DEF_ANTENNA, "DEF_ANT"), 301 DEFBASIC(AR_QOS_MASK, "QOS_MASK"), 302 DEFBASIC(AR_SEQ_MASK, "SEQ_MASK"), 303 DEFBASIC(AR_OBSERV_2, "OBSERV2"), 304 DEFBASIC(AR_OBSERV_1, "OBSERV1"), 305 306 DEFBASIC(AR_LAST_TSTP, "LAST_TST"), 307 DEFBASIC(AR_NAV, "NAV"), 308 DEFBASIC(AR_RTS_OK, "RTS_OK"), 309 DEFBASIC(AR_RTS_FAIL, "RTS_FAIL"), 310 DEFBASIC(AR_ACK_FAIL, "ACK_FAIL"), 311 DEFBASIC(AR_FCS_FAIL, "FCS_FAIL"), 312 DEFBASIC(AR_BEACON_CNT, "BEAC_CNT"), 313 314 DEFBASIC(AR_SLEEP1, "SLEEP1"), 315 DEFBASIC(AR_SLEEP2, "SLEEP2"), 316 DEFBASIC(AR_SLEEP3, "SLEEP3"), 317 DEFBASIC(AR_BSSMSKL, "BSSMSKL"), 318 DEFBASIC(AR_BSSMSKU, "BSSMSKU"), 319 DEFBASIC(AR_TPC, "TPC"), 320 DEFBASIC(AR_TFCNT, "TFCNT"), 321 DEFBASIC(AR_RFCNT, "RFCNT"), 322 DEFBASIC(AR_RCCNT, "RCCNT"), 323 DEFBASIC(AR_CCCNT, "CCCNT"), 324 DEFBASIC(AR_QUIET1, "QUIET1"), 325 DEFBASIC(AR_QUIET2, "QUIET2"), 326 DEFBASIC(AR_TSF_PARM, "TSF_PARM"), 327 DEFBASIC(AR_NOACK, "NOACK"), 328 DEFBASIC(AR_PHY_ERR, "PHY_ERR"), 329 DEFBASIC(AR_QOS_CONTROL, "QOS_CTRL"), 330 DEFBASIC(AR_QOS_SELECT, "QOS_SEL"), 331 DEFBASIC(AR_MISC_MODE, "MISCMODE"), 332 DEFBASIC(AR_FILTOFDM, "FILTOFDM"), 333 DEFBASIC(AR_FILTCCK, "FILTCCK"), 334 DEFBASIC(AR_PHYCNT1, "PHYCNT1"), 335 DEFBASIC(AR_PHYCNTMASK1, "PHYCMSK1"), 336 DEFBASIC(AR_PHYCNT2, "PHYCNT2"), 337 DEFBASIC(AR_PHYCNTMASK2, "PHYCMSK2"), 338 339 DEFVOID(AR_PHYCNT1, "PHYCNT1"), 340 DEFVOID(AR_PHYCNTMASK1, "PHYCNTMASK1"), 341 DEFVOID(AR_PHYCNT2, "PHYCNT2"), 342 DEFVOID(AR_PHYCNTMASK2, "PHYCNTMASK2"), 343 344 DEFVOID(AR_PHY_TEST, "PHY_TEST"), 345 DEFVOID(AR_PHY_TURBO, "PHY_TURBO"), 346 DEFVOID(AR_PHY_TESTCTRL, "PHY_TESTCTRL"), 347 DEFVOID(AR_PHY_TIMING3, "PHY_TIMING3"), 348 DEFVOID(AR_PHY_CHIP_ID, "PHY_CHIP_ID"), 349 DEFVOIDfmt(AR_PHY_ACTIVE, "PHY_ACTIVE", "\20\1ENA"), 350 DEFVOID(AR_PHY_TX_CTL, "PHY_TX_CTL"), 351 DEFVOID(AR_PHY_ADC_CTL, "PHY_ADC_CTL"), 352 DEFVOID(AR_PHY_BB_XP_PA_CTL,"PHY_BB_XP_PA_CTL"), 353 DEFVOID(AR_PHY_TSTDAC_CONST,"PHY_TSTDAC_CONST"), 354 DEFVOID(AR_PHY_SETTLING, "PHY_SETTLING"), 355 DEFVOID(AR_PHY_RXGAIN, "PHY_RXGAIN"), 356 DEFVOID(AR_PHY_DESIRED_SZ, "PHY_DESIRED_SZ"), 357 DEFVOID(AR_PHY_FIND_SIG, "PHY_FIND_SIG"), 358 DEFVOID(AR_PHY_AGC_CTL1, "PHY_AGC_CTL1"), 359 DEFVOIDfmt(AR_PHY_AGC_CONTROL, "PHY_AGC_CONTROL", 360 "\20\1CAL\2NF\16ENA_NF\22NO_UPDATE_NF"), 361 DEFVOIDfmt(AR_PHY_SFCORR_LOW, "PHY_SFCORR_LOW", 362 "\20\1USE_SELF_CORR_LOW"), 363 DEFVOID(AR_PHY_SFCORR, "PHY_SFCORR"), 364 DEFVOID(AR_PHY_SLEEP_CTR_CONTROL, "PHY_SLEEP_CTR_CONTROL"), 365 DEFVOID(AR_PHY_SLEEP_CTR_LIMIT, "PHY_SLEEP_CTR_LIMIT"), 366 DEFVOID(AR_PHY_SLEEP_SCAL, "PHY_SLEEP_SCAL"), 367 DEFVOID(AR_PHY_BIN_MASK_1, "PHY_BIN_MASK_1"), 368 DEFVOID(AR_PHY_BIN_MASK_2, "PHY_BIN_MASK_2"), 369 DEFVOID(AR_PHY_BIN_MASK_3, "PHY_BIN_MASK_3"), 370 DEFVOID(AR_PHY_MASK_CTL, "PHY_MASK_CTL"), 371 DEFVOID(AR_PHY_PLL_CTL, "PHY_PLL_CTL"), 372 DEFVOID(AR_PHY_RX_DELAY, "PHY_RX_DELAY"), 373 DEFVOID(AR_PHY_TIMING_CTRL4,"PHY_TIMING_CTRL4"), 374 DEFVOID(AR_PHY_TIMING5, "PHY_TIMING5"), 375 DEFVOID(AR_PHY_PAPD_PROBE, "PHY_PAPD_PROBE"), 376 DEFVOID(AR_PHY_POWER_TX_RATE1,"PHY_POWER_TX_RATE1"), 377 DEFVOID(AR_PHY_POWER_TX_RATE2,"PHY_POWER_TX_RATE2"), 378 DEFVOID(AR_PHY_POWER_TX_RATE_MAX, "PHY_POWER_TX_RATE_MAX"), 379 DEFVOID(AR_PHY_FRAME_CTL, "PHY_FRAME_CTL"), 380 DEFVOID(AR_PHY_TXPWRADJ, "PHY_TXPWRADJ"), 381 DEFVOID(AR_PHY_RADAR_0, "PHY_RADAR_0"), 382 DEFVOID(AR_PHY_SIGMA_DELTA, "PHY_SIGMA_DELTA"), 383 DEFVOID(AR_PHY_RESTART, "PHY_RESTART"), 384 DEFVOID(AR_PHY_RFBUS_REQ, "PHY_RFBUS_REQ"), 385 DEFVOID(AR_PHY_TIMING7, "PHY_TIMING7"), 386 DEFVOID(AR_PHY_TIMING8, "PHY_TIMING8"), 387 DEFVOID(AR_PHY_BIN_MASK2_1, "PHY_BIN_MASK2_1"), 388 DEFVOID(AR_PHY_BIN_MASK2_2, "PHY_BIN_MASK2_2"), 389 DEFVOID(AR_PHY_BIN_MASK2_3, "PHY_BIN_MASK2_3"), 390 DEFVOID(AR_PHY_BIN_MASK2_4, "PHY_BIN_MASK2_4"), 391 DEFVOID(AR_PHY_TIMING9, "PHY_TIMING9"), 392 DEFVOID(AR_PHY_TIMING10, "PHY_TIMING10"), 393 DEFVOID(AR_PHY_TIMING11, "PHY_TIMING11"), 394 DEFVOID(AR_PHY_HEAVY_CLIP_ENABLE, "PHY_HEAVY_CLIP_ENABLE"), 395 DEFVOID(AR_PHY_M_SLEEP, "PHY_M_SLEEP"), 396 DEFVOID(AR_PHY_REFCLKDLY, "PHY_REFCLKDLY"), 397 DEFVOID(AR_PHY_REFCLKPD, "PHY_REFCLKPD"), 398 DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_I, "PHY_IQCAL_RES_PWR_MEAS_I"), 399 DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_Q, "PHY_IQCAL_RES_PWR_MEAS_Q"), 400 DEFVOID(AR_PHY_IQCAL_RES_IQ_CORR_MEAS, "PHY_IQCAL_RES_IQ_CORR_MEAS"), 401 DEFVOID(AR_PHY_CURRENT_RSSI,"PHY_CURRENT_RSSI"), 402 DEFVOID(AR_PHY_RFBUS_GNT, "PHY_RFBUS_GNT"), 403 DEFVOIDfmt(AR_PHY_MODE, "PHY_MODE", 404 "\20\1CCK\2RF2GHZ\3DYNAMIC\4AR5112\5HALF\6QUARTER"), 405 DEFVOID(AR_PHY_CCK_TX_CTRL, "PHY_CCK_TX_CTRL"), 406 DEFVOID(AR_PHY_CCK_DETECT, "PHY_CCK_DETECT"), 407 DEFVOID(AR_PHY_GAIN_2GHZ, "PHY_GAIN_2GHZ"), 408 DEFVOID(AR_PHY_CCK_RXCTRL4, "PHY_CCK_RXCTRL4"), 409 DEFVOID(AR_PHY_DAG_CTRLCCK, "PHY_DAG_CTRLCCK"), 410 DEFVOID(AR_PHY_DAG_CTRLCCK, "PHY_DAG_CTRLCCK"), 411 DEFVOID(AR_PHY_POWER_TX_RATE3,"PHY_POWER_TX_RATE3"), 412 DEFVOID(AR_PHY_POWER_TX_RATE4,"PHY_POWER_TX_RATE4"), 413 DEFVOID(AR_PHY_FAST_ADC, "PHY_FAST_ADC"), 414 DEFVOID(AR_PHY_BLUETOOTH, "PHY_BLUETOOTH"), 415 DEFVOID(AR_PHY_TPCRG1, "PHY_TPCRG1"), 416 DEFVOID(AR_PHY_TPCRG5, "PHY_TPCRG5"), 417 418 /* XXX { AR_RATE_DURATION(0), AR_RATE_DURATION(0x20) }, */ 419 }; 420 421 static __constructor void 422 ar5212_ctor(void) 423 { 424 register_regs(ar5212regs, N(ar5212regs), MAC5212, PHYANY); 425 register_keycache(128, MAC5212, PHYANY); 426 427 register_range(0x9800, 0x987c, DUMP_BASEBAND, MAC5212, PHYANY); 428 register_range(0x9900, 0x995c, DUMP_BASEBAND, MAC5212, PHYANY); 429 register_range(0x9c00, 0x9c1c, DUMP_BASEBAND, MAC5212, PHYANY); 430 register_range(0xa180, 0xa238, DUMP_BASEBAND, MAC5212, PHYANY); 431 register_range(0xa258, 0xa26c, DUMP_BASEBAND, 432 SREV(7,8), SREV(15,15), PHYANY); 433 } 434