1.\" Copyright (c) 1999 Chris Costello 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD: src/usr.sbin/memcontrol/memcontrol.8,v 1.3.2.5 2003/03/12 22:08:15 trhodes Exp $ 26.\" $DragonFly: src/usr.sbin/memcontrol/memcontrol.8,v 1.2 2003/06/17 04:29:57 dillon Exp $ 27.\" 28.Dd September 28, 1999 29.Dt MEMCONTROL 8 30.Os 31.Sh NAME 32.Nm memcontrol 33.Nd "control system cache behaviour with respect to memory" 34.Sh SYNOPSIS 35.Nm 36.Cm list 37.Op Fl a 38.Nm 39.Cm set 40.Fl b Ar base 41.Fl l Ar length 42.Fl o Ar owner 43.Ar attribute 44.Nm 45.Cm clear 46.Fl o Ar owner 47.Nm 48.Cm clear 49.Fl b Ar base 50.Fl l Ar length 51.Sh DESCRIPTION 52A number of supported system architectures allow the behaviour of the CPU 53cache to be programmed to behave differently depending on the region being 54written. 55.Pp 56The 57.Nm 58utility 59provides an interface to this facility, allowing CPU cache behavior to 60be altered for ranges of system physical memory. 61.Pp 62These ranges are typically power-of-2 aligned and sized, however the specific 63rules governing their layout vary between architectures. 64The 65.Nm 66utility does not attempt to enforce these rules, however the system will 67reject any attempt to set an illegal combination. 68.Bl -tag -width ".Cm clear" 69.It Cm list 70List range slots. 71.Bl -tag -width indent 72.It Fl a 73List all range slots, even those that are inactive. 74.El 75.It Cm set 76Set memory range attributes. 77.Bl -tag -width indent 78.It Fl b Ar base 79Memory range base address. 80.It Fl l Ar length 81Length of memory range in bytes, power of 2. 82.It Fl o Ar owner 83Text identifier for this setting (7 char max). 84.It Ar attribute 85Attributes applied to this range; combinations of 86.Cm force , uncacheable , write-combine , write-through , write-back , 87and 88.Cm write-protect . 89.El 90.It Cm clear 91Clear memory range attributes. 92Ranges may be cleared by owner or by 93base/length combination. 94.Pp 95To clear based on ownership: 96.Bl -tag -width indent 97.It Fl o Ar owner 98All ranges with this owner will be cleared. 99.El 100.Pp 101To clear based on the base/length combination: 102.Bl -tag -width indent 103.It Fl b Ar base 104Memory range base address. 105.It Fl l Ar length 106Length of memory range in bytes, power of 2. 107.El 108.Pp 109Base and length must exactly match an existing range. 110.El 111.Sh SEE ALSO 112.Xr mem 4 113