1 /* 2 * Single-precision vector 10^x function. 3 * 4 * Copyright (c) 2023, Arm Limited. 5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception 6 */ 7 8 #include "mathlib.h" 9 #include "v_math.h" 10 #include "pl_sig.h" 11 #include "pl_test.h" 12 #include "poly_advsimd_f32.h" 13 14 #define ScaleBound 192.0f 15 16 static const struct data 17 { 18 float32x4_t poly[5]; 19 float32x4_t log10_2_and_inv, shift; 20 21 #if !WANT_SIMD_EXCEPT 22 float32x4_t scale_thresh; 23 #endif 24 } data = { 25 /* Coefficients generated using Remez algorithm with minimisation of relative 26 error. 27 rel error: 0x1.89dafa3p-24 28 abs error: 0x1.167d55p-23 in [-log10(2)/2, log10(2)/2] 29 maxerr: 1.85943 +0.5 ulp. */ 30 .poly = { V4 (0x1.26bb16p+1f), V4 (0x1.5350d2p+1f), V4 (0x1.04744ap+1f), 31 V4 (0x1.2d8176p+0f), V4 (0x1.12b41ap-1f) }, 32 .shift = V4 (0x1.8p23f), 33 34 /* Stores constants 1/log10(2), log10(2)_high, log10(2)_low, 0. */ 35 .log10_2_and_inv = { 0x1.a934fp+1, 0x1.344136p-2, -0x1.ec10cp-27, 0 }, 36 #if !WANT_SIMD_EXCEPT 37 .scale_thresh = V4 (ScaleBound) 38 #endif 39 }; 40 41 #define ExponentBias v_u32 (0x3f800000) 42 43 #if WANT_SIMD_EXCEPT 44 45 # define SpecialBound 38.0f /* rint(log10(2^127)). */ 46 # define TinyBound v_u32 (0x20000000) /* asuint (0x1p-63). */ 47 # define BigBound v_u32 (0x42180000) /* asuint (SpecialBound). */ 48 # define Thres v_u32 (0x22180000) /* BigBound - TinyBound. */ 49 50 static float32x4_t VPCS_ATTR NOINLINE 51 special_case (float32x4_t x, float32x4_t y, uint32x4_t cmp) 52 { 53 /* If fenv exceptions are to be triggered correctly, fall back to the scalar 54 routine to special lanes. */ 55 return v_call_f32 (exp10f, x, y, cmp); 56 } 57 58 #else 59 60 # define SpecialBound 126.0f /* rint (log2 (2^127 / (1 + sqrt (2)))). */ 61 # define SpecialOffset v_u32 (0x82000000) 62 # define SpecialBias v_u32 (0x7f000000) 63 64 static float32x4_t VPCS_ATTR NOINLINE 65 special_case (float32x4_t poly, float32x4_t n, uint32x4_t e, uint32x4_t cmp1, 66 float32x4_t scale, const struct data *d) 67 { 68 /* 2^n may overflow, break it up into s1*s2. */ 69 uint32x4_t b = vandq_u32 (vclezq_f32 (n), SpecialOffset); 70 float32x4_t s1 = vreinterpretq_f32_u32 (vaddq_u32 (b, SpecialBias)); 71 float32x4_t s2 = vreinterpretq_f32_u32 (vsubq_u32 (e, b)); 72 uint32x4_t cmp2 = vcagtq_f32 (n, d->scale_thresh); 73 float32x4_t r2 = vmulq_f32 (s1, s1); 74 float32x4_t r1 = vmulq_f32 (vfmaq_f32 (s2, poly, s2), s1); 75 /* Similar to r1 but avoids double rounding in the subnormal range. */ 76 float32x4_t r0 = vfmaq_f32 (scale, poly, scale); 77 float32x4_t r = vbslq_f32 (cmp1, r1, r0); 78 return vbslq_f32 (cmp2, r2, r); 79 } 80 81 #endif 82 83 /* Fast vector implementation of single-precision exp10. 84 Algorithm is accurate to 2.36 ULP. 85 _ZGVnN4v_exp10f(0x1.be2b36p+1) got 0x1.7e79c4p+11 86 want 0x1.7e79cp+11. */ 87 float32x4_t VPCS_ATTR V_NAME_F1 (exp10) (float32x4_t x) 88 { 89 const struct data *d = ptr_barrier (&data); 90 #if WANT_SIMD_EXCEPT 91 /* asuint(x) - TinyBound >= BigBound - TinyBound. */ 92 uint32x4_t cmp = vcgeq_u32 ( 93 vsubq_u32 (vreinterpretq_u32_f32 (vabsq_f32 (x)), TinyBound), Thres); 94 float32x4_t xm = x; 95 /* If any lanes are special, mask them with 1 and retain a copy of x to allow 96 special case handler to fix special lanes later. This is only necessary if 97 fenv exceptions are to be triggered correctly. */ 98 if (unlikely (v_any_u32 (cmp))) 99 x = v_zerofy_f32 (x, cmp); 100 #endif 101 102 /* exp10(x) = 2^n * 10^r = 2^n * (1 + poly (r)), 103 with poly(r) in [1/sqrt(2), sqrt(2)] and 104 x = r + n * log10 (2), with r in [-log10(2)/2, log10(2)/2]. */ 105 float32x4_t z = vfmaq_laneq_f32 (d->shift, x, d->log10_2_and_inv, 0); 106 float32x4_t n = vsubq_f32 (z, d->shift); 107 float32x4_t r = vfmsq_laneq_f32 (x, n, d->log10_2_and_inv, 1); 108 r = vfmsq_laneq_f32 (r, n, d->log10_2_and_inv, 2); 109 uint32x4_t e = vshlq_n_u32 (vreinterpretq_u32_f32 (z), 23); 110 111 float32x4_t scale = vreinterpretq_f32_u32 (vaddq_u32 (e, ExponentBias)); 112 113 #if !WANT_SIMD_EXCEPT 114 uint32x4_t cmp = vcagtq_f32 (n, v_f32 (SpecialBound)); 115 #endif 116 117 float32x4_t r2 = vmulq_f32 (r, r); 118 float32x4_t poly 119 = vfmaq_f32 (vmulq_f32 (r, d->poly[0]), 120 v_pairwise_poly_3_f32 (r, r2, d->poly + 1), r2); 121 122 if (unlikely (v_any_u32 (cmp))) 123 #if WANT_SIMD_EXCEPT 124 return special_case (xm, vfmaq_f32 (scale, poly, scale), cmp); 125 #else 126 return special_case (poly, n, e, cmp, scale, d); 127 #endif 128 129 return vfmaq_f32 (scale, poly, scale); 130 } 131 132 PL_SIG (S, F, 1, exp10, -9.9, 9.9) 133 PL_SIG (V, F, 1, exp10, -9.9, 9.9) 134 PL_TEST_ULP (V_NAME_F1 (exp10), 1.86) 135 PL_TEST_EXPECT_FENV (V_NAME_F1 (exp10), WANT_SIMD_EXCEPT) 136 PL_TEST_SYM_INTERVAL (V_NAME_F1 (exp10), 0, SpecialBound, 5000) 137 PL_TEST_SYM_INTERVAL (V_NAME_F1 (exp10), SpecialBound, ScaleBound, 5000) 138 PL_TEST_SYM_INTERVAL (V_NAME_F1 (exp10), ScaleBound, inf, 10000) 139