1//===--- BuiltinsPTX.def - PTX Builtin function database ----*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the PTX-specific builtin function database. Users of 10// this file must define the BUILTIN macro to make use of this information. 11// 12//===----------------------------------------------------------------------===// 13 14// The format of this database matches clang/Basic/Builtins.def. 15 16#if defined(BUILTIN) && !defined(TARGET_BUILTIN) 17# define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS) 18#endif 19 20#pragma push_macro("SM_53") 21#pragma push_macro("SM_70") 22#pragma push_macro("SM_72") 23#pragma push_macro("SM_75") 24#pragma push_macro("SM_80") 25#pragma push_macro("SM_86") 26#define SM_86 "sm_86" 27#define SM_80 "sm_80|" SM_86 28#define SM_75 "sm_75|" SM_80 29#define SM_72 "sm_72|" SM_75 30#define SM_70 "sm_70|" SM_72 31 32#pragma push_macro("SM_60") 33#define SM_60 "sm_60|sm_61|sm_62|" SM_70 34#define SM_53 "sm_53|" SM_60 35 36#pragma push_macro("PTX42") 37#pragma push_macro("PTX60") 38#pragma push_macro("PTX61") 39#pragma push_macro("PTX63") 40#pragma push_macro("PTX64") 41#pragma push_macro("PTX65") 42#pragma push_macro("PTX70") 43#pragma push_macro("PTX71") 44#pragma push_macro("PTX72") 45#pragma push_macro("PTX73") 46#pragma push_macro("PTX74") 47#pragma push_macro("PTX75") 48#define PTX75 "ptx75" 49#define PTX74 "ptx74|" PTX75 50#define PTX73 "ptx73|" PTX74 51#define PTX72 "ptx72|" PTX73 52#define PTX71 "ptx71|" PTX72 53#define PTX70 "ptx70|" PTX71 54#define PTX65 "ptx65|" PTX70 55#define PTX64 "ptx64|" PTX65 56#define PTX63 "ptx63|" PTX64 57#define PTX61 "ptx61|" PTX63 58#define PTX60 "ptx60|" PTX61 59#define PTX42 "ptx42|" PTX60 60 61#pragma push_macro("AND") 62#define AND(a, b) "(" a "),(" b ")" 63 64// Special Registers 65 66BUILTIN(__nvvm_read_ptx_sreg_tid_x, "i", "nc") 67BUILTIN(__nvvm_read_ptx_sreg_tid_y, "i", "nc") 68BUILTIN(__nvvm_read_ptx_sreg_tid_z, "i", "nc") 69BUILTIN(__nvvm_read_ptx_sreg_tid_w, "i", "nc") 70 71BUILTIN(__nvvm_read_ptx_sreg_ntid_x, "i", "nc") 72BUILTIN(__nvvm_read_ptx_sreg_ntid_y, "i", "nc") 73BUILTIN(__nvvm_read_ptx_sreg_ntid_z, "i", "nc") 74BUILTIN(__nvvm_read_ptx_sreg_ntid_w, "i", "nc") 75 76BUILTIN(__nvvm_read_ptx_sreg_ctaid_x, "i", "nc") 77BUILTIN(__nvvm_read_ptx_sreg_ctaid_y, "i", "nc") 78BUILTIN(__nvvm_read_ptx_sreg_ctaid_z, "i", "nc") 79BUILTIN(__nvvm_read_ptx_sreg_ctaid_w, "i", "nc") 80 81BUILTIN(__nvvm_read_ptx_sreg_nctaid_x, "i", "nc") 82BUILTIN(__nvvm_read_ptx_sreg_nctaid_y, "i", "nc") 83BUILTIN(__nvvm_read_ptx_sreg_nctaid_z, "i", "nc") 84BUILTIN(__nvvm_read_ptx_sreg_nctaid_w, "i", "nc") 85 86BUILTIN(__nvvm_read_ptx_sreg_laneid, "i", "nc") 87BUILTIN(__nvvm_read_ptx_sreg_warpid, "i", "nc") 88BUILTIN(__nvvm_read_ptx_sreg_nwarpid, "i", "nc") 89 90BUILTIN(__nvvm_read_ptx_sreg_smid, "i", "nc") 91BUILTIN(__nvvm_read_ptx_sreg_nsmid, "i", "nc") 92BUILTIN(__nvvm_read_ptx_sreg_gridid, "i", "nc") 93 94BUILTIN(__nvvm_read_ptx_sreg_lanemask_eq, "i", "nc") 95BUILTIN(__nvvm_read_ptx_sreg_lanemask_le, "i", "nc") 96BUILTIN(__nvvm_read_ptx_sreg_lanemask_lt, "i", "nc") 97BUILTIN(__nvvm_read_ptx_sreg_lanemask_ge, "i", "nc") 98BUILTIN(__nvvm_read_ptx_sreg_lanemask_gt, "i", "nc") 99 100BUILTIN(__nvvm_read_ptx_sreg_clock, "i", "n") 101BUILTIN(__nvvm_read_ptx_sreg_clock64, "LLi", "n") 102 103BUILTIN(__nvvm_read_ptx_sreg_pm0, "i", "n") 104BUILTIN(__nvvm_read_ptx_sreg_pm1, "i", "n") 105BUILTIN(__nvvm_read_ptx_sreg_pm2, "i", "n") 106BUILTIN(__nvvm_read_ptx_sreg_pm3, "i", "n") 107 108// MISC 109 110BUILTIN(__nvvm_prmt, "UiUiUiUi", "") 111 112// Min Max 113 114TARGET_BUILTIN(__nvvm_fmin_f16, "hhh", "", AND(SM_80, PTX70)) 115TARGET_BUILTIN(__nvvm_fmin_ftz_f16, "hhh", "", AND(SM_80, PTX70)) 116TARGET_BUILTIN(__nvvm_fmin_nan_f16, "hhh", "", AND(SM_80, PTX70)) 117TARGET_BUILTIN(__nvvm_fmin_ftz_nan_f16, "hhh", "", AND(SM_80, PTX70)) 118TARGET_BUILTIN(__nvvm_fmin_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72)) 119TARGET_BUILTIN(__nvvm_fmin_ftz_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72)) 120TARGET_BUILTIN(__nvvm_fmin_nan_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72)) 121TARGET_BUILTIN(__nvvm_fmin_ftz_nan_xorsign_abs_f16, "hhh", "", 122 AND(SM_86, PTX72)) 123TARGET_BUILTIN(__nvvm_fmin_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70)) 124TARGET_BUILTIN(__nvvm_fmin_ftz_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70)) 125TARGET_BUILTIN(__nvvm_fmin_nan_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70)) 126TARGET_BUILTIN(__nvvm_fmin_ftz_nan_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70)) 127TARGET_BUILTIN(__nvvm_fmin_xorsign_abs_f16x2, "V2hV2hV2h", "", 128 AND(SM_86, PTX72)) 129TARGET_BUILTIN(__nvvm_fmin_ftz_xorsign_abs_f16x2, "V2hV2hV2h", "", 130 AND(SM_86, PTX72)) 131TARGET_BUILTIN(__nvvm_fmin_nan_xorsign_abs_f16x2, "V2hV2hV2h", "", 132 AND(SM_86, PTX72)) 133TARGET_BUILTIN(__nvvm_fmin_ftz_nan_xorsign_abs_f16x2, "V2hV2hV2h", "", 134 AND(SM_86, PTX72)) 135TARGET_BUILTIN(__nvvm_fmin_bf16, "UsUsUs", "", AND(SM_80, PTX70)) 136TARGET_BUILTIN(__nvvm_fmin_nan_bf16, "UsUsUs", "", AND(SM_80, PTX70)) 137TARGET_BUILTIN(__nvvm_fmin_xorsign_abs_bf16, "UsUsUs", "", AND(SM_86, PTX72)) 138TARGET_BUILTIN(__nvvm_fmin_nan_xorsign_abs_bf16, "UsUsUs", "", 139 AND(SM_86, PTX72)) 140TARGET_BUILTIN(__nvvm_fmin_bf16x2, "ZUiZUiZUi", "", AND(SM_80, PTX70)) 141TARGET_BUILTIN(__nvvm_fmin_nan_bf16x2, "ZUiZUiZUi", "", AND(SM_80, PTX70)) 142TARGET_BUILTIN(__nvvm_fmin_xorsign_abs_bf16x2, "ZUiZUiZUi", "", 143 AND(SM_86, PTX72)) 144TARGET_BUILTIN(__nvvm_fmin_nan_xorsign_abs_bf16x2, "ZUiZUiZUi", "", 145 AND(SM_86, PTX72)) 146BUILTIN(__nvvm_fmin_f, "fff", "") 147BUILTIN(__nvvm_fmin_ftz_f, "fff", "") 148TARGET_BUILTIN(__nvvm_fmin_nan_f, "fff", "", AND(SM_80, PTX70)) 149TARGET_BUILTIN(__nvvm_fmin_ftz_nan_f, "fff", "", AND(SM_80, PTX70)) 150TARGET_BUILTIN(__nvvm_fmin_xorsign_abs_f, "fff", "", AND(SM_86, PTX72)) 151TARGET_BUILTIN(__nvvm_fmin_ftz_xorsign_abs_f, "fff", "", AND(SM_86, PTX72)) 152TARGET_BUILTIN(__nvvm_fmin_nan_xorsign_abs_f, "fff", "", AND(SM_86, PTX72)) 153TARGET_BUILTIN(__nvvm_fmin_ftz_nan_xorsign_abs_f, "fff", "", AND(SM_86, PTX72)) 154BUILTIN(__nvvm_fmin_d, "ddd", "") 155 156TARGET_BUILTIN(__nvvm_fmax_f16, "hhh", "", AND(SM_80, PTX70)) 157TARGET_BUILTIN(__nvvm_fmax_ftz_f16, "hhh", "", AND(SM_80, PTX70)) 158TARGET_BUILTIN(__nvvm_fmax_nan_f16, "hhh", "", AND(SM_80, PTX70)) 159TARGET_BUILTIN(__nvvm_fmax_ftz_nan_f16, "hhh", "", AND(SM_80, PTX70)) 160TARGET_BUILTIN(__nvvm_fmax_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72)) 161TARGET_BUILTIN(__nvvm_fmax_ftz_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72)) 162TARGET_BUILTIN(__nvvm_fmax_nan_xorsign_abs_f16, "hhh", "", AND(SM_86, PTX72)) 163TARGET_BUILTIN(__nvvm_fmax_ftz_nan_xorsign_abs_f16, "hhh", "", 164 AND(SM_86, PTX72)) 165TARGET_BUILTIN(__nvvm_fmax_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70)) 166TARGET_BUILTIN(__nvvm_fmax_ftz_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70)) 167TARGET_BUILTIN(__nvvm_fmax_nan_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70)) 168TARGET_BUILTIN(__nvvm_fmax_ftz_nan_f16x2, "V2hV2hV2h", "", AND(SM_80, PTX70)) 169TARGET_BUILTIN(__nvvm_fmax_xorsign_abs_f16x2, "V2hV2hV2h", "", 170 AND(SM_86, PTX72)) 171TARGET_BUILTIN(__nvvm_fmax_ftz_xorsign_abs_f16x2, "V2hV2hV2h", "", 172 AND(SM_86, PTX72)) 173TARGET_BUILTIN(__nvvm_fmax_nan_xorsign_abs_f16x2, "V2hV2hV2h", "", 174 AND(SM_86, PTX72)) 175TARGET_BUILTIN(__nvvm_fmax_ftz_nan_xorsign_abs_f16x2, "V2hV2hV2h", "", 176 AND(SM_86, PTX72)) 177TARGET_BUILTIN(__nvvm_fmax_bf16, "UsUsUs", "", AND(SM_80, PTX70)) 178TARGET_BUILTIN(__nvvm_fmax_nan_bf16, "UsUsUs", "", AND(SM_80, PTX70)) 179TARGET_BUILTIN(__nvvm_fmax_xorsign_abs_bf16, "UsUsUs", "", AND(SM_86, PTX72)) 180TARGET_BUILTIN(__nvvm_fmax_nan_xorsign_abs_bf16, "UsUsUs", "", 181 AND(SM_86, PTX72)) 182TARGET_BUILTIN(__nvvm_fmax_bf16x2, "ZUiZUiZUi", "", AND(SM_80, PTX70)) 183TARGET_BUILTIN(__nvvm_fmax_nan_bf16x2, "ZUiZUiZUi", "", AND(SM_80, PTX70)) 184TARGET_BUILTIN(__nvvm_fmax_xorsign_abs_bf16x2, "ZUiZUiZUi", "", 185 AND(SM_86, PTX72)) 186TARGET_BUILTIN(__nvvm_fmax_nan_xorsign_abs_bf16x2, "ZUiZUiZUi", "", 187 AND(SM_86, PTX72)) 188BUILTIN(__nvvm_fmax_f, "fff", "") 189BUILTIN(__nvvm_fmax_ftz_f, "fff", "") 190TARGET_BUILTIN(__nvvm_fmax_nan_f, "fff", "", AND(SM_80, PTX70)) 191TARGET_BUILTIN(__nvvm_fmax_ftz_nan_f, "fff", "", AND(SM_80, PTX70)) 192TARGET_BUILTIN(__nvvm_fmax_xorsign_abs_f, "fff", "", AND(SM_86, PTX72)) 193TARGET_BUILTIN(__nvvm_fmax_ftz_xorsign_abs_f, "fff", "", AND(SM_86, PTX72)) 194TARGET_BUILTIN(__nvvm_fmax_nan_xorsign_abs_f, "fff", "", AND(SM_86, PTX72)) 195TARGET_BUILTIN(__nvvm_fmax_ftz_nan_xorsign_abs_f, "fff", "", AND(SM_86, PTX72)) 196BUILTIN(__nvvm_fmax_d, "ddd", "") 197 198// Multiplication 199 200BUILTIN(__nvvm_mulhi_i, "iii", "") 201BUILTIN(__nvvm_mulhi_ui, "UiUiUi", "") 202BUILTIN(__nvvm_mulhi_ll, "LLiLLiLLi", "") 203BUILTIN(__nvvm_mulhi_ull, "ULLiULLiULLi", "") 204 205BUILTIN(__nvvm_mul_rn_ftz_f, "fff", "") 206BUILTIN(__nvvm_mul_rn_f, "fff", "") 207BUILTIN(__nvvm_mul_rz_ftz_f, "fff", "") 208BUILTIN(__nvvm_mul_rz_f, "fff", "") 209BUILTIN(__nvvm_mul_rm_ftz_f, "fff", "") 210BUILTIN(__nvvm_mul_rm_f, "fff", "") 211BUILTIN(__nvvm_mul_rp_ftz_f, "fff", "") 212BUILTIN(__nvvm_mul_rp_f, "fff", "") 213 214BUILTIN(__nvvm_mul_rn_d, "ddd", "") 215BUILTIN(__nvvm_mul_rz_d, "ddd", "") 216BUILTIN(__nvvm_mul_rm_d, "ddd", "") 217BUILTIN(__nvvm_mul_rp_d, "ddd", "") 218 219BUILTIN(__nvvm_mul24_i, "iii", "") 220BUILTIN(__nvvm_mul24_ui, "UiUiUi", "") 221 222// Div 223 224BUILTIN(__nvvm_div_approx_ftz_f, "fff", "") 225BUILTIN(__nvvm_div_approx_f, "fff", "") 226 227BUILTIN(__nvvm_div_rn_ftz_f, "fff", "") 228BUILTIN(__nvvm_div_rn_f, "fff", "") 229BUILTIN(__nvvm_div_rz_ftz_f, "fff", "") 230BUILTIN(__nvvm_div_rz_f, "fff", "") 231BUILTIN(__nvvm_div_rm_ftz_f, "fff", "") 232BUILTIN(__nvvm_div_rm_f, "fff", "") 233BUILTIN(__nvvm_div_rp_ftz_f, "fff", "") 234BUILTIN(__nvvm_div_rp_f, "fff", "") 235 236BUILTIN(__nvvm_div_rn_d, "ddd", "") 237BUILTIN(__nvvm_div_rz_d, "ddd", "") 238BUILTIN(__nvvm_div_rm_d, "ddd", "") 239BUILTIN(__nvvm_div_rp_d, "ddd", "") 240 241// Sad 242 243BUILTIN(__nvvm_sad_i, "iiii", "") 244BUILTIN(__nvvm_sad_ui, "UiUiUiUi", "") 245 246// Floor, Ceil 247 248BUILTIN(__nvvm_floor_ftz_f, "ff", "") 249BUILTIN(__nvvm_floor_f, "ff", "") 250BUILTIN(__nvvm_floor_d, "dd", "") 251 252BUILTIN(__nvvm_ceil_ftz_f, "ff", "") 253BUILTIN(__nvvm_ceil_f, "ff", "") 254BUILTIN(__nvvm_ceil_d, "dd", "") 255 256// Abs 257 258BUILTIN(__nvvm_fabs_ftz_f, "ff", "") 259BUILTIN(__nvvm_fabs_f, "ff", "") 260BUILTIN(__nvvm_fabs_d, "dd", "") 261 262// Round 263 264BUILTIN(__nvvm_round_ftz_f, "ff", "") 265BUILTIN(__nvvm_round_f, "ff", "") 266BUILTIN(__nvvm_round_d, "dd", "") 267 268// Trunc 269 270BUILTIN(__nvvm_trunc_ftz_f, "ff", "") 271BUILTIN(__nvvm_trunc_f, "ff", "") 272BUILTIN(__nvvm_trunc_d, "dd", "") 273 274// Saturate 275 276BUILTIN(__nvvm_saturate_ftz_f, "ff", "") 277BUILTIN(__nvvm_saturate_f, "ff", "") 278BUILTIN(__nvvm_saturate_d, "dd", "") 279 280// Exp2, Log2 281 282BUILTIN(__nvvm_ex2_approx_ftz_f, "ff", "") 283BUILTIN(__nvvm_ex2_approx_f, "ff", "") 284BUILTIN(__nvvm_ex2_approx_d, "dd", "") 285TARGET_BUILTIN(__nvvm_ex2_approx_f16, "hh", "", AND(SM_75, PTX70)) 286TARGET_BUILTIN(__nvvm_ex2_approx_f16x2, "V2hV2h", "", AND(SM_75, PTX70)) 287 288BUILTIN(__nvvm_lg2_approx_ftz_f, "ff", "") 289BUILTIN(__nvvm_lg2_approx_f, "ff", "") 290BUILTIN(__nvvm_lg2_approx_d, "dd", "") 291 292// Sin, Cos 293 294BUILTIN(__nvvm_sin_approx_ftz_f, "ff", "") 295BUILTIN(__nvvm_sin_approx_f, "ff", "") 296 297BUILTIN(__nvvm_cos_approx_ftz_f, "ff", "") 298BUILTIN(__nvvm_cos_approx_f, "ff", "") 299 300// Fma 301 302TARGET_BUILTIN(__nvvm_fma_rn_f16, "hhhh", "", AND(SM_53, PTX42)) 303TARGET_BUILTIN(__nvvm_fma_rn_ftz_f16, "hhhh", "", AND(SM_53, PTX42)) 304TARGET_BUILTIN(__nvvm_fma_rn_sat_f16, "hhhh", "", AND(SM_53, PTX42)) 305TARGET_BUILTIN(__nvvm_fma_rn_ftz_sat_f16, "hhhh", "", AND(SM_53, PTX42)) 306TARGET_BUILTIN(__nvvm_fma_rn_relu_f16, "hhhh", "", AND(SM_80, PTX70)) 307TARGET_BUILTIN(__nvvm_fma_rn_ftz_relu_f16, "hhhh", "", AND(SM_80, PTX70)) 308TARGET_BUILTIN(__nvvm_fma_rn_f16x2, "V2hV2hV2hV2h", "", AND(SM_53, PTX42)) 309TARGET_BUILTIN(__nvvm_fma_rn_ftz_f16x2, "V2hV2hV2hV2h", "", AND(SM_53, PTX42)) 310TARGET_BUILTIN(__nvvm_fma_rn_sat_f16x2, "V2hV2hV2hV2h", "", AND(SM_53, PTX42)) 311TARGET_BUILTIN(__nvvm_fma_rn_ftz_sat_f16x2, "V2hV2hV2hV2h", "", AND(SM_53, PTX42)) 312TARGET_BUILTIN(__nvvm_fma_rn_relu_f16x2, "V2hV2hV2hV2h", "", AND(SM_80, PTX70)) 313TARGET_BUILTIN(__nvvm_fma_rn_ftz_relu_f16x2, "V2hV2hV2hV2h", "", AND(SM_80, PTX70)) 314TARGET_BUILTIN(__nvvm_fma_rn_bf16, "UsUsUsUs", "", AND(SM_80, PTX70)) 315TARGET_BUILTIN(__nvvm_fma_rn_relu_bf16, "UsUsUsUs", "", AND(SM_80, PTX70)) 316TARGET_BUILTIN(__nvvm_fma_rn_bf16x2, "ZUiZUiZUiZUi", "", AND(SM_80, PTX70)) 317TARGET_BUILTIN(__nvvm_fma_rn_relu_bf16x2, "ZUiZUiZUiZUi", "", AND(SM_80, PTX70)) 318BUILTIN(__nvvm_fma_rn_ftz_f, "ffff", "") 319BUILTIN(__nvvm_fma_rn_f, "ffff", "") 320BUILTIN(__nvvm_fma_rz_ftz_f, "ffff", "") 321BUILTIN(__nvvm_fma_rz_f, "ffff", "") 322BUILTIN(__nvvm_fma_rm_ftz_f, "ffff", "") 323BUILTIN(__nvvm_fma_rm_f, "ffff", "") 324BUILTIN(__nvvm_fma_rp_ftz_f, "ffff", "") 325BUILTIN(__nvvm_fma_rp_f, "ffff", "") 326BUILTIN(__nvvm_fma_rn_d, "dddd", "") 327BUILTIN(__nvvm_fma_rz_d, "dddd", "") 328BUILTIN(__nvvm_fma_rm_d, "dddd", "") 329BUILTIN(__nvvm_fma_rp_d, "dddd", "") 330 331// Rcp 332 333BUILTIN(__nvvm_rcp_rn_ftz_f, "ff", "") 334BUILTIN(__nvvm_rcp_rn_f, "ff", "") 335BUILTIN(__nvvm_rcp_rz_ftz_f, "ff", "") 336BUILTIN(__nvvm_rcp_rz_f, "ff", "") 337BUILTIN(__nvvm_rcp_rm_ftz_f, "ff", "") 338BUILTIN(__nvvm_rcp_rm_f, "ff", "") 339BUILTIN(__nvvm_rcp_rp_ftz_f, "ff", "") 340BUILTIN(__nvvm_rcp_rp_f, "ff", "") 341 342BUILTIN(__nvvm_rcp_rn_d, "dd", "") 343BUILTIN(__nvvm_rcp_rz_d, "dd", "") 344BUILTIN(__nvvm_rcp_rm_d, "dd", "") 345BUILTIN(__nvvm_rcp_rp_d, "dd", "") 346 347BUILTIN(__nvvm_rcp_approx_ftz_f, "ff", "") 348BUILTIN(__nvvm_rcp_approx_ftz_d, "dd", "") 349 350// Sqrt 351 352BUILTIN(__nvvm_sqrt_rn_ftz_f, "ff", "") 353BUILTIN(__nvvm_sqrt_rn_f, "ff", "") 354BUILTIN(__nvvm_sqrt_rz_ftz_f, "ff", "") 355BUILTIN(__nvvm_sqrt_rz_f, "ff", "") 356BUILTIN(__nvvm_sqrt_rm_ftz_f, "ff", "") 357BUILTIN(__nvvm_sqrt_rm_f, "ff", "") 358BUILTIN(__nvvm_sqrt_rp_ftz_f, "ff", "") 359BUILTIN(__nvvm_sqrt_rp_f, "ff", "") 360BUILTIN(__nvvm_sqrt_approx_ftz_f, "ff", "") 361BUILTIN(__nvvm_sqrt_approx_f, "ff", "") 362 363BUILTIN(__nvvm_sqrt_rn_d, "dd", "") 364BUILTIN(__nvvm_sqrt_rz_d, "dd", "") 365BUILTIN(__nvvm_sqrt_rm_d, "dd", "") 366BUILTIN(__nvvm_sqrt_rp_d, "dd", "") 367 368// Rsqrt 369 370BUILTIN(__nvvm_rsqrt_approx_ftz_f, "ff", "") 371BUILTIN(__nvvm_rsqrt_approx_f, "ff", "") 372BUILTIN(__nvvm_rsqrt_approx_d, "dd", "") 373 374// Add 375 376BUILTIN(__nvvm_add_rn_ftz_f, "fff", "") 377BUILTIN(__nvvm_add_rn_f, "fff", "") 378BUILTIN(__nvvm_add_rz_ftz_f, "fff", "") 379BUILTIN(__nvvm_add_rz_f, "fff", "") 380BUILTIN(__nvvm_add_rm_ftz_f, "fff", "") 381BUILTIN(__nvvm_add_rm_f, "fff", "") 382BUILTIN(__nvvm_add_rp_ftz_f, "fff", "") 383BUILTIN(__nvvm_add_rp_f, "fff", "") 384 385BUILTIN(__nvvm_add_rn_d, "ddd", "") 386BUILTIN(__nvvm_add_rz_d, "ddd", "") 387BUILTIN(__nvvm_add_rm_d, "ddd", "") 388BUILTIN(__nvvm_add_rp_d, "ddd", "") 389 390// Convert 391 392BUILTIN(__nvvm_d2f_rn_ftz, "fd", "") 393BUILTIN(__nvvm_d2f_rn, "fd", "") 394BUILTIN(__nvvm_d2f_rz_ftz, "fd", "") 395BUILTIN(__nvvm_d2f_rz, "fd", "") 396BUILTIN(__nvvm_d2f_rm_ftz, "fd", "") 397BUILTIN(__nvvm_d2f_rm, "fd", "") 398BUILTIN(__nvvm_d2f_rp_ftz, "fd", "") 399BUILTIN(__nvvm_d2f_rp, "fd", "") 400 401BUILTIN(__nvvm_d2i_rn, "id", "") 402BUILTIN(__nvvm_d2i_rz, "id", "") 403BUILTIN(__nvvm_d2i_rm, "id", "") 404BUILTIN(__nvvm_d2i_rp, "id", "") 405 406BUILTIN(__nvvm_d2ui_rn, "Uid", "") 407BUILTIN(__nvvm_d2ui_rz, "Uid", "") 408BUILTIN(__nvvm_d2ui_rm, "Uid", "") 409BUILTIN(__nvvm_d2ui_rp, "Uid", "") 410 411BUILTIN(__nvvm_i2d_rn, "di", "") 412BUILTIN(__nvvm_i2d_rz, "di", "") 413BUILTIN(__nvvm_i2d_rm, "di", "") 414BUILTIN(__nvvm_i2d_rp, "di", "") 415 416BUILTIN(__nvvm_ui2d_rn, "dUi", "") 417BUILTIN(__nvvm_ui2d_rz, "dUi", "") 418BUILTIN(__nvvm_ui2d_rm, "dUi", "") 419BUILTIN(__nvvm_ui2d_rp, "dUi", "") 420 421BUILTIN(__nvvm_f2i_rn_ftz, "if", "") 422BUILTIN(__nvvm_f2i_rn, "if", "") 423BUILTIN(__nvvm_f2i_rz_ftz, "if", "") 424BUILTIN(__nvvm_f2i_rz, "if", "") 425BUILTIN(__nvvm_f2i_rm_ftz, "if", "") 426BUILTIN(__nvvm_f2i_rm, "if", "") 427BUILTIN(__nvvm_f2i_rp_ftz, "if", "") 428BUILTIN(__nvvm_f2i_rp, "if", "") 429 430BUILTIN(__nvvm_f2ui_rn_ftz, "Uif", "") 431BUILTIN(__nvvm_f2ui_rn, "Uif", "") 432BUILTIN(__nvvm_f2ui_rz_ftz, "Uif", "") 433BUILTIN(__nvvm_f2ui_rz, "Uif", "") 434BUILTIN(__nvvm_f2ui_rm_ftz, "Uif", "") 435BUILTIN(__nvvm_f2ui_rm, "Uif", "") 436BUILTIN(__nvvm_f2ui_rp_ftz, "Uif", "") 437BUILTIN(__nvvm_f2ui_rp, "Uif", "") 438 439BUILTIN(__nvvm_i2f_rn, "fi", "") 440BUILTIN(__nvvm_i2f_rz, "fi", "") 441BUILTIN(__nvvm_i2f_rm, "fi", "") 442BUILTIN(__nvvm_i2f_rp, "fi", "") 443 444BUILTIN(__nvvm_ui2f_rn, "fUi", "") 445BUILTIN(__nvvm_ui2f_rz, "fUi", "") 446BUILTIN(__nvvm_ui2f_rm, "fUi", "") 447BUILTIN(__nvvm_ui2f_rp, "fUi", "") 448 449BUILTIN(__nvvm_lohi_i2d, "dii", "") 450 451BUILTIN(__nvvm_d2i_lo, "id", "") 452BUILTIN(__nvvm_d2i_hi, "id", "") 453 454BUILTIN(__nvvm_f2ll_rn_ftz, "LLif", "") 455BUILTIN(__nvvm_f2ll_rn, "LLif", "") 456BUILTIN(__nvvm_f2ll_rz_ftz, "LLif", "") 457BUILTIN(__nvvm_f2ll_rz, "LLif", "") 458BUILTIN(__nvvm_f2ll_rm_ftz, "LLif", "") 459BUILTIN(__nvvm_f2ll_rm, "LLif", "") 460BUILTIN(__nvvm_f2ll_rp_ftz, "LLif", "") 461BUILTIN(__nvvm_f2ll_rp, "LLif", "") 462 463BUILTIN(__nvvm_f2ull_rn_ftz, "ULLif", "") 464BUILTIN(__nvvm_f2ull_rn, "ULLif", "") 465BUILTIN(__nvvm_f2ull_rz_ftz, "ULLif", "") 466BUILTIN(__nvvm_f2ull_rz, "ULLif", "") 467BUILTIN(__nvvm_f2ull_rm_ftz, "ULLif", "") 468BUILTIN(__nvvm_f2ull_rm, "ULLif", "") 469BUILTIN(__nvvm_f2ull_rp_ftz, "ULLif", "") 470BUILTIN(__nvvm_f2ull_rp, "ULLif", "") 471 472BUILTIN(__nvvm_d2ll_rn, "LLid", "") 473BUILTIN(__nvvm_d2ll_rz, "LLid", "") 474BUILTIN(__nvvm_d2ll_rm, "LLid", "") 475BUILTIN(__nvvm_d2ll_rp, "LLid", "") 476 477BUILTIN(__nvvm_d2ull_rn, "ULLid", "") 478BUILTIN(__nvvm_d2ull_rz, "ULLid", "") 479BUILTIN(__nvvm_d2ull_rm, "ULLid", "") 480BUILTIN(__nvvm_d2ull_rp, "ULLid", "") 481 482BUILTIN(__nvvm_ll2f_rn, "fLLi", "") 483BUILTIN(__nvvm_ll2f_rz, "fLLi", "") 484BUILTIN(__nvvm_ll2f_rm, "fLLi", "") 485BUILTIN(__nvvm_ll2f_rp, "fLLi", "") 486 487BUILTIN(__nvvm_ull2f_rn, "fULLi", "") 488BUILTIN(__nvvm_ull2f_rz, "fULLi", "") 489BUILTIN(__nvvm_ull2f_rm, "fULLi", "") 490BUILTIN(__nvvm_ull2f_rp, "fULLi", "") 491 492BUILTIN(__nvvm_ll2d_rn, "dLLi", "") 493BUILTIN(__nvvm_ll2d_rz, "dLLi", "") 494BUILTIN(__nvvm_ll2d_rm, "dLLi", "") 495BUILTIN(__nvvm_ll2d_rp, "dLLi", "") 496 497BUILTIN(__nvvm_ull2d_rn, "dULLi", "") 498BUILTIN(__nvvm_ull2d_rz, "dULLi", "") 499BUILTIN(__nvvm_ull2d_rm, "dULLi", "") 500BUILTIN(__nvvm_ull2d_rp, "dULLi", "") 501 502BUILTIN(__nvvm_f2h_rn_ftz, "Usf", "") 503BUILTIN(__nvvm_f2h_rn, "Usf", "") 504 505TARGET_BUILTIN(__nvvm_ff2bf16x2_rn, "ZUiff", "", AND(SM_80,PTX70)) 506TARGET_BUILTIN(__nvvm_ff2bf16x2_rn_relu, "ZUiff", "", AND(SM_80,PTX70)) 507TARGET_BUILTIN(__nvvm_ff2bf16x2_rz, "ZUiff", "", AND(SM_80,PTX70)) 508TARGET_BUILTIN(__nvvm_ff2bf16x2_rz_relu, "ZUiff", "", AND(SM_80,PTX70)) 509 510TARGET_BUILTIN(__nvvm_ff2f16x2_rn, "V2hff", "", AND(SM_80,PTX70)) 511TARGET_BUILTIN(__nvvm_ff2f16x2_rn_relu, "V2hff", "", AND(SM_80,PTX70)) 512TARGET_BUILTIN(__nvvm_ff2f16x2_rz, "V2hff", "", AND(SM_80,PTX70)) 513TARGET_BUILTIN(__nvvm_ff2f16x2_rz_relu, "V2hff", "", AND(SM_80,PTX70)) 514 515TARGET_BUILTIN(__nvvm_f2bf16_rn, "ZUsf", "", AND(SM_80,PTX70)) 516TARGET_BUILTIN(__nvvm_f2bf16_rn_relu, "ZUsf", "", AND(SM_80,PTX70)) 517TARGET_BUILTIN(__nvvm_f2bf16_rz, "ZUsf", "", AND(SM_80,PTX70)) 518TARGET_BUILTIN(__nvvm_f2bf16_rz_relu, "ZUsf", "", AND(SM_80,PTX70)) 519 520TARGET_BUILTIN(__nvvm_f2tf32_rna, "ZUif", "", AND(SM_80,PTX70)) 521 522// Bitcast 523 524BUILTIN(__nvvm_bitcast_f2i, "if", "") 525BUILTIN(__nvvm_bitcast_i2f, "fi", "") 526 527BUILTIN(__nvvm_bitcast_ll2d, "dLLi", "") 528BUILTIN(__nvvm_bitcast_d2ll, "LLid", "") 529 530// FNS 531TARGET_BUILTIN(__nvvm_fns, "UiUiUii", "n", PTX60) 532 533// Sync 534 535BUILTIN(__syncthreads, "v", "") 536BUILTIN(__nvvm_bar0_popc, "ii", "") 537BUILTIN(__nvvm_bar0_and, "ii", "") 538BUILTIN(__nvvm_bar0_or, "ii", "") 539BUILTIN(__nvvm_bar_sync, "vi", "n") 540TARGET_BUILTIN(__nvvm_bar_warp_sync, "vUi", "n", PTX60) 541TARGET_BUILTIN(__nvvm_barrier_sync, "vUi", "n", PTX60) 542TARGET_BUILTIN(__nvvm_barrier_sync_cnt, "vUiUi", "n", PTX60) 543 544// Shuffle 545 546BUILTIN(__nvvm_shfl_down_i32, "iiii", "") 547BUILTIN(__nvvm_shfl_down_f32, "ffii", "") 548BUILTIN(__nvvm_shfl_up_i32, "iiii", "") 549BUILTIN(__nvvm_shfl_up_f32, "ffii", "") 550BUILTIN(__nvvm_shfl_bfly_i32, "iiii", "") 551BUILTIN(__nvvm_shfl_bfly_f32, "ffii", "") 552BUILTIN(__nvvm_shfl_idx_i32, "iiii", "") 553BUILTIN(__nvvm_shfl_idx_f32, "ffii", "") 554 555TARGET_BUILTIN(__nvvm_shfl_sync_down_i32, "iUiiii", "", PTX60) 556TARGET_BUILTIN(__nvvm_shfl_sync_down_f32, "fUifii", "", PTX60) 557TARGET_BUILTIN(__nvvm_shfl_sync_up_i32, "iUiiii", "", PTX60) 558TARGET_BUILTIN(__nvvm_shfl_sync_up_f32, "fUifii", "", PTX60) 559TARGET_BUILTIN(__nvvm_shfl_sync_bfly_i32, "iUiiii", "", PTX60) 560TARGET_BUILTIN(__nvvm_shfl_sync_bfly_f32, "fUifii", "", PTX60) 561TARGET_BUILTIN(__nvvm_shfl_sync_idx_i32, "iUiiii", "", PTX60) 562TARGET_BUILTIN(__nvvm_shfl_sync_idx_f32, "fUifii", "", PTX60) 563 564// Vote 565BUILTIN(__nvvm_vote_all, "bb", "") 566BUILTIN(__nvvm_vote_any, "bb", "") 567BUILTIN(__nvvm_vote_uni, "bb", "") 568BUILTIN(__nvvm_vote_ballot, "Uib", "") 569 570TARGET_BUILTIN(__nvvm_vote_all_sync, "bUib", "", PTX60) 571TARGET_BUILTIN(__nvvm_vote_any_sync, "bUib", "", PTX60) 572TARGET_BUILTIN(__nvvm_vote_uni_sync, "bUib", "", PTX60) 573TARGET_BUILTIN(__nvvm_vote_ballot_sync, "UiUib", "", PTX60) 574 575// Match 576TARGET_BUILTIN(__nvvm_match_any_sync_i32, "UiUiUi", "", AND(SM_70,PTX60)) 577TARGET_BUILTIN(__nvvm_match_any_sync_i64, "UiUiWi", "", AND(SM_70,PTX60)) 578// These return a pair {value, predicate}, which requires custom lowering. 579TARGET_BUILTIN(__nvvm_match_all_sync_i32p, "UiUiUii*", "", AND(SM_70,PTX60)) 580TARGET_BUILTIN(__nvvm_match_all_sync_i64p, "UiUiWii*", "", AND(SM_70,PTX60)) 581 582// Redux 583TARGET_BUILTIN(__nvvm_redux_sync_add, "iii", "", AND(SM_80,PTX70)) 584TARGET_BUILTIN(__nvvm_redux_sync_min, "iii", "", AND(SM_80,PTX70)) 585TARGET_BUILTIN(__nvvm_redux_sync_max, "iii", "", AND(SM_80,PTX70)) 586TARGET_BUILTIN(__nvvm_redux_sync_umin, "UiUii", "", AND(SM_80,PTX70)) 587TARGET_BUILTIN(__nvvm_redux_sync_umax, "UiUii", "", AND(SM_80,PTX70)) 588TARGET_BUILTIN(__nvvm_redux_sync_and, "iii", "", AND(SM_80,PTX70)) 589TARGET_BUILTIN(__nvvm_redux_sync_xor, "iii", "", AND(SM_80,PTX70)) 590TARGET_BUILTIN(__nvvm_redux_sync_or, "iii", "", AND(SM_80,PTX70)) 591 592// Membar 593 594BUILTIN(__nvvm_membar_cta, "v", "") 595BUILTIN(__nvvm_membar_gl, "v", "") 596BUILTIN(__nvvm_membar_sys, "v", "") 597 598// mbarrier 599 600TARGET_BUILTIN(__nvvm_mbarrier_init, "vWi*i", "", AND(SM_80,PTX70)) 601TARGET_BUILTIN(__nvvm_mbarrier_init_shared, "vWi*3i", "", AND(SM_80,PTX70)) 602 603TARGET_BUILTIN(__nvvm_mbarrier_inval, "vWi*", "", AND(SM_80,PTX70)) 604TARGET_BUILTIN(__nvvm_mbarrier_inval_shared, "vWi*3", "", AND(SM_80,PTX70)) 605 606TARGET_BUILTIN(__nvvm_mbarrier_arrive, "WiWi*", "", AND(SM_80,PTX70)) 607TARGET_BUILTIN(__nvvm_mbarrier_arrive_shared, "WiWi*3", "", AND(SM_80,PTX70)) 608TARGET_BUILTIN(__nvvm_mbarrier_arrive_noComplete, "WiWi*i", "", AND(SM_80,PTX70)) 609TARGET_BUILTIN(__nvvm_mbarrier_arrive_noComplete_shared, "WiWi*3i", "", AND(SM_80,PTX70)) 610 611TARGET_BUILTIN(__nvvm_mbarrier_arrive_drop, "WiWi*", "", AND(SM_80,PTX70)) 612TARGET_BUILTIN(__nvvm_mbarrier_arrive_drop_shared, "WiWi*3", "", AND(SM_80,PTX70)) 613TARGET_BUILTIN(__nvvm_mbarrier_arrive_drop_noComplete, "WiWi*i", "", AND(SM_80,PTX70)) 614TARGET_BUILTIN(__nvvm_mbarrier_arrive_drop_noComplete_shared, "WiWi*3i", "", AND(SM_80,PTX70)) 615 616TARGET_BUILTIN(__nvvm_mbarrier_test_wait, "bWi*Wi", "", AND(SM_80,PTX70)) 617TARGET_BUILTIN(__nvvm_mbarrier_test_wait_shared, "bWi*3Wi", "", AND(SM_80,PTX70)) 618 619TARGET_BUILTIN(__nvvm_mbarrier_pending_count, "iWi", "", AND(SM_80,PTX70)) 620 621// Memcpy, Memset 622 623BUILTIN(__nvvm_memcpy, "vUc*Uc*zi","") 624BUILTIN(__nvvm_memset, "vUc*Uczi","") 625 626// Image 627 628BUILTIN(__builtin_ptx_read_image2Dfi_, "V4fiiii", "") 629BUILTIN(__builtin_ptx_read_image2Dff_, "V4fiiff", "") 630BUILTIN(__builtin_ptx_read_image2Dii_, "V4iiiii", "") 631BUILTIN(__builtin_ptx_read_image2Dif_, "V4iiiff", "") 632 633BUILTIN(__builtin_ptx_read_image3Dfi_, "V4fiiiiii", "") 634BUILTIN(__builtin_ptx_read_image3Dff_, "V4fiiffff", "") 635BUILTIN(__builtin_ptx_read_image3Dii_, "V4iiiiiii", "") 636BUILTIN(__builtin_ptx_read_image3Dif_, "V4iiiffff", "") 637 638BUILTIN(__builtin_ptx_write_image2Df_, "viiiffff", "") 639BUILTIN(__builtin_ptx_write_image2Di_, "viiiiiii", "") 640BUILTIN(__builtin_ptx_write_image2Dui_, "viiiUiUiUiUi", "") 641BUILTIN(__builtin_ptx_get_image_depthi_, "ii", "") 642BUILTIN(__builtin_ptx_get_image_heighti_, "ii", "") 643BUILTIN(__builtin_ptx_get_image_widthi_, "ii", "") 644BUILTIN(__builtin_ptx_get_image_channel_data_typei_, "ii", "") 645BUILTIN(__builtin_ptx_get_image_channel_orderi_, "ii", "") 646 647// Atomic 648// 649// We need the atom intrinsics because 650// - they are used in converging analysis 651// - they are used in address space analysis and optimization 652// So it does not hurt to expose them as builtins. 653// 654BUILTIN(__nvvm_atom_add_gen_i, "iiD*i", "n") 655TARGET_BUILTIN(__nvvm_atom_cta_add_gen_i, "iiD*i", "n", SM_60) 656TARGET_BUILTIN(__nvvm_atom_sys_add_gen_i, "iiD*i", "n", SM_60) 657BUILTIN(__nvvm_atom_add_gen_l, "LiLiD*Li", "n") 658TARGET_BUILTIN(__nvvm_atom_cta_add_gen_l, "LiLiD*Li", "n", SM_60) 659TARGET_BUILTIN(__nvvm_atom_sys_add_gen_l, "LiLiD*Li", "n", SM_60) 660BUILTIN(__nvvm_atom_add_gen_ll, "LLiLLiD*LLi", "n") 661TARGET_BUILTIN(__nvvm_atom_cta_add_gen_ll, "LLiLLiD*LLi", "n", SM_60) 662TARGET_BUILTIN(__nvvm_atom_sys_add_gen_ll, "LLiLLiD*LLi", "n", SM_60) 663BUILTIN(__nvvm_atom_add_gen_f, "ffD*f", "n") 664TARGET_BUILTIN(__nvvm_atom_cta_add_gen_f, "ffD*f", "n", SM_60) 665TARGET_BUILTIN(__nvvm_atom_sys_add_gen_f, "ffD*f", "n", SM_60) 666TARGET_BUILTIN(__nvvm_atom_add_gen_d, "ddD*d", "n", SM_60) 667TARGET_BUILTIN(__nvvm_atom_cta_add_gen_d, "ddD*d", "n", SM_60) 668TARGET_BUILTIN(__nvvm_atom_sys_add_gen_d, "ddD*d", "n", SM_60) 669 670BUILTIN(__nvvm_atom_sub_gen_i, "iiD*i", "n") 671BUILTIN(__nvvm_atom_sub_gen_l, "LiLiD*Li", "n") 672BUILTIN(__nvvm_atom_sub_gen_ll, "LLiLLiD*LLi", "n") 673 674BUILTIN(__nvvm_atom_xchg_gen_i, "iiD*i", "n") 675TARGET_BUILTIN(__nvvm_atom_cta_xchg_gen_i, "iiD*i", "n", SM_60) 676TARGET_BUILTIN(__nvvm_atom_sys_xchg_gen_i, "iiD*i", "n", SM_60) 677BUILTIN(__nvvm_atom_xchg_gen_l, "LiLiD*Li", "n") 678TARGET_BUILTIN(__nvvm_atom_cta_xchg_gen_l, "LiLiD*Li", "n", SM_60) 679TARGET_BUILTIN(__nvvm_atom_sys_xchg_gen_l, "LiLiD*Li", "n", SM_60) 680BUILTIN(__nvvm_atom_xchg_gen_ll, "LLiLLiD*LLi", "n") 681TARGET_BUILTIN(__nvvm_atom_cta_xchg_gen_ll, "LLiLLiD*LLi", "n", SM_60) 682TARGET_BUILTIN(__nvvm_atom_sys_xchg_gen_ll, "LLiLLiD*LLi", "n", SM_60) 683 684BUILTIN(__nvvm_atom_max_gen_i, "iiD*i", "n") 685TARGET_BUILTIN(__nvvm_atom_cta_max_gen_i, "iiD*i", "n", SM_60) 686TARGET_BUILTIN(__nvvm_atom_sys_max_gen_i, "iiD*i", "n", SM_60) 687BUILTIN(__nvvm_atom_max_gen_ui, "UiUiD*Ui", "n") 688TARGET_BUILTIN(__nvvm_atom_cta_max_gen_ui, "UiUiD*Ui", "n", SM_60) 689TARGET_BUILTIN(__nvvm_atom_sys_max_gen_ui, "UiUiD*Ui", "n", SM_60) 690BUILTIN(__nvvm_atom_max_gen_l, "LiLiD*Li", "n") 691TARGET_BUILTIN(__nvvm_atom_cta_max_gen_l, "LiLiD*Li", "n", SM_60) 692TARGET_BUILTIN(__nvvm_atom_sys_max_gen_l, "LiLiD*Li", "n", SM_60) 693BUILTIN(__nvvm_atom_max_gen_ul, "ULiULiD*ULi", "n") 694TARGET_BUILTIN(__nvvm_atom_cta_max_gen_ul, "ULiULiD*ULi", "n", SM_60) 695TARGET_BUILTIN(__nvvm_atom_sys_max_gen_ul, "ULiULiD*ULi", "n", SM_60) 696BUILTIN(__nvvm_atom_max_gen_ll, "LLiLLiD*LLi", "n") 697TARGET_BUILTIN(__nvvm_atom_cta_max_gen_ll, "LLiLLiD*LLi", "n", SM_60) 698TARGET_BUILTIN(__nvvm_atom_sys_max_gen_ll, "LLiLLiD*LLi", "n", SM_60) 699BUILTIN(__nvvm_atom_max_gen_ull, "ULLiULLiD*ULLi", "n") 700TARGET_BUILTIN(__nvvm_atom_cta_max_gen_ull, "ULLiULLiD*ULLi", "n", SM_60) 701TARGET_BUILTIN(__nvvm_atom_sys_max_gen_ull, "ULLiULLiD*ULLi", "n", SM_60) 702 703BUILTIN(__nvvm_atom_min_gen_i, "iiD*i", "n") 704TARGET_BUILTIN(__nvvm_atom_cta_min_gen_i, "iiD*i", "n", SM_60) 705TARGET_BUILTIN(__nvvm_atom_sys_min_gen_i, "iiD*i", "n", SM_60) 706BUILTIN(__nvvm_atom_min_gen_ui, "UiUiD*Ui", "n") 707TARGET_BUILTIN(__nvvm_atom_cta_min_gen_ui, "UiUiD*Ui", "n", SM_60) 708TARGET_BUILTIN(__nvvm_atom_sys_min_gen_ui, "UiUiD*Ui", "n", SM_60) 709BUILTIN(__nvvm_atom_min_gen_l, "LiLiD*Li", "n") 710TARGET_BUILTIN(__nvvm_atom_cta_min_gen_l, "LiLiD*Li", "n", SM_60) 711TARGET_BUILTIN(__nvvm_atom_sys_min_gen_l, "LiLiD*Li", "n", SM_60) 712BUILTIN(__nvvm_atom_min_gen_ul, "ULiULiD*ULi", "n") 713TARGET_BUILTIN(__nvvm_atom_cta_min_gen_ul, "ULiULiD*ULi", "n", SM_60) 714TARGET_BUILTIN(__nvvm_atom_sys_min_gen_ul, "ULiULiD*ULi", "n", SM_60) 715BUILTIN(__nvvm_atom_min_gen_ll, "LLiLLiD*LLi", "n") 716TARGET_BUILTIN(__nvvm_atom_cta_min_gen_ll, "LLiLLiD*LLi", "n", SM_60) 717TARGET_BUILTIN(__nvvm_atom_sys_min_gen_ll, "LLiLLiD*LLi", "n", SM_60) 718BUILTIN(__nvvm_atom_min_gen_ull, "ULLiULLiD*ULLi", "n") 719TARGET_BUILTIN(__nvvm_atom_cta_min_gen_ull, "ULLiULLiD*ULLi", "n", SM_60) 720TARGET_BUILTIN(__nvvm_atom_sys_min_gen_ull, "ULLiULLiD*ULLi", "n", SM_60) 721 722BUILTIN(__nvvm_atom_inc_gen_ui, "UiUiD*Ui", "n") 723TARGET_BUILTIN(__nvvm_atom_cta_inc_gen_ui, "UiUiD*Ui", "n", SM_60) 724TARGET_BUILTIN(__nvvm_atom_sys_inc_gen_ui, "UiUiD*Ui", "n", SM_60) 725BUILTIN(__nvvm_atom_dec_gen_ui, "UiUiD*Ui", "n") 726TARGET_BUILTIN(__nvvm_atom_cta_dec_gen_ui, "UiUiD*Ui", "n", SM_60) 727TARGET_BUILTIN(__nvvm_atom_sys_dec_gen_ui, "UiUiD*Ui", "n", SM_60) 728 729BUILTIN(__nvvm_atom_and_gen_i, "iiD*i", "n") 730TARGET_BUILTIN(__nvvm_atom_cta_and_gen_i, "iiD*i", "n", SM_60) 731TARGET_BUILTIN(__nvvm_atom_sys_and_gen_i, "iiD*i", "n", SM_60) 732BUILTIN(__nvvm_atom_and_gen_l, "LiLiD*Li", "n") 733TARGET_BUILTIN(__nvvm_atom_cta_and_gen_l, "LiLiD*Li", "n", SM_60) 734TARGET_BUILTIN(__nvvm_atom_sys_and_gen_l, "LiLiD*Li", "n", SM_60) 735BUILTIN(__nvvm_atom_and_gen_ll, "LLiLLiD*LLi", "n") 736TARGET_BUILTIN(__nvvm_atom_cta_and_gen_ll, "LLiLLiD*LLi", "n", SM_60) 737TARGET_BUILTIN(__nvvm_atom_sys_and_gen_ll, "LLiLLiD*LLi", "n", SM_60) 738 739BUILTIN(__nvvm_atom_or_gen_i, "iiD*i", "n") 740TARGET_BUILTIN(__nvvm_atom_cta_or_gen_i, "iiD*i", "n", SM_60) 741TARGET_BUILTIN(__nvvm_atom_sys_or_gen_i, "iiD*i", "n", SM_60) 742BUILTIN(__nvvm_atom_or_gen_l, "LiLiD*Li", "n") 743TARGET_BUILTIN(__nvvm_atom_cta_or_gen_l, "LiLiD*Li", "n", SM_60) 744TARGET_BUILTIN(__nvvm_atom_sys_or_gen_l, "LiLiD*Li", "n", SM_60) 745BUILTIN(__nvvm_atom_or_gen_ll, "LLiLLiD*LLi", "n") 746TARGET_BUILTIN(__nvvm_atom_cta_or_gen_ll, "LLiLLiD*LLi", "n", SM_60) 747TARGET_BUILTIN(__nvvm_atom_sys_or_gen_ll, "LLiLLiD*LLi", "n", SM_60) 748 749BUILTIN(__nvvm_atom_xor_gen_i, "iiD*i", "n") 750TARGET_BUILTIN(__nvvm_atom_cta_xor_gen_i, "iiD*i", "n", SM_60) 751TARGET_BUILTIN(__nvvm_atom_sys_xor_gen_i, "iiD*i", "n", SM_60) 752BUILTIN(__nvvm_atom_xor_gen_l, "LiLiD*Li", "n") 753TARGET_BUILTIN(__nvvm_atom_cta_xor_gen_l, "LiLiD*Li", "n", SM_60) 754TARGET_BUILTIN(__nvvm_atom_sys_xor_gen_l, "LiLiD*Li", "n", SM_60) 755BUILTIN(__nvvm_atom_xor_gen_ll, "LLiLLiD*LLi", "n") 756TARGET_BUILTIN(__nvvm_atom_cta_xor_gen_ll, "LLiLLiD*LLi", "n", SM_60) 757TARGET_BUILTIN(__nvvm_atom_sys_xor_gen_ll, "LLiLLiD*LLi", "n", SM_60) 758 759BUILTIN(__nvvm_atom_cas_gen_i, "iiD*ii", "n") 760TARGET_BUILTIN(__nvvm_atom_cta_cas_gen_i, "iiD*ii", "n", SM_60) 761TARGET_BUILTIN(__nvvm_atom_sys_cas_gen_i, "iiD*ii", "n", SM_60) 762BUILTIN(__nvvm_atom_cas_gen_l, "LiLiD*LiLi", "n") 763TARGET_BUILTIN(__nvvm_atom_cta_cas_gen_l, "LiLiD*LiLi", "n", SM_60) 764TARGET_BUILTIN(__nvvm_atom_sys_cas_gen_l, "LiLiD*LiLi", "n", SM_60) 765BUILTIN(__nvvm_atom_cas_gen_ll, "LLiLLiD*LLiLLi", "n") 766TARGET_BUILTIN(__nvvm_atom_cta_cas_gen_ll, "LLiLLiD*LLiLLi", "n", SM_60) 767TARGET_BUILTIN(__nvvm_atom_sys_cas_gen_ll, "LLiLLiD*LLiLLi", "n", SM_60) 768 769// Compiler Error Warn 770BUILTIN(__nvvm_compiler_error, "vcC*4", "n") 771BUILTIN(__nvvm_compiler_warn, "vcC*4", "n") 772 773// __ldg. This is not implemented as a builtin by nvcc. 774BUILTIN(__nvvm_ldg_c, "ccC*", "") 775BUILTIN(__nvvm_ldg_s, "ssC*", "") 776BUILTIN(__nvvm_ldg_i, "iiC*", "") 777BUILTIN(__nvvm_ldg_l, "LiLiC*", "") 778BUILTIN(__nvvm_ldg_ll, "LLiLLiC*", "") 779 780BUILTIN(__nvvm_ldg_uc, "UcUcC*", "") 781BUILTIN(__nvvm_ldg_us, "UsUsC*", "") 782BUILTIN(__nvvm_ldg_ui, "UiUiC*", "") 783BUILTIN(__nvvm_ldg_ul, "ULiULiC*", "") 784BUILTIN(__nvvm_ldg_ull, "ULLiULLiC*", "") 785 786BUILTIN(__nvvm_ldg_f, "ffC*", "") 787BUILTIN(__nvvm_ldg_d, "ddC*", "") 788 789BUILTIN(__nvvm_ldg_c2, "E2cE2cC*", "") 790BUILTIN(__nvvm_ldg_c4, "E4cE4cC*", "") 791BUILTIN(__nvvm_ldg_s2, "E2sE2sC*", "") 792BUILTIN(__nvvm_ldg_s4, "E4sE4sC*", "") 793BUILTIN(__nvvm_ldg_i2, "E2iE2iC*", "") 794BUILTIN(__nvvm_ldg_i4, "E4iE4iC*", "") 795BUILTIN(__nvvm_ldg_ll2, "E2LLiE2LLiC*", "") 796 797BUILTIN(__nvvm_ldg_uc2, "E2UcE2UcC*", "") 798BUILTIN(__nvvm_ldg_uc4, "E4UcE4UcC*", "") 799BUILTIN(__nvvm_ldg_us2, "E2UsE2UsC*", "") 800BUILTIN(__nvvm_ldg_us4, "E4UsE4UsC*", "") 801BUILTIN(__nvvm_ldg_ui2, "E2UiE2UiC*", "") 802BUILTIN(__nvvm_ldg_ui4, "E4UiE4UiC*", "") 803BUILTIN(__nvvm_ldg_ull2, "E2ULLiE2ULLiC*", "") 804 805BUILTIN(__nvvm_ldg_f2, "E2fE2fC*", "") 806BUILTIN(__nvvm_ldg_f4, "E4fE4fC*", "") 807BUILTIN(__nvvm_ldg_d2, "E2dE2dC*", "") 808 809// Address space predicates. 810BUILTIN(__nvvm_isspacep_const, "bvC*", "nc") 811BUILTIN(__nvvm_isspacep_global, "bvC*", "nc") 812BUILTIN(__nvvm_isspacep_local, "bvC*", "nc") 813BUILTIN(__nvvm_isspacep_shared, "bvC*", "nc") 814 815// Builtins to support WMMA instructions on sm_70 816TARGET_BUILTIN(__hmma_m16n16k16_ld_a, "vi*iC*UiIi", "", AND(SM_70,PTX60)) 817TARGET_BUILTIN(__hmma_m16n16k16_ld_b, "vi*iC*UiIi", "", AND(SM_70,PTX60)) 818TARGET_BUILTIN(__hmma_m16n16k16_ld_c_f16, "vi*iC*UiIi", "", AND(SM_70,PTX60)) 819TARGET_BUILTIN(__hmma_m16n16k16_ld_c_f32, "vf*fC*UiIi", "", AND(SM_70,PTX60)) 820TARGET_BUILTIN(__hmma_m16n16k16_st_c_f16, "vi*i*UiIi", "", AND(SM_70,PTX60)) 821TARGET_BUILTIN(__hmma_m16n16k16_st_c_f32, "vf*f*UiIi", "", AND(SM_70,PTX60)) 822 823TARGET_BUILTIN(__hmma_m32n8k16_ld_a, "vi*iC*UiIi", "", AND(SM_70,PTX61)) 824TARGET_BUILTIN(__hmma_m32n8k16_ld_b, "vi*iC*UiIi", "", AND(SM_70,PTX61)) 825TARGET_BUILTIN(__hmma_m32n8k16_ld_c_f16, "vi*iC*UiIi", "", AND(SM_70,PTX61)) 826TARGET_BUILTIN(__hmma_m32n8k16_ld_c_f32, "vf*fC*UiIi", "", AND(SM_70,PTX61)) 827TARGET_BUILTIN(__hmma_m32n8k16_st_c_f16, "vi*i*UiIi", "", AND(SM_70,PTX61)) 828TARGET_BUILTIN(__hmma_m32n8k16_st_c_f32, "vf*f*UiIi", "", AND(SM_70,PTX61)) 829 830TARGET_BUILTIN(__hmma_m8n32k16_ld_a, "vi*iC*UiIi", "", AND(SM_70,PTX61)) 831TARGET_BUILTIN(__hmma_m8n32k16_ld_b, "vi*iC*UiIi", "", AND(SM_70,PTX61)) 832TARGET_BUILTIN(__hmma_m8n32k16_ld_c_f16, "vi*iC*UiIi", "", AND(SM_70,PTX61)) 833TARGET_BUILTIN(__hmma_m8n32k16_ld_c_f32, "vf*fC*UiIi", "", AND(SM_70,PTX61)) 834TARGET_BUILTIN(__hmma_m8n32k16_st_c_f16, "vi*i*UiIi", "", AND(SM_70,PTX61)) 835TARGET_BUILTIN(__hmma_m8n32k16_st_c_f32, "vf*f*UiIi", "", AND(SM_70,PTX61)) 836 837TARGET_BUILTIN(__hmma_m16n16k16_mma_f16f16, "vi*iC*iC*iC*IiIi", "", AND(SM_70,PTX60)) 838TARGET_BUILTIN(__hmma_m16n16k16_mma_f32f16, "vf*iC*iC*iC*IiIi", "", AND(SM_70,PTX60)) 839TARGET_BUILTIN(__hmma_m16n16k16_mma_f32f32, "vf*iC*iC*fC*IiIi", "", AND(SM_70,PTX60)) 840TARGET_BUILTIN(__hmma_m16n16k16_mma_f16f32, "vi*iC*iC*fC*IiIi", "", AND(SM_70,PTX60)) 841 842TARGET_BUILTIN(__hmma_m32n8k16_mma_f16f16, "vi*iC*iC*iC*IiIi", "", AND(SM_70,PTX61)) 843TARGET_BUILTIN(__hmma_m32n8k16_mma_f32f16, "vf*iC*iC*iC*IiIi", "", AND(SM_70,PTX61)) 844TARGET_BUILTIN(__hmma_m32n8k16_mma_f32f32, "vf*iC*iC*fC*IiIi", "", AND(SM_70,PTX61)) 845TARGET_BUILTIN(__hmma_m32n8k16_mma_f16f32, "vi*iC*iC*fC*IiIi", "", AND(SM_70,PTX61)) 846 847TARGET_BUILTIN(__hmma_m8n32k16_mma_f16f16, "vi*iC*iC*iC*IiIi", "", AND(SM_70,PTX61)) 848TARGET_BUILTIN(__hmma_m8n32k16_mma_f32f16, "vf*iC*iC*iC*IiIi", "", AND(SM_70,PTX61)) 849TARGET_BUILTIN(__hmma_m8n32k16_mma_f32f32, "vf*iC*iC*fC*IiIi", "", AND(SM_70,PTX61)) 850TARGET_BUILTIN(__hmma_m8n32k16_mma_f16f32, "vi*iC*iC*fC*IiIi", "", AND(SM_70,PTX61)) 851 852// Builtins to support integer and sub-integer WMMA instructions on sm_72/sm_75 853TARGET_BUILTIN(__bmma_m8n8k128_ld_a_b1, "vi*iC*UiIi", "", AND(SM_75,PTX63)) 854TARGET_BUILTIN(__bmma_m8n8k128_ld_b_b1, "vi*iC*UiIi", "", AND(SM_75,PTX63)) 855TARGET_BUILTIN(__bmma_m8n8k128_ld_c, "vi*iC*UiIi", "", AND(SM_75,PTX63)) 856TARGET_BUILTIN(__bmma_m8n8k128_mma_and_popc_b1, "vi*iC*iC*iC*Ii", "", AND(SM_75,PTX71)) 857TARGET_BUILTIN(__bmma_m8n8k128_mma_xor_popc_b1, "vi*iC*iC*iC*Ii", "", AND(SM_75,PTX63)) 858TARGET_BUILTIN(__bmma_m8n8k128_st_c_i32, "vi*iC*UiIi", "", AND(SM_75,PTX63)) 859TARGET_BUILTIN(__imma_m16n16k16_ld_a_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 860TARGET_BUILTIN(__imma_m16n16k16_ld_a_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 861TARGET_BUILTIN(__imma_m16n16k16_ld_b_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 862TARGET_BUILTIN(__imma_m16n16k16_ld_b_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 863TARGET_BUILTIN(__imma_m16n16k16_ld_c, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 864TARGET_BUILTIN(__imma_m16n16k16_mma_s8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63)) 865TARGET_BUILTIN(__imma_m16n16k16_mma_u8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63)) 866TARGET_BUILTIN(__imma_m16n16k16_st_c_i32, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 867TARGET_BUILTIN(__imma_m32n8k16_ld_a_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 868TARGET_BUILTIN(__imma_m32n8k16_ld_a_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 869TARGET_BUILTIN(__imma_m32n8k16_ld_b_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 870TARGET_BUILTIN(__imma_m32n8k16_ld_b_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 871TARGET_BUILTIN(__imma_m32n8k16_ld_c, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 872TARGET_BUILTIN(__imma_m32n8k16_mma_s8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63)) 873TARGET_BUILTIN(__imma_m32n8k16_mma_u8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63)) 874TARGET_BUILTIN(__imma_m32n8k16_st_c_i32, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 875TARGET_BUILTIN(__imma_m8n32k16_ld_a_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 876TARGET_BUILTIN(__imma_m8n32k16_ld_a_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 877TARGET_BUILTIN(__imma_m8n32k16_ld_b_s8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 878TARGET_BUILTIN(__imma_m8n32k16_ld_b_u8, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 879TARGET_BUILTIN(__imma_m8n32k16_ld_c, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 880TARGET_BUILTIN(__imma_m8n32k16_mma_s8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63)) 881TARGET_BUILTIN(__imma_m8n32k16_mma_u8, "vi*iC*iC*iC*IiIi", "", AND(SM_72,PTX63)) 882TARGET_BUILTIN(__imma_m8n32k16_st_c_i32, "vi*iC*UiIi", "", AND(SM_72,PTX63)) 883TARGET_BUILTIN(__imma_m8n8k32_ld_a_s4, "vi*iC*UiIi", "", AND(SM_75,PTX63)) 884TARGET_BUILTIN(__imma_m8n8k32_ld_a_u4, "vi*iC*UiIi", "", AND(SM_75,PTX63)) 885TARGET_BUILTIN(__imma_m8n8k32_ld_b_s4, "vi*iC*UiIi", "", AND(SM_75,PTX63)) 886TARGET_BUILTIN(__imma_m8n8k32_ld_b_u4, "vi*iC*UiIi", "", AND(SM_75,PTX63)) 887TARGET_BUILTIN(__imma_m8n8k32_ld_c, "vi*iC*UiIi", "", AND(SM_75,PTX63)) 888TARGET_BUILTIN(__imma_m8n8k32_mma_s4, "vi*iC*iC*iC*IiIi", "", AND(SM_75,PTX63)) 889TARGET_BUILTIN(__imma_m8n8k32_mma_u4, "vi*iC*iC*iC*IiIi", "", AND(SM_75,PTX63)) 890TARGET_BUILTIN(__imma_m8n8k32_st_c_i32, "vi*iC*UiIi", "", AND(SM_75,PTX63)) 891 892// Builtins to support double and alternate float WMMA instructions on sm_80 893TARGET_BUILTIN(__dmma_m8n8k4_ld_a, "vd*dC*UiIi", "", AND(SM_80,PTX70)) 894TARGET_BUILTIN(__dmma_m8n8k4_ld_b, "vd*dC*UiIi", "", AND(SM_80,PTX70)) 895TARGET_BUILTIN(__dmma_m8n8k4_ld_c, "vd*dC*UiIi", "", AND(SM_80,PTX70)) 896TARGET_BUILTIN(__dmma_m8n8k4_st_c_f64, "vd*dC*UiIi", "", AND(SM_80,PTX70)) 897TARGET_BUILTIN(__dmma_m8n8k4_mma_f64, "vd*dC*dC*dC*IiIi", "", AND(SM_80,PTX70)) 898 899TARGET_BUILTIN(__mma_bf16_m16n16k16_ld_a, "vi*iC*UiIi", "", AND(SM_80,PTX70)) 900TARGET_BUILTIN(__mma_bf16_m16n16k16_ld_b, "vi*iC*UiIi", "", AND(SM_80,PTX70)) 901TARGET_BUILTIN(__mma_bf16_m16n16k16_mma_f32, "vf*iC*iC*fC*IiIi", "", AND(SM_80,PTX70)) 902TARGET_BUILTIN(__mma_bf16_m8n32k16_ld_a, "vi*iC*UiIi", "", AND(SM_80,PTX70)) 903TARGET_BUILTIN(__mma_bf16_m8n32k16_ld_b, "vi*iC*UiIi", "", AND(SM_80,PTX70)) 904TARGET_BUILTIN(__mma_bf16_m8n32k16_mma_f32, "vf*iC*iC*fC*IiIi", "", AND(SM_80,PTX70)) 905TARGET_BUILTIN(__mma_bf16_m32n8k16_ld_a, "vi*iC*UiIi", "", AND(SM_80,PTX70)) 906TARGET_BUILTIN(__mma_bf16_m32n8k16_ld_b, "vi*iC*UiIi", "", AND(SM_80,PTX70)) 907TARGET_BUILTIN(__mma_bf16_m32n8k16_mma_f32, "vf*iC*iC*fC*IiIi", "", AND(SM_80,PTX70)) 908 909TARGET_BUILTIN(__mma_tf32_m16n16k8_ld_a, "vi*iC*UiIi", "", AND(SM_80,PTX70)) 910TARGET_BUILTIN(__mma_tf32_m16n16k8_ld_b, "vi*iC*UiIi", "", AND(SM_80,PTX70)) 911TARGET_BUILTIN(__mma_tf32_m16n16k8_ld_c, "vf*fC*UiIi", "", AND(SM_80,PTX70)) 912TARGET_BUILTIN(__mma_m16n16k8_st_c_f32, "vf*fC*UiIi", "", AND(SM_80,PTX70)) 913TARGET_BUILTIN(__mma_tf32_m16n16k8_mma_f32, "vf*iC*iC*fC*IiIi", "", AND(SM_80,PTX70)) 914 915// Async Copy 916TARGET_BUILTIN(__nvvm_cp_async_mbarrier_arrive, "vWi*", "", AND(SM_80,PTX70)) 917TARGET_BUILTIN(__nvvm_cp_async_mbarrier_arrive_shared, "vWi*3", "", AND(SM_80,PTX70)) 918TARGET_BUILTIN(__nvvm_cp_async_mbarrier_arrive_noinc, "vWi*", "", AND(SM_80,PTX70)) 919TARGET_BUILTIN(__nvvm_cp_async_mbarrier_arrive_noinc_shared, "vWi*3", "", AND(SM_80,PTX70)) 920 921TARGET_BUILTIN(__nvvm_cp_async_ca_shared_global_4, "vv*3vC*1", "", AND(SM_80,PTX70)) 922TARGET_BUILTIN(__nvvm_cp_async_ca_shared_global_8, "vv*3vC*1", "", AND(SM_80,PTX70)) 923TARGET_BUILTIN(__nvvm_cp_async_ca_shared_global_16, "vv*3vC*1", "", AND(SM_80,PTX70)) 924TARGET_BUILTIN(__nvvm_cp_async_cg_shared_global_16, "vv*3vC*1", "", AND(SM_80,PTX70)) 925 926TARGET_BUILTIN(__nvvm_cp_async_commit_group, "v", "", AND(SM_80,PTX70)) 927TARGET_BUILTIN(__nvvm_cp_async_wait_group, "vIi", "", AND(SM_80,PTX70)) 928TARGET_BUILTIN(__nvvm_cp_async_wait_all, "v", "", AND(SM_80,PTX70)) 929 930 931// bf16, bf16x2 abs, neg 932TARGET_BUILTIN(__nvvm_abs_bf16, "UsUs", "", AND(SM_80,PTX70)) 933TARGET_BUILTIN(__nvvm_abs_bf16x2, "ZUiZUi", "", AND(SM_80,PTX70)) 934TARGET_BUILTIN(__nvvm_neg_bf16, "UsUs", "", AND(SM_80,PTX70)) 935TARGET_BUILTIN(__nvvm_neg_bf16x2, "ZUiZUi", "", AND(SM_80,PTX70)) 936 937#undef BUILTIN 938#undef TARGET_BUILTIN 939#pragma pop_macro("AND") 940#pragma pop_macro("SM_53") 941#pragma pop_macro("SM_60") 942#pragma pop_macro("SM_70") 943#pragma pop_macro("SM_72") 944#pragma pop_macro("SM_75") 945#pragma pop_macro("SM_80") 946#pragma pop_macro("SM_86") 947#pragma pop_macro("PTX42") 948#pragma pop_macro("PTX60") 949#pragma pop_macro("PTX61") 950#pragma pop_macro("PTX63") 951#pragma pop_macro("PTX64") 952#pragma pop_macro("PTX65") 953#pragma pop_macro("PTX70") 954#pragma pop_macro("PTX71") 955#pragma pop_macro("PTX72") 956#pragma pop_macro("PTX73") 957#pragma pop_macro("PTX74") 958#pragma pop_macro("PTX75") 959