1//===--- arm_neon_incl.td - ARM NEON compiler interface ------------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines data structures shared by arm_neon.td and arm_fp16.td. 10// It constains base operation classes, operations, instructions, instruction 11// modifiers, etc. 12// 13//===----------------------------------------------------------------------===// 14// 15// Each intrinsic is a subclass of the Inst class. An intrinsic can either 16// generate a __builtin_* call or it can expand to a set of generic operations. 17// 18// The operations are subclasses of Operation providing a list of DAGs, the 19// last of which is the return value. The available DAG nodes are documented 20// below. 21// 22//===----------------------------------------------------------------------===// 23 24// The base Operation class. All operations must subclass this. 25class Operation<list<dag> ops=[]> { 26 list<dag> Ops = ops; 27 bit Unavailable = 0; 28} 29// An operation that only contains a single DAG. 30class Op<dag op> : Operation<[op]>; 31// A shorter version of Operation - takes a list of DAGs. The last of these will 32// be the return value. 33class LOp<list<dag> ops> : Operation<ops>; 34 35// These defs and classes are used internally to implement the SetTheory 36// expansion and should be ignored. 37foreach Index = 0-63 in 38 def sv#Index; 39class MaskExpand; 40 41//===----------------------------------------------------------------------===// 42// Available operations 43//===----------------------------------------------------------------------===// 44 45// DAG arguments can either be operations (documented below) or variables. 46// Variables are prefixed with '$'. There are variables for each input argument, 47// with the name $pN, where N starts at zero. So the zero'th argument will be 48// $p0, the first $p1 etc. 49 50// op - Binary or unary operator, depending on the number of arguments. The 51// operator itself is just treated as a raw string and is not checked. 52// example: (op "+", $p0, $p1) -> "__p0 + __p1". 53// (op "-", $p0) -> "-__p0" 54def op; 55// call - Invoke another intrinsic. The input types are type checked and 56// disambiguated. If there is no intrinsic defined that takes 57// the given types (or if there is a type ambiguity) an error is 58// generated at tblgen time. The name of the intrinsic is the raw 59// name as given to the Inst class (not mangled). 60// example: (call "vget_high", $p0) -> "vgetq_high_s16(__p0)" 61// (assuming $p0 has type int16x8_t). 62def call; 63// call_mangled - Invoke another intrinsic matching the mangled name variation 64// of the caller's base type. If there is no intrinsic defined 65// that has the variation and takes the given types, an error 66// is generated at tblgen time. 67// example: (call_mangled "vfma_lane", $p0, $p1) -> "vfma_lane(__p0, __p1)" 68// (assuming non-LaneQ caller) 69// (call_mangled "vfma_lane", $p0, $p1) -> "vfma_laneq(__p0, __p1)" 70// (assuming LaneQ caller) 71def call_mangled; 72// cast - Perform a cast to a different type. This gets emitted as a static 73// C-style cast. For a pure reinterpret cast (T x = *(T*)&y), use 74// "bitcast". 75// 76// The syntax is (cast MOD* VAL). The last argument is the value to 77// cast, preceded by a sequence of type modifiers. The target type 78// starts off as the type of VAL, and is modified by MOD in sequence. 79// The available modifiers are: 80// - $X - Take the type of parameter/variable X. For example: 81// (cast $p0, $p1) would cast $p1 to the type of $p0. 82// - "R" - The type of the return type. 83// - A typedef string - A NEON or stdint.h type that is then parsed. 84// for example: (cast "uint32x4_t", $p0). 85// - "U" - Make the type unsigned. 86// - "S" - Make the type signed. 87// - "H" - Halve the number of lanes in the type. 88// - "D" - Double the number of lanes in the type. 89// - "8" - Convert type to an equivalent vector of 8-bit signed 90// integers. 91// - "32" - Convert type to an equivalent vector of 32-bit integers. 92// example: (cast "R", "U", $p0) -> "(uint32x4_t)__p0" (assuming the return 93// value is of type "int32x4_t". 94// (cast $p0, "D", "8", $p1) -> "(int8x16_t)__p1" (assuming __p0 95// has type float64x1_t or any other vector type of 64 bits). 96// (cast "int32_t", $p2) -> "(int32_t)__p2" 97def cast; 98// bitcast - Same as "cast", except a reinterpret-cast is produced: 99// (bitcast "T", $p0) -> "*(T*)&__p0". 100// The VAL argument is saved to a temporary so it can be used 101// as an l-value. 102def bitcast; 103// dup - Take a scalar argument and create a vector by duplicating it into 104// all lanes. The type of the vector is the base type of the intrinsic. 105// example: (dup $p1) -> "(uint32x2_t) {__p1, __p1}" (assuming the base type 106// is uint32x2_t). 107def dup; 108// dup_typed - Take a vector and a scalar argument, and create a new vector of 109// the same type by duplicating the scalar value into all lanes. 110// example: (dup_typed $p1, $p2) -> "(float16x4_t) {__p2, __p2, __p2, __p2}" 111// (assuming __p1 is float16x4_t, and __p2 is a compatible scalar). 112def dup_typed; 113// save_temp - Create a temporary (local) variable. The variable takes a name 114// based on the zero'th parameter and can be referenced using 115// using that name in subsequent DAGs in the same 116// operation. The scope of a temp is the operation. If a variable 117// with the given name already exists, an error will be given at 118// tblgen time. 119// example: [(save_temp $var, (call "foo", $p0)), 120// (op "+", $var, $p1)] -> 121// "int32x2_t __var = foo(__p0); return __var + __p1;" 122def save_temp; 123// name_replace - Return the name of the current intrinsic with the first 124// argument replaced by the second argument. Raises an error if 125// the first argument does not exist in the intrinsic name. 126// example: (call (name_replace "_high_", "_"), $p0) (to call the non-high 127// version of this intrinsic). 128def name_replace; 129// literal - Create a literal piece of code. The code is treated as a raw 130// string, and must be given a type. The type is a stdint.h or 131// NEON intrinsic type as given to (cast). 132// example: (literal "int32_t", "0") 133def literal; 134// shuffle - Create a vector shuffle. The syntax is (shuffle ARG0, ARG1, MASK). 135// The MASK argument is a set of elements. The elements are generated 136// from the two special defs "mask0" and "mask1". "mask0" expands to 137// the lane indices in sequence for ARG0, and "mask1" expands to 138// the lane indices in sequence for ARG1. They can be used as-is, e.g. 139// 140// (shuffle $p0, $p1, mask0) -> $p0 141// (shuffle $p0, $p1, mask1) -> $p1 142// 143// or, more usefully, they can be manipulated using the SetTheory 144// operators plus some extra operators defined in the NEON emitter. 145// The operators are described below. 146// example: (shuffle $p0, $p1, (add (highhalf mask0), (highhalf mask1))) -> 147// A concatenation of the high halves of the input vectors. 148def shuffle; 149 150// add, interleave, decimate: These set operators are vanilla SetTheory 151// operators and take their normal definition. 152def add; 153def interleave; 154def decimate; 155// rotl - Rotate set left by a number of elements. 156// example: (rotl mask0, 3) -> [3, 4, 5, 6, 0, 1, 2] 157def rotl; 158// rotl - Rotate set right by a number of elements. 159// example: (rotr mask0, 3) -> [4, 5, 6, 0, 1, 2, 3] 160def rotr; 161// highhalf - Take only the high half of the input. 162// example: (highhalf mask0) -> [4, 5, 6, 7] (assuming mask0 had 8 elements) 163def highhalf; 164// highhalf - Take only the low half of the input. 165// example: (lowhalf mask0) -> [0, 1, 2, 3] (assuming mask0 had 8 elements) 166def lowhalf; 167// rev - Perform a variable-width reversal of the elements. The zero'th argument 168// is a width in bits to reverse. The lanes this maps to is determined 169// based on the element width of the underlying type. 170// example: (rev 32, mask0) -> [3, 2, 1, 0, 7, 6, 5, 4] (if 8-bit elements) 171// example: (rev 32, mask0) -> [1, 0, 3, 2] (if 16-bit elements) 172def rev; 173// mask0 - The initial sequence of lanes for shuffle ARG0 174def mask0 : MaskExpand; 175// mask0 - The initial sequence of lanes for shuffle ARG1 176def mask1 : MaskExpand; 177 178def OP_NONE : Operation; 179def OP_UNAVAILABLE : Operation { 180 let Unavailable = 1; 181} 182 183//===----------------------------------------------------------------------===// 184// Instruction definitions 185//===----------------------------------------------------------------------===// 186 187// Every intrinsic subclasses "Inst". An intrinsic has a name, a prototype and 188// a sequence of typespecs. 189// 190// The name is the base name of the intrinsic, for example "vget_lane". This is 191// then mangled by the tblgen backend to add type information ("vget_lane_s16"). 192// 193// A typespec is a sequence of uppercase characters (modifiers) followed by one 194// lowercase character. A typespec encodes a particular "base type" of the 195// intrinsic. 196// 197// An example typespec is "Qs" - quad-size short - uint16x8_t. The available 198// typespec codes are given below. 199// 200// The string given to an Inst class is a sequence of typespecs. The intrinsic 201// is instantiated for every typespec in the sequence. For example "sdQsQd". 202// 203// The prototype is a string that defines the return type of the intrinsic 204// and the type of each argument. The return type and every argument gets a 205// set of "modifiers" that can change in some way the "base type" of the 206// intrinsic. 207// 208// Typespecs 209// --------- 210// c: char 211// s: short 212// i: int 213// l: long 214// k: 128-bit long 215// f: float 216// h: half-float 217// d: double 218// b: bfloat16 219// 220// Typespec modifiers 221// ------------------ 222// S: scalar, only used for function mangling. 223// U: unsigned 224// Q: 128b 225// H: 128b without mangling 'q' 226// P: polynomial 227// 228// Prototype modifiers 229// ------------------- 230// prototype: return (arg, arg, ...) 231// 232// Each type modifier is either a single character, or a group surrounded by 233// parentheses. 234// 235// .: default 236// v: change to void category. 237// S: change to signed integer category. 238// U: change to unsigned integer category. 239// F: change to floating category. 240// B: change to BFloat16 241// P: change to polynomial category. 242// p: change polynomial to equivalent integer category. Otherwise nop. 243// 244// >: double element width (vector size unchanged). 245// <: half element width (vector size unchanged). 246// 247// 1: change to scalar. 248// 2: change to struct of two vectors. 249// 3: change to struct of three vectors. 250// 4: change to struct of four vectors. 251// 252// *: make a pointer argument. 253// c: make a constant argument (for pointers). 254// 255// Q: force 128-bit width. 256// q: force 64-bit width. 257// 258// I: make 32-bit signed scalar immediate 259// !: make this the key type passed to CGBuiltin.cpp in a polymorphic call. 260 261 262// Every intrinsic subclasses Inst. 263class Inst <string n, string p, string t, Operation o> { 264 string Name = n; 265 string Prototype = p; 266 string Types = t; 267 string ArchGuard = ""; 268 269 Operation Operation = o; 270 bit BigEndianSafe = 0; 271 bit isShift = 0; 272 bit isScalarShift = 0; 273 bit isScalarNarrowShift = 0; 274 bit isVCVT_N = 0; 275 bit isVXAR = 0; 276 // For immediate checks: the immediate will be assumed to specify the lane of 277 // a Q register. Only used for intrinsics which end up calling polymorphic 278 // builtins. 279 bit isLaneQ = 0; 280 281 // Certain intrinsics have different names than their representative 282 // instructions. This field allows us to handle this correctly when we 283 // are generating tests. 284 string InstName = ""; 285 286 // Certain intrinsics even though they are not a WOpInst or LOpInst, 287 // generate a WOpInst/LOpInst instruction (see below for definition 288 // of a WOpInst/LOpInst). For testing purposes we need to know 289 // this. Ex: vset_lane which outputs vmov instructions. 290 bit isHiddenWInst = 0; 291 bit isHiddenLInst = 0; 292 293 string CartesianProductWith = ""; 294} 295 296// The following instruction classes are implemented via builtins. 297// These declarations are used to generate Builtins.def: 298// 299// SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8") 300// IInst: Instruction with generic integer suffix (e.g., "i8") 301// WInst: Instruction with only bit size suffix (e.g., "8") 302class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 303class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 304class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 305 306// The following instruction classes are implemented via operators 307// instead of builtins. As such these declarations are only used for 308// the purpose of generating tests. 309// 310// SOpInst: Instruction with signed/unsigned suffix (e.g., "s8", 311// "u8", "p8"). 312// IOpInst: Instruction with generic integer suffix (e.g., "i8"). 313// WOpInst: Instruction with bit size only suffix (e.g., "8"). 314// LOpInst: Logical instruction with no bit size suffix. 315// NoTestOpInst: Intrinsic that has no corresponding instruction. 316class SOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 317class IOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 318class WOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 319class LOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 320class NoTestOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 321