1 //===--- Hexagon.h - Declare Hexagon target feature support -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares Hexagon TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
15 
16 #include "clang/Basic/TargetInfo.h"
17 #include "clang/Basic/TargetOptions.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Support/Compiler.h"
20 
21 namespace clang {
22 namespace targets {
23 
24 // Hexagon abstract base class
25 class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
26 
27   static const char *const GCCRegNames[];
28   static const TargetInfo::GCCRegAlias GCCRegAliases[];
29   std::string CPU;
30   std::string HVXVersion;
31   bool HasHVX = false;
32   bool HasHVX64B = false;
33   bool HasHVX128B = false;
34   bool HasAudio = false;
35   bool UseLongCalls = false;
36 
37 public:
38   HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
39       : TargetInfo(Triple) {
40     // Specify the vector alignment explicitly. For v512x1, the calculated
41     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
42     // the required minimum of 64 bytes.
43     resetDataLayout(
44         "e-m:e-p:32:32:32-a:0-n16:32-"
45         "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
46         "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");
47     SizeType = UnsignedInt;
48     PtrDiffType = SignedInt;
49     IntPtrType = SignedInt;
50 
51     // {} in inline assembly are packet specifiers, not assembly variant
52     // specifiers.
53     NoAsmVariants = true;
54 
55     LargeArrayMinWidth = 64;
56     LargeArrayAlign = 64;
57     UseBitFieldTypeAlignment = true;
58     ZeroLengthBitfieldBoundary = 32;
59     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
60 
61     // These are the default values anyway, but explicitly make sure
62     // that the size of the boolean type is 8 bits. Bool vectors are used
63     // for modeling predicate registers in HVX, and the bool -> byte
64     // correspondence matches the HVX architecture.
65     BoolWidth = BoolAlign = 8;
66   }
67 
68   ArrayRef<Builtin::Info> getTargetBuiltins() const override;
69 
70   bool validateAsmConstraint(const char *&Name,
71                              TargetInfo::ConstraintInfo &Info) const override {
72     switch (*Name) {
73     case 'v':
74     case 'q':
75       if (HasHVX) {
76         Info.setAllowsRegister();
77         return true;
78       }
79       break;
80     case 'a': // Modifier register m0-m1.
81       Info.setAllowsRegister();
82       return true;
83     case 's':
84       // Relocatable constant.
85       return true;
86     }
87     return false;
88   }
89 
90   void getTargetDefines(const LangOptions &Opts,
91                         MacroBuilder &Builder) const override;
92 
93   bool isCLZForZeroUndef() const override { return false; }
94 
95   bool hasFeature(StringRef Feature) const override;
96 
97   bool
98   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
99                  StringRef CPU,
100                  const std::vector<std::string> &FeaturesVec) const override;
101 
102   bool handleTargetFeatures(std::vector<std::string> &Features,
103                             DiagnosticsEngine &Diags) override;
104 
105   BuiltinVaListKind getBuiltinVaListKind() const override {
106     if (getTriple().isMusl())
107       return TargetInfo::HexagonBuiltinVaList;
108     return TargetInfo::CharPtrBuiltinVaList;
109   }
110 
111   ArrayRef<const char *> getGCCRegNames() const override;
112 
113   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
114 
115   const char *getClobbers() const override { return ""; }
116 
117   static const char *getHexagonCPUSuffix(StringRef Name);
118 
119   bool isValidCPUName(StringRef Name) const override {
120     return getHexagonCPUSuffix(Name);
121   }
122 
123   void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
124 
125   bool setCPU(const std::string &Name) override {
126     if (!isValidCPUName(Name))
127       return false;
128     CPU = Name;
129     return true;
130   }
131 
132   int getEHDataRegisterNumber(unsigned RegNo) const override {
133     return RegNo < 2 ? RegNo : -1;
134   }
135 
136   bool isTinyCore() const {
137     // We can write more stricter checks later.
138     return CPU.find('t') != std::string::npos;
139   }
140 
141   bool hasBitIntType() const override { return true; }
142 };
143 } // namespace targets
144 } // namespace clang
145 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H
146