1 //===--- Mips.cpp - Implement Mips target feature support -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements Mips TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Mips.h"
14 #include "Targets.h"
15 #include "clang/Basic/Diagnostic.h"
16 #include "clang/Basic/MacroBuilder.h"
17 #include "clang/Basic/TargetBuiltins.h"
18 #include "llvm/ADT/StringSwitch.h"
19 
20 using namespace clang;
21 using namespace clang::targets;
22 
23 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
24 #define BUILTIN(ID, TYPE, ATTRS)                                               \
25   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
26 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
27   {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
28 #include "clang/Basic/BuiltinsMips.def"
29 };
30 
31 bool MipsTargetInfo::processorSupportsGPR64() const {
32   return llvm::StringSwitch<bool>(CPU)
33       .Case("mips3", true)
34       .Case("mips4", true)
35       .Case("mips5", true)
36       .Case("mips64", true)
37       .Case("mips64r2", true)
38       .Case("mips64r3", true)
39       .Case("mips64r5", true)
40       .Case("mips64r6", true)
41       .Case("octeon", true)
42       .Case("octeon+", true)
43       .Default(false);
44 }
45 
46 static constexpr llvm::StringLiteral ValidCPUNames[] = {
47     {"mips1"},  {"mips2"},    {"mips3"},    {"mips4"},    {"mips5"},
48     {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
49     {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
50     {"octeon"}, {"octeon+"}, {"p5600"}};
51 
52 bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
53   return llvm::is_contained(ValidCPUNames, Name);
54 }
55 
56 void MipsTargetInfo::fillValidCPUList(
57     SmallVectorImpl<StringRef> &Values) const {
58   Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
59 }
60 
61 unsigned MipsTargetInfo::getISARev() const {
62   return llvm::StringSwitch<unsigned>(getCPU())
63              .Cases("mips32", "mips64", 1)
64              .Cases("mips32r2", "mips64r2", "octeon", "octeon+", 2)
65              .Cases("mips32r3", "mips64r3", 3)
66              .Cases("mips32r5", "mips64r5", 5)
67              .Cases("mips32r6", "mips64r6", 6)
68              .Default(0);
69 }
70 
71 void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
72                                       MacroBuilder &Builder) const {
73   if (BigEndian) {
74     DefineStd(Builder, "MIPSEB", Opts);
75     Builder.defineMacro("_MIPSEB");
76   } else {
77     DefineStd(Builder, "MIPSEL", Opts);
78     Builder.defineMacro("_MIPSEL");
79   }
80 
81   Builder.defineMacro("__mips__");
82   Builder.defineMacro("_mips");
83   if (Opts.GNUMode)
84     Builder.defineMacro("mips");
85 
86   if (ABI == "o32") {
87     Builder.defineMacro("__mips", "32");
88     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
89   } else {
90     Builder.defineMacro("__mips", "64");
91     Builder.defineMacro("__mips64");
92     Builder.defineMacro("__mips64__");
93     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
94   }
95 
96   const std::string ISARev = std::to_string(getISARev());
97 
98   if (!ISARev.empty())
99     Builder.defineMacro("__mips_isa_rev", ISARev);
100 
101   if (ABI == "o32") {
102     Builder.defineMacro("__mips_o32");
103     Builder.defineMacro("_ABIO32", "1");
104     Builder.defineMacro("_MIPS_SIM", "_ABIO32");
105   } else if (ABI == "n32") {
106     Builder.defineMacro("__mips_n32");
107     Builder.defineMacro("_ABIN32", "2");
108     Builder.defineMacro("_MIPS_SIM", "_ABIN32");
109   } else if (ABI == "n64") {
110     Builder.defineMacro("__mips_n64");
111     Builder.defineMacro("_ABI64", "3");
112     Builder.defineMacro("_MIPS_SIM", "_ABI64");
113   } else
114     llvm_unreachable("Invalid ABI.");
115 
116   if (!IsNoABICalls) {
117     Builder.defineMacro("__mips_abicalls");
118     if (CanUseBSDABICalls)
119       Builder.defineMacro("__ABICALLS__");
120   }
121 
122   Builder.defineMacro("__REGISTER_PREFIX__", "");
123 
124   switch (FloatABI) {
125   case HardFloat:
126     Builder.defineMacro("__mips_hard_float", Twine(1));
127     break;
128   case SoftFloat:
129     Builder.defineMacro("__mips_soft_float", Twine(1));
130     break;
131   }
132 
133   if (IsSingleFloat)
134     Builder.defineMacro("__mips_single_float", Twine(1));
135 
136   switch (FPMode) {
137   case FPXX:
138     Builder.defineMacro("__mips_fpr", Twine(0));
139     break;
140   case FP32:
141     Builder.defineMacro("__mips_fpr", Twine(32));
142     break;
143   case FP64:
144     Builder.defineMacro("__mips_fpr", Twine(64));
145     break;
146 }
147 
148   if (FPMode == FP64 || IsSingleFloat)
149     Builder.defineMacro("_MIPS_FPSET", Twine(32));
150   else
151     Builder.defineMacro("_MIPS_FPSET", Twine(16));
152 
153   if (IsMips16)
154     Builder.defineMacro("__mips16", Twine(1));
155 
156   if (IsMicromips)
157     Builder.defineMacro("__mips_micromips", Twine(1));
158 
159   if (IsNan2008)
160     Builder.defineMacro("__mips_nan2008", Twine(1));
161 
162   if (IsAbs2008)
163     Builder.defineMacro("__mips_abs2008", Twine(1));
164 
165   switch (DspRev) {
166   default:
167     break;
168   case DSP1:
169     Builder.defineMacro("__mips_dsp_rev", Twine(1));
170     Builder.defineMacro("__mips_dsp", Twine(1));
171     break;
172   case DSP2:
173     Builder.defineMacro("__mips_dsp_rev", Twine(2));
174     Builder.defineMacro("__mips_dspr2", Twine(1));
175     Builder.defineMacro("__mips_dsp", Twine(1));
176     break;
177   }
178 
179   if (HasMSA)
180     Builder.defineMacro("__mips_msa", Twine(1));
181 
182   if (DisableMadd4)
183     Builder.defineMacro("__mips_no_madd4", Twine(1));
184 
185   Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
186   Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
187   Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
188 
189   Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
190   if (CPU == "octeon+")
191     Builder.defineMacro("_MIPS_ARCH_OCTEONP");
192   else
193     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
194 
195   if (StringRef(CPU).startswith("octeon"))
196     Builder.defineMacro("__OCTEON__");
197 
198   // These shouldn't be defined for MIPS-I but there's no need to check
199   // for that since MIPS-I isn't supported.
200   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
201   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
202   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
203 
204   // 32-bit MIPS processors don't have the necessary lld/scd instructions
205   // found in 64-bit processors. In the case of O32 on a 64-bit processor,
206   // the instructions exist but using them violates the ABI since they
207   // require 64-bit GPRs and O32 only supports 32-bit GPRs.
208   if (ABI == "n32" || ABI == "n64")
209     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
210 }
211 
212 bool MipsTargetInfo::hasFeature(StringRef Feature) const {
213   return llvm::StringSwitch<bool>(Feature)
214       .Case("mips", true)
215       .Case("dsp", DspRev >= DSP1)
216       .Case("dspr2", DspRev >= DSP2)
217       .Case("fp64", FPMode == FP64)
218       .Case("msa", HasMSA)
219       .Default(false);
220 }
221 
222 ArrayRef<Builtin::Info> MipsTargetInfo::getTargetBuiltins() const {
223   return llvm::makeArrayRef(BuiltinInfo, clang::Mips::LastTSBuiltin -
224                                              Builtin::FirstTSBuiltin);
225 }
226 
227 unsigned MipsTargetInfo::getUnwindWordWidth() const {
228   return llvm::StringSwitch<unsigned>(ABI)
229       .Case("o32", 32)
230       .Case("n32", 64)
231       .Case("n64", 64)
232       .Default(getPointerWidth(0));
233 }
234 
235 bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
236   // microMIPS64R6 backend was removed.
237   if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) {
238     Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU;
239     return false;
240   }
241   // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
242   //        this yet. It's better to fail here than on the backend assertion.
243   if (processorSupportsGPR64() && ABI == "o32") {
244     Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
245     return false;
246   }
247 
248   // 64-bit ABI's require 64-bit CPU's.
249   if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
250     Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
251     return false;
252   }
253 
254   // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
255   //        can't handle this yet. It's better to fail here than on the
256   //        backend assertion.
257   if (getTriple().isMIPS64() && ABI == "o32") {
258     Diags.Report(diag::err_target_unsupported_abi_for_triple)
259         << ABI << getTriple().str();
260     return false;
261   }
262 
263   // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
264   //        can't handle this yet. It's better to fail here than on the
265   //        backend assertion.
266   if (getTriple().isMIPS32() && (ABI == "n32" || ABI == "n64")) {
267     Diags.Report(diag::err_target_unsupported_abi_for_triple)
268         << ABI << getTriple().str();
269     return false;
270   }
271 
272   // -fpxx is valid only for the o32 ABI
273   if (FPMode == FPXX && (ABI == "n32" || ABI == "n64")) {
274     Diags.Report(diag::err_unsupported_abi_for_opt) << "-mfpxx" << "o32";
275     return false;
276   }
277 
278   // -mfp32 and n32/n64 ABIs are incompatible
279   if (FPMode != FP64 && FPMode != FPXX && !IsSingleFloat &&
280       (ABI == "n32" || ABI == "n64")) {
281     Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU;
282     return false;
283   }
284   // Mips revision 6 and -mfp32 are incompatible
285   if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" ||
286       CPU == "mips64r6")) {
287     Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
288     return false;
289   }
290   // Option -mfp64 permitted on Mips32 iff revision 2 or higher is present
291   if (FPMode == FP64 && (CPU == "mips1" || CPU == "mips2" ||
292       getISARev() < 2) && ABI == "o32") {
293     Diags.Report(diag::err_mips_fp64_req) << "-mfp64";
294     return false;
295   }
296 
297   return true;
298 }
299