1 //===--- RISCV.h - Declare RISCV target feature support ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares RISCV TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
15 
16 #include "clang/Basic/TargetInfo.h"
17 #include "clang/Basic/TargetOptions.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Support/Compiler.h"
20 #include "llvm/Support/RISCVISAInfo.h"
21 
22 namespace clang {
23 namespace targets {
24 
25 // RISC-V Target
26 class RISCVTargetInfo : public TargetInfo {
27 protected:
28   std::string ABI, CPU;
29   std::unique_ptr<llvm::RISCVISAInfo> ISAInfo;
30   static const Builtin::Info BuiltinInfo[];
31 
32 public:
33   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
34       : TargetInfo(Triple) {
35     LongDoubleWidth = 128;
36     LongDoubleAlign = 128;
37     LongDoubleFormat = &llvm::APFloat::IEEEquad();
38     SuitableAlign = 128;
39     WCharType = SignedInt;
40     WIntType = UnsignedInt;
41     HasRISCVVTypes = true;
42     MCountName = "_mcount";
43     HasFloat16 = true;
44   }
45 
46   bool setCPU(const std::string &Name) override {
47     if (!isValidCPUName(Name))
48       return false;
49     CPU = Name;
50     return true;
51   }
52 
53   StringRef getABI() const override { return ABI; }
54   void getTargetDefines(const LangOptions &Opts,
55                         MacroBuilder &Builder) const override;
56 
57   ArrayRef<Builtin::Info> getTargetBuiltins() const override;
58 
59   BuiltinVaListKind getBuiltinVaListKind() const override {
60     return TargetInfo::VoidPtrBuiltinVaList;
61   }
62 
63   const char *getClobbers() const override { return ""; }
64 
65   StringRef getConstraintRegister(StringRef Constraint,
66                                   StringRef Expression) const override {
67     return Expression;
68   }
69 
70   ArrayRef<const char *> getGCCRegNames() const override;
71 
72   int getEHDataRegisterNumber(unsigned RegNo) const override {
73     if (RegNo == 0)
74       return 10;
75     else if (RegNo == 1)
76       return 11;
77     else
78       return -1;
79   }
80 
81   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
82 
83   bool validateAsmConstraint(const char *&Name,
84                              TargetInfo::ConstraintInfo &Info) const override;
85 
86   std::string convertConstraint(const char *&Constraint) const override;
87 
88   bool
89   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
90                  StringRef CPU,
91                  const std::vector<std::string> &FeaturesVec) const override;
92 
93   bool hasFeature(StringRef Feature) const override;
94 
95   bool handleTargetFeatures(std::vector<std::string> &Features,
96                             DiagnosticsEngine &Diags) override;
97 
98   bool hasBitIntType() const override { return true; }
99 
100   bool useFP16ConversionIntrinsics() const override {
101     return false;
102   }
103 };
104 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
105 public:
106   RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
107       : RISCVTargetInfo(Triple, Opts) {
108     IntPtrType = SignedInt;
109     PtrDiffType = SignedInt;
110     SizeType = UnsignedInt;
111     resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
112   }
113 
114   bool setABI(const std::string &Name) override {
115     if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") {
116       ABI = Name;
117       return true;
118     }
119     return false;
120   }
121 
122   bool isValidCPUName(StringRef Name) const override;
123   void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
124   bool isValidTuneCPUName(StringRef Name) const override;
125   void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
126 
127   void setMaxAtomicWidth() override {
128     MaxAtomicPromoteWidth = 128;
129 
130     if (ISAInfo->hasExtension("a"))
131       MaxAtomicInlineWidth = 32;
132   }
133 };
134 class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
135 public:
136   RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
137       : RISCVTargetInfo(Triple, Opts) {
138     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
139     IntMaxType = Int64Type = SignedLong;
140     resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n64-S128");
141   }
142 
143   bool setABI(const std::string &Name) override {
144     if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") {
145       ABI = Name;
146       return true;
147     }
148     return false;
149   }
150 
151   bool isValidCPUName(StringRef Name) const override;
152   void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
153   bool isValidTuneCPUName(StringRef Name) const override;
154   void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
155 
156   void setMaxAtomicWidth() override {
157     MaxAtomicPromoteWidth = 128;
158 
159     if (ISAInfo->hasExtension("a"))
160       MaxAtomicInlineWidth = 64;
161   }
162 };
163 } // namespace targets
164 } // namespace clang
165 
166 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H
167