1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/X86TargetParser.h" 21 22 namespace clang { 23 namespace targets { 24 25 const Builtin::Info BuiltinInfoX86[] = { 26 #define BUILTIN(ID, TYPE, ATTRS) \ 27 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 29 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 31 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 32 #include "clang/Basic/BuiltinsX86.def" 33 34 #define BUILTIN(ID, TYPE, ATTRS) \ 35 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 37 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 39 {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, 40 #include "clang/Basic/BuiltinsX86_64.def" 41 }; 42 43 static const char *const GCCRegNames[] = { 44 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 45 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 46 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 47 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 48 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 49 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 50 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 51 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 52 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 53 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 54 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 55 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 56 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 57 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 58 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 59 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 60 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 61 "k2", "k3", "k4", "k5", "k6", "k7", 62 "cr0", "cr2", "cr3", "cr4", "cr8", 63 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 64 "bnd0", "bnd1", "bnd2", "bnd3", 65 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 66 }; 67 68 const TargetInfo::AddlRegName AddlRegNames[] = { 69 {{"al", "ah", "eax", "rax"}, 0}, 70 {{"bl", "bh", "ebx", "rbx"}, 3}, 71 {{"cl", "ch", "ecx", "rcx"}, 2}, 72 {{"dl", "dh", "edx", "rdx"}, 1}, 73 {{"esi", "rsi"}, 4}, 74 {{"edi", "rdi"}, 5}, 75 {{"esp", "rsp"}, 7}, 76 {{"ebp", "rbp"}, 6}, 77 {{"r8d", "r8w", "r8b"}, 38}, 78 {{"r9d", "r9w", "r9b"}, 39}, 79 {{"r10d", "r10w", "r10b"}, 40}, 80 {{"r11d", "r11w", "r11b"}, 41}, 81 {{"r12d", "r12w", "r12b"}, 42}, 82 {{"r13d", "r13w", "r13b"}, 43}, 83 {{"r14d", "r14w", "r14b"}, 44}, 84 {{"r15d", "r15w", "r15b"}, 45}, 85 }; 86 87 } // namespace targets 88 } // namespace clang 89 90 using namespace clang; 91 using namespace clang::targets; 92 93 bool X86TargetInfo::setFPMath(StringRef Name) { 94 if (Name == "387") { 95 FPMath = FP_387; 96 return true; 97 } 98 if (Name == "sse") { 99 FPMath = FP_SSE; 100 return true; 101 } 102 return false; 103 } 104 105 bool X86TargetInfo::initFeatureMap( 106 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 107 const std::vector<std::string> &FeaturesVec) const { 108 // FIXME: This *really* should not be here. 109 // X86_64 always has SSE2. 110 if (getTriple().getArch() == llvm::Triple::x86_64) 111 setFeatureEnabled(Features, "sse2", true); 112 113 using namespace llvm::X86; 114 115 SmallVector<StringRef, 16> CPUFeatures; 116 getFeaturesForCPU(CPU, CPUFeatures); 117 for (auto &F : CPUFeatures) 118 setFeatureEnabled(Features, F, true); 119 120 std::vector<std::string> UpdatedFeaturesVec; 121 for (const auto &Feature : FeaturesVec) { 122 // Expand general-regs-only to -x86, -mmx and -sse 123 if (Feature == "+general-regs-only") { 124 UpdatedFeaturesVec.push_back("-x87"); 125 UpdatedFeaturesVec.push_back("-mmx"); 126 UpdatedFeaturesVec.push_back("-sse"); 127 continue; 128 } 129 130 UpdatedFeaturesVec.push_back(Feature); 131 } 132 133 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) 134 return false; 135 136 // Can't do this earlier because we need to be able to explicitly enable 137 // or disable these features and the things that they depend upon. 138 139 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 140 auto I = Features.find("sse4.2"); 141 if (I != Features.end() && I->getValue() && 142 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt")) 143 Features["popcnt"] = true; 144 145 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 146 // then enable MMX. 147 I = Features.find("sse"); 148 if (I != Features.end() && I->getValue() && 149 !llvm::is_contained(UpdatedFeaturesVec, "-mmx")) 150 Features["mmx"] = true; 151 152 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 153 I = Features.find("avx"); 154 if (I != Features.end() && I->getValue() && 155 !llvm::is_contained(UpdatedFeaturesVec, "-xsave")) 156 Features["xsave"] = true; 157 158 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled. 159 I = Features.find("sse4.2"); 160 if (I != Features.end() && I->getValue() && 161 !llvm::is_contained(UpdatedFeaturesVec, "-crc32")) 162 Features["crc32"] = true; 163 164 return true; 165 } 166 167 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 168 StringRef Name, bool Enabled) const { 169 if (Name == "sse4") { 170 // We can get here via the __target__ attribute since that's not controlled 171 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 172 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 173 // disabled. 174 if (Enabled) 175 Name = "sse4.2"; 176 else 177 Name = "sse4.1"; 178 } 179 180 Features[Name] = Enabled; 181 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 182 } 183 184 /// handleTargetFeatures - Perform initialization based on the user 185 /// configured set of features. 186 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 187 DiagnosticsEngine &Diags) { 188 for (const auto &Feature : Features) { 189 if (Feature[0] != '+') 190 continue; 191 192 if (Feature == "+aes") { 193 HasAES = true; 194 } else if (Feature == "+vaes") { 195 HasVAES = true; 196 } else if (Feature == "+pclmul") { 197 HasPCLMUL = true; 198 } else if (Feature == "+vpclmulqdq") { 199 HasVPCLMULQDQ = true; 200 } else if (Feature == "+lzcnt") { 201 HasLZCNT = true; 202 } else if (Feature == "+rdrnd") { 203 HasRDRND = true; 204 } else if (Feature == "+fsgsbase") { 205 HasFSGSBASE = true; 206 } else if (Feature == "+bmi") { 207 HasBMI = true; 208 } else if (Feature == "+bmi2") { 209 HasBMI2 = true; 210 } else if (Feature == "+popcnt") { 211 HasPOPCNT = true; 212 } else if (Feature == "+rtm") { 213 HasRTM = true; 214 } else if (Feature == "+prfchw") { 215 HasPRFCHW = true; 216 } else if (Feature == "+rdseed") { 217 HasRDSEED = true; 218 } else if (Feature == "+adx") { 219 HasADX = true; 220 } else if (Feature == "+tbm") { 221 HasTBM = true; 222 } else if (Feature == "+lwp") { 223 HasLWP = true; 224 } else if (Feature == "+fma") { 225 HasFMA = true; 226 } else if (Feature == "+f16c") { 227 HasF16C = true; 228 } else if (Feature == "+gfni") { 229 HasGFNI = true; 230 } else if (Feature == "+avx512cd") { 231 HasAVX512CD = true; 232 } else if (Feature == "+avx512vpopcntdq") { 233 HasAVX512VPOPCNTDQ = true; 234 } else if (Feature == "+avx512vnni") { 235 HasAVX512VNNI = true; 236 } else if (Feature == "+avx512bf16") { 237 HasAVX512BF16 = true; 238 } else if (Feature == "+avx512er") { 239 HasAVX512ER = true; 240 } else if (Feature == "+avx512fp16") { 241 HasAVX512FP16 = true; 242 } else if (Feature == "+avx512pf") { 243 HasAVX512PF = true; 244 } else if (Feature == "+avx512dq") { 245 HasAVX512DQ = true; 246 } else if (Feature == "+avx512bitalg") { 247 HasAVX512BITALG = true; 248 } else if (Feature == "+avx512bw") { 249 HasAVX512BW = true; 250 } else if (Feature == "+avx512vl") { 251 HasAVX512VL = true; 252 } else if (Feature == "+avx512vbmi") { 253 HasAVX512VBMI = true; 254 } else if (Feature == "+avx512vbmi2") { 255 HasAVX512VBMI2 = true; 256 } else if (Feature == "+avx512ifma") { 257 HasAVX512IFMA = true; 258 } else if (Feature == "+avx512vp2intersect") { 259 HasAVX512VP2INTERSECT = true; 260 } else if (Feature == "+sha") { 261 HasSHA = true; 262 } else if (Feature == "+shstk") { 263 HasSHSTK = true; 264 } else if (Feature == "+movbe") { 265 HasMOVBE = true; 266 } else if (Feature == "+sgx") { 267 HasSGX = true; 268 } else if (Feature == "+cx8") { 269 HasCX8 = true; 270 } else if (Feature == "+cx16") { 271 HasCX16 = true; 272 } else if (Feature == "+fxsr") { 273 HasFXSR = true; 274 } else if (Feature == "+xsave") { 275 HasXSAVE = true; 276 } else if (Feature == "+xsaveopt") { 277 HasXSAVEOPT = true; 278 } else if (Feature == "+xsavec") { 279 HasXSAVEC = true; 280 } else if (Feature == "+xsaves") { 281 HasXSAVES = true; 282 } else if (Feature == "+mwaitx") { 283 HasMWAITX = true; 284 } else if (Feature == "+pku") { 285 HasPKU = true; 286 } else if (Feature == "+clflushopt") { 287 HasCLFLUSHOPT = true; 288 } else if (Feature == "+clwb") { 289 HasCLWB = true; 290 } else if (Feature == "+wbnoinvd") { 291 HasWBNOINVD = true; 292 } else if (Feature == "+prefetchwt1") { 293 HasPREFETCHWT1 = true; 294 } else if (Feature == "+clzero") { 295 HasCLZERO = true; 296 } else if (Feature == "+cldemote") { 297 HasCLDEMOTE = true; 298 } else if (Feature == "+rdpid") { 299 HasRDPID = true; 300 } else if (Feature == "+rdpru") { 301 HasRDPRU = true; 302 } else if (Feature == "+kl") { 303 HasKL = true; 304 } else if (Feature == "+widekl") { 305 HasWIDEKL = true; 306 } else if (Feature == "+retpoline-external-thunk") { 307 HasRetpolineExternalThunk = true; 308 } else if (Feature == "+sahf") { 309 HasLAHFSAHF = true; 310 } else if (Feature == "+waitpkg") { 311 HasWAITPKG = true; 312 } else if (Feature == "+movdiri") { 313 HasMOVDIRI = true; 314 } else if (Feature == "+movdir64b") { 315 HasMOVDIR64B = true; 316 } else if (Feature == "+pconfig") { 317 HasPCONFIG = true; 318 } else if (Feature == "+ptwrite") { 319 HasPTWRITE = true; 320 } else if (Feature == "+invpcid") { 321 HasINVPCID = true; 322 } else if (Feature == "+enqcmd") { 323 HasENQCMD = true; 324 } else if (Feature == "+hreset") { 325 HasHRESET = true; 326 } else if (Feature == "+amx-bf16") { 327 HasAMXBF16 = true; 328 } else if (Feature == "+amx-int8") { 329 HasAMXINT8 = true; 330 } else if (Feature == "+amx-tile") { 331 HasAMXTILE = true; 332 } else if (Feature == "+avxvnni") { 333 HasAVXVNNI = true; 334 } else if (Feature == "+serialize") { 335 HasSERIALIZE = true; 336 } else if (Feature == "+tsxldtrk") { 337 HasTSXLDTRK = true; 338 } else if (Feature == "+uintr") { 339 HasUINTR = true; 340 } else if (Feature == "+crc32") { 341 HasCRC32 = true; 342 } else if (Feature == "+x87") { 343 HasX87 = true; 344 } 345 346 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 347 .Case("+avx512f", AVX512F) 348 .Case("+avx2", AVX2) 349 .Case("+avx", AVX) 350 .Case("+sse4.2", SSE42) 351 .Case("+sse4.1", SSE41) 352 .Case("+ssse3", SSSE3) 353 .Case("+sse3", SSE3) 354 .Case("+sse2", SSE2) 355 .Case("+sse", SSE1) 356 .Default(NoSSE); 357 SSELevel = std::max(SSELevel, Level); 358 359 HasFloat16 = SSELevel >= SSE2; 360 361 MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) 362 .Case("+3dnowa", AMD3DNowAthlon) 363 .Case("+3dnow", AMD3DNow) 364 .Case("+mmx", MMX) 365 .Default(NoMMX3DNow); 366 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 367 368 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 369 .Case("+xop", XOP) 370 .Case("+fma4", FMA4) 371 .Case("+sse4a", SSE4A) 372 .Default(NoXOP); 373 XOPLevel = std::max(XOPLevel, XLevel); 374 } 375 376 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 377 // matches the selected sse level. 378 if ((FPMath == FP_SSE && SSELevel < SSE1) || 379 (FPMath == FP_387 && SSELevel >= SSE1)) { 380 Diags.Report(diag::err_target_unsupported_fpmath) 381 << (FPMath == FP_SSE ? "sse" : "387"); 382 return false; 383 } 384 385 SimdDefaultAlign = 386 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 387 388 // FIXME: We should allow long double type on 32-bits to match with GCC. 389 // This requires backend to be able to lower f80 without x87 first. 390 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended()) 391 HasLongDouble = false; 392 393 return true; 394 } 395 396 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 397 /// definitions for this particular subtarget. 398 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 399 MacroBuilder &Builder) const { 400 // Inline assembly supports X86 flag outputs. 401 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 402 403 std::string CodeModel = getTargetOpts().CodeModel; 404 if (CodeModel == "default") 405 CodeModel = "small"; 406 Builder.defineMacro("__code_model_" + CodeModel + "__"); 407 408 // Target identification. 409 if (getTriple().getArch() == llvm::Triple::x86_64) { 410 Builder.defineMacro("__amd64__"); 411 Builder.defineMacro("__amd64"); 412 Builder.defineMacro("__x86_64"); 413 Builder.defineMacro("__x86_64__"); 414 if (getTriple().getArchName() == "x86_64h") { 415 Builder.defineMacro("__x86_64h"); 416 Builder.defineMacro("__x86_64h__"); 417 } 418 } else { 419 DefineStd(Builder, "i386", Opts); 420 } 421 422 Builder.defineMacro("__SEG_GS"); 423 Builder.defineMacro("__SEG_FS"); 424 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 425 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 426 427 // Subtarget options. 428 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 429 // truly should be based on -mtune options. 430 using namespace llvm::X86; 431 switch (CPU) { 432 case CK_None: 433 break; 434 case CK_i386: 435 // The rest are coming from the i386 define above. 436 Builder.defineMacro("__tune_i386__"); 437 break; 438 case CK_i486: 439 case CK_WinChipC6: 440 case CK_WinChip2: 441 case CK_C3: 442 defineCPUMacros(Builder, "i486"); 443 break; 444 case CK_PentiumMMX: 445 Builder.defineMacro("__pentium_mmx__"); 446 Builder.defineMacro("__tune_pentium_mmx__"); 447 LLVM_FALLTHROUGH; 448 case CK_i586: 449 case CK_Pentium: 450 defineCPUMacros(Builder, "i586"); 451 defineCPUMacros(Builder, "pentium"); 452 break; 453 case CK_Pentium3: 454 case CK_PentiumM: 455 Builder.defineMacro("__tune_pentium3__"); 456 LLVM_FALLTHROUGH; 457 case CK_Pentium2: 458 case CK_C3_2: 459 Builder.defineMacro("__tune_pentium2__"); 460 LLVM_FALLTHROUGH; 461 case CK_PentiumPro: 462 case CK_i686: 463 defineCPUMacros(Builder, "i686"); 464 defineCPUMacros(Builder, "pentiumpro"); 465 break; 466 case CK_Pentium4: 467 defineCPUMacros(Builder, "pentium4"); 468 break; 469 case CK_Yonah: 470 case CK_Prescott: 471 case CK_Nocona: 472 defineCPUMacros(Builder, "nocona"); 473 break; 474 case CK_Core2: 475 case CK_Penryn: 476 defineCPUMacros(Builder, "core2"); 477 break; 478 case CK_Bonnell: 479 defineCPUMacros(Builder, "atom"); 480 break; 481 case CK_Silvermont: 482 defineCPUMacros(Builder, "slm"); 483 break; 484 case CK_Goldmont: 485 defineCPUMacros(Builder, "goldmont"); 486 break; 487 case CK_GoldmontPlus: 488 defineCPUMacros(Builder, "goldmont_plus"); 489 break; 490 case CK_Tremont: 491 defineCPUMacros(Builder, "tremont"); 492 break; 493 case CK_Nehalem: 494 case CK_Westmere: 495 case CK_SandyBridge: 496 case CK_IvyBridge: 497 case CK_Haswell: 498 case CK_Broadwell: 499 case CK_SkylakeClient: 500 case CK_SkylakeServer: 501 case CK_Cascadelake: 502 case CK_Cooperlake: 503 case CK_Cannonlake: 504 case CK_IcelakeClient: 505 case CK_Rocketlake: 506 case CK_IcelakeServer: 507 case CK_Tigerlake: 508 case CK_SapphireRapids: 509 case CK_Alderlake: 510 // FIXME: Historically, we defined this legacy name, it would be nice to 511 // remove it at some point. We've never exposed fine-grained names for 512 // recent primary x86 CPUs, and we should keep it that way. 513 defineCPUMacros(Builder, "corei7"); 514 break; 515 case CK_KNL: 516 defineCPUMacros(Builder, "knl"); 517 break; 518 case CK_KNM: 519 break; 520 case CK_Lakemont: 521 defineCPUMacros(Builder, "i586", /*Tuning*/false); 522 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 523 Builder.defineMacro("__tune_lakemont__"); 524 break; 525 case CK_K6_2: 526 Builder.defineMacro("__k6_2__"); 527 Builder.defineMacro("__tune_k6_2__"); 528 LLVM_FALLTHROUGH; 529 case CK_K6_3: 530 if (CPU != CK_K6_2) { // In case of fallthrough 531 // FIXME: GCC may be enabling these in cases where some other k6 532 // architecture is specified but -m3dnow is explicitly provided. The 533 // exact semantics need to be determined and emulated here. 534 Builder.defineMacro("__k6_3__"); 535 Builder.defineMacro("__tune_k6_3__"); 536 } 537 LLVM_FALLTHROUGH; 538 case CK_K6: 539 defineCPUMacros(Builder, "k6"); 540 break; 541 case CK_Athlon: 542 case CK_AthlonXP: 543 defineCPUMacros(Builder, "athlon"); 544 if (SSELevel != NoSSE) { 545 Builder.defineMacro("__athlon_sse__"); 546 Builder.defineMacro("__tune_athlon_sse__"); 547 } 548 break; 549 case CK_K8: 550 case CK_K8SSE3: 551 case CK_x86_64: 552 defineCPUMacros(Builder, "k8"); 553 break; 554 case CK_x86_64_v2: 555 case CK_x86_64_v3: 556 case CK_x86_64_v4: 557 break; 558 case CK_AMDFAM10: 559 defineCPUMacros(Builder, "amdfam10"); 560 break; 561 case CK_BTVER1: 562 defineCPUMacros(Builder, "btver1"); 563 break; 564 case CK_BTVER2: 565 defineCPUMacros(Builder, "btver2"); 566 break; 567 case CK_BDVER1: 568 defineCPUMacros(Builder, "bdver1"); 569 break; 570 case CK_BDVER2: 571 defineCPUMacros(Builder, "bdver2"); 572 break; 573 case CK_BDVER3: 574 defineCPUMacros(Builder, "bdver3"); 575 break; 576 case CK_BDVER4: 577 defineCPUMacros(Builder, "bdver4"); 578 break; 579 case CK_ZNVER1: 580 defineCPUMacros(Builder, "znver1"); 581 break; 582 case CK_ZNVER2: 583 defineCPUMacros(Builder, "znver2"); 584 break; 585 case CK_ZNVER3: 586 defineCPUMacros(Builder, "znver3"); 587 break; 588 case CK_Geode: 589 defineCPUMacros(Builder, "geode"); 590 break; 591 } 592 593 // Target properties. 594 Builder.defineMacro("__REGISTER_PREFIX__", ""); 595 596 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 597 // functions in glibc header files that use FP Stack inline asm which the 598 // backend can't deal with (PR879). 599 Builder.defineMacro("__NO_MATH_INLINES"); 600 601 if (HasAES) 602 Builder.defineMacro("__AES__"); 603 604 if (HasVAES) 605 Builder.defineMacro("__VAES__"); 606 607 if (HasPCLMUL) 608 Builder.defineMacro("__PCLMUL__"); 609 610 if (HasVPCLMULQDQ) 611 Builder.defineMacro("__VPCLMULQDQ__"); 612 613 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 614 // the feature flag only applies to 64-bit mode. 615 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 616 Builder.defineMacro("__LAHF_SAHF__"); 617 618 if (HasLZCNT) 619 Builder.defineMacro("__LZCNT__"); 620 621 if (HasRDRND) 622 Builder.defineMacro("__RDRND__"); 623 624 if (HasFSGSBASE) 625 Builder.defineMacro("__FSGSBASE__"); 626 627 if (HasBMI) 628 Builder.defineMacro("__BMI__"); 629 630 if (HasBMI2) 631 Builder.defineMacro("__BMI2__"); 632 633 if (HasPOPCNT) 634 Builder.defineMacro("__POPCNT__"); 635 636 if (HasRTM) 637 Builder.defineMacro("__RTM__"); 638 639 if (HasPRFCHW) 640 Builder.defineMacro("__PRFCHW__"); 641 642 if (HasRDSEED) 643 Builder.defineMacro("__RDSEED__"); 644 645 if (HasADX) 646 Builder.defineMacro("__ADX__"); 647 648 if (HasTBM) 649 Builder.defineMacro("__TBM__"); 650 651 if (HasLWP) 652 Builder.defineMacro("__LWP__"); 653 654 if (HasMWAITX) 655 Builder.defineMacro("__MWAITX__"); 656 657 if (HasMOVBE) 658 Builder.defineMacro("__MOVBE__"); 659 660 switch (XOPLevel) { 661 case XOP: 662 Builder.defineMacro("__XOP__"); 663 LLVM_FALLTHROUGH; 664 case FMA4: 665 Builder.defineMacro("__FMA4__"); 666 LLVM_FALLTHROUGH; 667 case SSE4A: 668 Builder.defineMacro("__SSE4A__"); 669 LLVM_FALLTHROUGH; 670 case NoXOP: 671 break; 672 } 673 674 if (HasFMA) 675 Builder.defineMacro("__FMA__"); 676 677 if (HasF16C) 678 Builder.defineMacro("__F16C__"); 679 680 if (HasGFNI) 681 Builder.defineMacro("__GFNI__"); 682 683 if (HasAVX512CD) 684 Builder.defineMacro("__AVX512CD__"); 685 if (HasAVX512VPOPCNTDQ) 686 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 687 if (HasAVX512VNNI) 688 Builder.defineMacro("__AVX512VNNI__"); 689 if (HasAVX512BF16) 690 Builder.defineMacro("__AVX512BF16__"); 691 if (HasAVX512ER) 692 Builder.defineMacro("__AVX512ER__"); 693 if (HasAVX512FP16) 694 Builder.defineMacro("__AVX512FP16__"); 695 if (HasAVX512PF) 696 Builder.defineMacro("__AVX512PF__"); 697 if (HasAVX512DQ) 698 Builder.defineMacro("__AVX512DQ__"); 699 if (HasAVX512BITALG) 700 Builder.defineMacro("__AVX512BITALG__"); 701 if (HasAVX512BW) 702 Builder.defineMacro("__AVX512BW__"); 703 if (HasAVX512VL) 704 Builder.defineMacro("__AVX512VL__"); 705 if (HasAVX512VBMI) 706 Builder.defineMacro("__AVX512VBMI__"); 707 if (HasAVX512VBMI2) 708 Builder.defineMacro("__AVX512VBMI2__"); 709 if (HasAVX512IFMA) 710 Builder.defineMacro("__AVX512IFMA__"); 711 if (HasAVX512VP2INTERSECT) 712 Builder.defineMacro("__AVX512VP2INTERSECT__"); 713 if (HasSHA) 714 Builder.defineMacro("__SHA__"); 715 716 if (HasFXSR) 717 Builder.defineMacro("__FXSR__"); 718 if (HasXSAVE) 719 Builder.defineMacro("__XSAVE__"); 720 if (HasXSAVEOPT) 721 Builder.defineMacro("__XSAVEOPT__"); 722 if (HasXSAVEC) 723 Builder.defineMacro("__XSAVEC__"); 724 if (HasXSAVES) 725 Builder.defineMacro("__XSAVES__"); 726 if (HasPKU) 727 Builder.defineMacro("__PKU__"); 728 if (HasCLFLUSHOPT) 729 Builder.defineMacro("__CLFLUSHOPT__"); 730 if (HasCLWB) 731 Builder.defineMacro("__CLWB__"); 732 if (HasWBNOINVD) 733 Builder.defineMacro("__WBNOINVD__"); 734 if (HasSHSTK) 735 Builder.defineMacro("__SHSTK__"); 736 if (HasSGX) 737 Builder.defineMacro("__SGX__"); 738 if (HasPREFETCHWT1) 739 Builder.defineMacro("__PREFETCHWT1__"); 740 if (HasCLZERO) 741 Builder.defineMacro("__CLZERO__"); 742 if (HasKL) 743 Builder.defineMacro("__KL__"); 744 if (HasWIDEKL) 745 Builder.defineMacro("__WIDEKL__"); 746 if (HasRDPID) 747 Builder.defineMacro("__RDPID__"); 748 if (HasRDPRU) 749 Builder.defineMacro("__RDPRU__"); 750 if (HasCLDEMOTE) 751 Builder.defineMacro("__CLDEMOTE__"); 752 if (HasWAITPKG) 753 Builder.defineMacro("__WAITPKG__"); 754 if (HasMOVDIRI) 755 Builder.defineMacro("__MOVDIRI__"); 756 if (HasMOVDIR64B) 757 Builder.defineMacro("__MOVDIR64B__"); 758 if (HasPCONFIG) 759 Builder.defineMacro("__PCONFIG__"); 760 if (HasPTWRITE) 761 Builder.defineMacro("__PTWRITE__"); 762 if (HasINVPCID) 763 Builder.defineMacro("__INVPCID__"); 764 if (HasENQCMD) 765 Builder.defineMacro("__ENQCMD__"); 766 if (HasHRESET) 767 Builder.defineMacro("__HRESET__"); 768 if (HasAMXTILE) 769 Builder.defineMacro("__AMXTILE__"); 770 if (HasAMXINT8) 771 Builder.defineMacro("__AMXINT8__"); 772 if (HasAMXBF16) 773 Builder.defineMacro("__AMXBF16__"); 774 if (HasAVXVNNI) 775 Builder.defineMacro("__AVXVNNI__"); 776 if (HasSERIALIZE) 777 Builder.defineMacro("__SERIALIZE__"); 778 if (HasTSXLDTRK) 779 Builder.defineMacro("__TSXLDTRK__"); 780 if (HasUINTR) 781 Builder.defineMacro("__UINTR__"); 782 if (HasCRC32) 783 Builder.defineMacro("__CRC32__"); 784 785 // Each case falls through to the previous one here. 786 switch (SSELevel) { 787 case AVX512F: 788 Builder.defineMacro("__AVX512F__"); 789 LLVM_FALLTHROUGH; 790 case AVX2: 791 Builder.defineMacro("__AVX2__"); 792 LLVM_FALLTHROUGH; 793 case AVX: 794 Builder.defineMacro("__AVX__"); 795 LLVM_FALLTHROUGH; 796 case SSE42: 797 Builder.defineMacro("__SSE4_2__"); 798 LLVM_FALLTHROUGH; 799 case SSE41: 800 Builder.defineMacro("__SSE4_1__"); 801 LLVM_FALLTHROUGH; 802 case SSSE3: 803 Builder.defineMacro("__SSSE3__"); 804 LLVM_FALLTHROUGH; 805 case SSE3: 806 Builder.defineMacro("__SSE3__"); 807 LLVM_FALLTHROUGH; 808 case SSE2: 809 Builder.defineMacro("__SSE2__"); 810 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 811 LLVM_FALLTHROUGH; 812 case SSE1: 813 Builder.defineMacro("__SSE__"); 814 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 815 LLVM_FALLTHROUGH; 816 case NoSSE: 817 break; 818 } 819 820 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 821 switch (SSELevel) { 822 case AVX512F: 823 case AVX2: 824 case AVX: 825 case SSE42: 826 case SSE41: 827 case SSSE3: 828 case SSE3: 829 case SSE2: 830 Builder.defineMacro("_M_IX86_FP", Twine(2)); 831 break; 832 case SSE1: 833 Builder.defineMacro("_M_IX86_FP", Twine(1)); 834 break; 835 default: 836 Builder.defineMacro("_M_IX86_FP", Twine(0)); 837 break; 838 } 839 } 840 841 // Each case falls through to the previous one here. 842 switch (MMX3DNowLevel) { 843 case AMD3DNowAthlon: 844 Builder.defineMacro("__3dNOW_A__"); 845 LLVM_FALLTHROUGH; 846 case AMD3DNow: 847 Builder.defineMacro("__3dNOW__"); 848 LLVM_FALLTHROUGH; 849 case MMX: 850 Builder.defineMacro("__MMX__"); 851 LLVM_FALLTHROUGH; 852 case NoMMX3DNow: 853 break; 854 } 855 856 if (CPU >= CK_i486 || CPU == CK_None) { 857 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 858 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 859 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 860 } 861 if (HasCX8) 862 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 863 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 864 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 865 866 if (HasFloat128) 867 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 868 } 869 870 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 871 return llvm::StringSwitch<bool>(Name) 872 .Case("3dnow", true) 873 .Case("3dnowa", true) 874 .Case("adx", true) 875 .Case("aes", true) 876 .Case("amx-bf16", true) 877 .Case("amx-int8", true) 878 .Case("amx-tile", true) 879 .Case("avx", true) 880 .Case("avx2", true) 881 .Case("avx512f", true) 882 .Case("avx512cd", true) 883 .Case("avx512vpopcntdq", true) 884 .Case("avx512vnni", true) 885 .Case("avx512bf16", true) 886 .Case("avx512er", true) 887 .Case("avx512fp16", true) 888 .Case("avx512pf", true) 889 .Case("avx512dq", true) 890 .Case("avx512bitalg", true) 891 .Case("avx512bw", true) 892 .Case("avx512vl", true) 893 .Case("avx512vbmi", true) 894 .Case("avx512vbmi2", true) 895 .Case("avx512ifma", true) 896 .Case("avx512vp2intersect", true) 897 .Case("avxvnni", true) 898 .Case("bmi", true) 899 .Case("bmi2", true) 900 .Case("cldemote", true) 901 .Case("clflushopt", true) 902 .Case("clwb", true) 903 .Case("clzero", true) 904 .Case("crc32", true) 905 .Case("cx16", true) 906 .Case("enqcmd", true) 907 .Case("f16c", true) 908 .Case("fma", true) 909 .Case("fma4", true) 910 .Case("fsgsbase", true) 911 .Case("fxsr", true) 912 .Case("general-regs-only", true) 913 .Case("gfni", true) 914 .Case("hreset", true) 915 .Case("invpcid", true) 916 .Case("kl", true) 917 .Case("widekl", true) 918 .Case("lwp", true) 919 .Case("lzcnt", true) 920 .Case("mmx", true) 921 .Case("movbe", true) 922 .Case("movdiri", true) 923 .Case("movdir64b", true) 924 .Case("mwaitx", true) 925 .Case("pclmul", true) 926 .Case("pconfig", true) 927 .Case("pku", true) 928 .Case("popcnt", true) 929 .Case("prefetchwt1", true) 930 .Case("prfchw", true) 931 .Case("ptwrite", true) 932 .Case("rdpid", true) 933 .Case("rdpru", true) 934 .Case("rdrnd", true) 935 .Case("rdseed", true) 936 .Case("rtm", true) 937 .Case("sahf", true) 938 .Case("serialize", true) 939 .Case("sgx", true) 940 .Case("sha", true) 941 .Case("shstk", true) 942 .Case("sse", true) 943 .Case("sse2", true) 944 .Case("sse3", true) 945 .Case("ssse3", true) 946 .Case("sse4", true) 947 .Case("sse4.1", true) 948 .Case("sse4.2", true) 949 .Case("sse4a", true) 950 .Case("tbm", true) 951 .Case("tsxldtrk", true) 952 .Case("uintr", true) 953 .Case("vaes", true) 954 .Case("vpclmulqdq", true) 955 .Case("wbnoinvd", true) 956 .Case("waitpkg", true) 957 .Case("x87", true) 958 .Case("xop", true) 959 .Case("xsave", true) 960 .Case("xsavec", true) 961 .Case("xsaves", true) 962 .Case("xsaveopt", true) 963 .Default(false); 964 } 965 966 bool X86TargetInfo::hasFeature(StringRef Feature) const { 967 return llvm::StringSwitch<bool>(Feature) 968 .Case("adx", HasADX) 969 .Case("aes", HasAES) 970 .Case("amx-bf16", HasAMXBF16) 971 .Case("amx-int8", HasAMXINT8) 972 .Case("amx-tile", HasAMXTILE) 973 .Case("avxvnni", HasAVXVNNI) 974 .Case("avx", SSELevel >= AVX) 975 .Case("avx2", SSELevel >= AVX2) 976 .Case("avx512f", SSELevel >= AVX512F) 977 .Case("avx512cd", HasAVX512CD) 978 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 979 .Case("avx512vnni", HasAVX512VNNI) 980 .Case("avx512bf16", HasAVX512BF16) 981 .Case("avx512er", HasAVX512ER) 982 .Case("avx512fp16", HasAVX512FP16) 983 .Case("avx512pf", HasAVX512PF) 984 .Case("avx512dq", HasAVX512DQ) 985 .Case("avx512bitalg", HasAVX512BITALG) 986 .Case("avx512bw", HasAVX512BW) 987 .Case("avx512vl", HasAVX512VL) 988 .Case("avx512vbmi", HasAVX512VBMI) 989 .Case("avx512vbmi2", HasAVX512VBMI2) 990 .Case("avx512ifma", HasAVX512IFMA) 991 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 992 .Case("bmi", HasBMI) 993 .Case("bmi2", HasBMI2) 994 .Case("cldemote", HasCLDEMOTE) 995 .Case("clflushopt", HasCLFLUSHOPT) 996 .Case("clwb", HasCLWB) 997 .Case("clzero", HasCLZERO) 998 .Case("crc32", HasCRC32) 999 .Case("cx8", HasCX8) 1000 .Case("cx16", HasCX16) 1001 .Case("enqcmd", HasENQCMD) 1002 .Case("f16c", HasF16C) 1003 .Case("fma", HasFMA) 1004 .Case("fma4", XOPLevel >= FMA4) 1005 .Case("fsgsbase", HasFSGSBASE) 1006 .Case("fxsr", HasFXSR) 1007 .Case("gfni", HasGFNI) 1008 .Case("hreset", HasHRESET) 1009 .Case("invpcid", HasINVPCID) 1010 .Case("kl", HasKL) 1011 .Case("widekl", HasWIDEKL) 1012 .Case("lwp", HasLWP) 1013 .Case("lzcnt", HasLZCNT) 1014 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 1015 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 1016 .Case("mmx", MMX3DNowLevel >= MMX) 1017 .Case("movbe", HasMOVBE) 1018 .Case("movdiri", HasMOVDIRI) 1019 .Case("movdir64b", HasMOVDIR64B) 1020 .Case("mwaitx", HasMWAITX) 1021 .Case("pclmul", HasPCLMUL) 1022 .Case("pconfig", HasPCONFIG) 1023 .Case("pku", HasPKU) 1024 .Case("popcnt", HasPOPCNT) 1025 .Case("prefetchwt1", HasPREFETCHWT1) 1026 .Case("prfchw", HasPRFCHW) 1027 .Case("ptwrite", HasPTWRITE) 1028 .Case("rdpid", HasRDPID) 1029 .Case("rdpru", HasRDPRU) 1030 .Case("rdrnd", HasRDRND) 1031 .Case("rdseed", HasRDSEED) 1032 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1033 .Case("rtm", HasRTM) 1034 .Case("sahf", HasLAHFSAHF) 1035 .Case("serialize", HasSERIALIZE) 1036 .Case("sgx", HasSGX) 1037 .Case("sha", HasSHA) 1038 .Case("shstk", HasSHSTK) 1039 .Case("sse", SSELevel >= SSE1) 1040 .Case("sse2", SSELevel >= SSE2) 1041 .Case("sse3", SSELevel >= SSE3) 1042 .Case("ssse3", SSELevel >= SSSE3) 1043 .Case("sse4.1", SSELevel >= SSE41) 1044 .Case("sse4.2", SSELevel >= SSE42) 1045 .Case("sse4a", XOPLevel >= SSE4A) 1046 .Case("tbm", HasTBM) 1047 .Case("tsxldtrk", HasTSXLDTRK) 1048 .Case("uintr", HasUINTR) 1049 .Case("vaes", HasVAES) 1050 .Case("vpclmulqdq", HasVPCLMULQDQ) 1051 .Case("wbnoinvd", HasWBNOINVD) 1052 .Case("waitpkg", HasWAITPKG) 1053 .Case("x86", true) 1054 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1055 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1056 .Case("x87", HasX87) 1057 .Case("xop", XOPLevel >= XOP) 1058 .Case("xsave", HasXSAVE) 1059 .Case("xsavec", HasXSAVEC) 1060 .Case("xsaves", HasXSAVES) 1061 .Case("xsaveopt", HasXSAVEOPT) 1062 .Default(false); 1063 } 1064 1065 // We can't use a generic validation scheme for the features accepted here 1066 // versus subtarget features accepted in the target attribute because the 1067 // bitfield structure that's initialized in the runtime only supports the 1068 // below currently rather than the full range of subtarget features. (See 1069 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1070 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1071 return llvm::StringSwitch<bool>(FeatureStr) 1072 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true) 1073 #include "llvm/Support/X86TargetParser.def" 1074 .Default(false); 1075 } 1076 1077 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1078 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1079 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 1080 .Case(STR, llvm::X86::FEATURE_##ENUM) 1081 1082 #include "llvm/Support/X86TargetParser.def" 1083 ; 1084 // Note, this function should only be used after ensuring the value is 1085 // correct, so it asserts if the value is out of range. 1086 } 1087 1088 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { 1089 // Valid CPUs have a 'key feature' that compares just better than its key 1090 // feature. 1091 using namespace llvm::X86; 1092 CPUKind Kind = parseArchX86(Name); 1093 if (Kind != CK_None) { 1094 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1095 return (getFeaturePriority(KeyFeature) << 1) + 1; 1096 } 1097 1098 // Now we know we have a feature, so get its priority and shift it a few so 1099 // that we have sufficient room for the CPUs (above). 1100 return getFeaturePriority(getFeature(Name)) << 1; 1101 } 1102 1103 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1104 return llvm::StringSwitch<bool>(Name) 1105 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, true) 1106 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, true) 1107 #include "llvm/Support/X86TargetParser.def" 1108 .Default(false); 1109 } 1110 1111 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { 1112 return llvm::StringSwitch<StringRef>(Name) 1113 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, NAME) 1114 #include "llvm/Support/X86TargetParser.def" 1115 .Default(Name); 1116 } 1117 1118 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1119 return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) 1120 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) 1121 #include "llvm/Support/X86TargetParser.def" 1122 .Default(0); 1123 } 1124 1125 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1126 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1127 StringRef WholeList = 1128 llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) 1129 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) 1130 #include "llvm/Support/X86TargetParser.def" 1131 .Default(""); 1132 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); 1133 } 1134 1135 StringRef X86TargetInfo::getCPUSpecificTuneName(StringRef Name) const { 1136 return llvm::StringSwitch<StringRef>(Name) 1137 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, TUNE_NAME) 1138 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, TUNE_NAME) 1139 #include "llvm/Support/X86TargetParser.def" 1140 .Default(""); 1141 } 1142 1143 // We can't use a generic validation scheme for the cpus accepted here 1144 // versus subtarget cpus accepted in the target attribute because the 1145 // variables intitialized by the runtime only support the below currently 1146 // rather than the full range of cpus. 1147 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1148 return llvm::StringSwitch<bool>(FeatureStr) 1149 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1150 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1151 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1152 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1153 #include "llvm/Support/X86TargetParser.def" 1154 .Default(false); 1155 } 1156 1157 static unsigned matchAsmCCConstraint(const char *&Name) { 1158 auto RV = llvm::StringSwitch<unsigned>(Name) 1159 .Case("@cca", 4) 1160 .Case("@ccae", 5) 1161 .Case("@ccb", 4) 1162 .Case("@ccbe", 5) 1163 .Case("@ccc", 4) 1164 .Case("@cce", 4) 1165 .Case("@ccz", 4) 1166 .Case("@ccg", 4) 1167 .Case("@ccge", 5) 1168 .Case("@ccl", 4) 1169 .Case("@ccle", 5) 1170 .Case("@ccna", 5) 1171 .Case("@ccnae", 6) 1172 .Case("@ccnb", 5) 1173 .Case("@ccnbe", 6) 1174 .Case("@ccnc", 5) 1175 .Case("@ccne", 5) 1176 .Case("@ccnz", 5) 1177 .Case("@ccng", 5) 1178 .Case("@ccnge", 6) 1179 .Case("@ccnl", 5) 1180 .Case("@ccnle", 6) 1181 .Case("@ccno", 5) 1182 .Case("@ccnp", 5) 1183 .Case("@ccns", 5) 1184 .Case("@cco", 4) 1185 .Case("@ccp", 4) 1186 .Case("@ccs", 4) 1187 .Default(0); 1188 return RV; 1189 } 1190 1191 bool X86TargetInfo::validateAsmConstraint( 1192 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1193 switch (*Name) { 1194 default: 1195 return false; 1196 // Constant constraints. 1197 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1198 // instructions. 1199 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1200 // x86_64 instructions. 1201 case 's': 1202 Info.setRequiresImmediate(); 1203 return true; 1204 case 'I': 1205 Info.setRequiresImmediate(0, 31); 1206 return true; 1207 case 'J': 1208 Info.setRequiresImmediate(0, 63); 1209 return true; 1210 case 'K': 1211 Info.setRequiresImmediate(-128, 127); 1212 return true; 1213 case 'L': 1214 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1215 return true; 1216 case 'M': 1217 Info.setRequiresImmediate(0, 3); 1218 return true; 1219 case 'N': 1220 Info.setRequiresImmediate(0, 255); 1221 return true; 1222 case 'O': 1223 Info.setRequiresImmediate(0, 127); 1224 return true; 1225 // Register constraints. 1226 case 'Y': // 'Y' is the first character for several 2-character constraints. 1227 // Shift the pointer to the second character of the constraint. 1228 Name++; 1229 switch (*Name) { 1230 default: 1231 return false; 1232 case 'z': // First SSE register. 1233 case '2': 1234 case 't': // Any SSE register, when SSE2 is enabled. 1235 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1236 case 'm': // Any MMX register, when inter-unit moves enabled. 1237 case 'k': // AVX512 arch mask registers: k1-k7. 1238 Info.setAllowsRegister(); 1239 return true; 1240 } 1241 case 'f': // Any x87 floating point stack register. 1242 // Constraint 'f' cannot be used for output operands. 1243 if (Info.ConstraintStr[0] == '=') 1244 return false; 1245 Info.setAllowsRegister(); 1246 return true; 1247 case 'a': // eax. 1248 case 'b': // ebx. 1249 case 'c': // ecx. 1250 case 'd': // edx. 1251 case 'S': // esi. 1252 case 'D': // edi. 1253 case 'A': // edx:eax. 1254 case 't': // Top of floating point stack. 1255 case 'u': // Second from top of floating point stack. 1256 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1257 case 'y': // Any MMX register. 1258 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1259 case 'x': // Any SSE register. 1260 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1261 // for intermideate k reg operations). 1262 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1263 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1264 case 'l': // "Index" registers: any general register that can be used as an 1265 // index in a base+index memory access. 1266 Info.setAllowsRegister(); 1267 return true; 1268 // Floating point constant constraints. 1269 case 'C': // SSE floating point constant. 1270 case 'G': // x87 floating point constant. 1271 return true; 1272 case '@': 1273 // CC condition changes. 1274 if (auto Len = matchAsmCCConstraint(Name)) { 1275 Name += Len - 1; 1276 Info.setAllowsRegister(); 1277 return true; 1278 } 1279 return false; 1280 } 1281 } 1282 1283 // Below is based on the following information: 1284 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1285 // | Processor Name | Cache Line Size (Bytes) | Source | 1286 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1287 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1288 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1289 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1290 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1291 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1292 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1293 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1294 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1295 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1296 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1297 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1298 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1299 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1300 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1301 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1302 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1303 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1304 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1305 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1306 using namespace llvm::X86; 1307 switch (CPU) { 1308 // i386 1309 case CK_i386: 1310 // i486 1311 case CK_i486: 1312 case CK_WinChipC6: 1313 case CK_WinChip2: 1314 case CK_C3: 1315 // Lakemont 1316 case CK_Lakemont: 1317 return 16; 1318 1319 // i586 1320 case CK_i586: 1321 case CK_Pentium: 1322 case CK_PentiumMMX: 1323 // i686 1324 case CK_PentiumPro: 1325 case CK_i686: 1326 case CK_Pentium2: 1327 case CK_Pentium3: 1328 case CK_PentiumM: 1329 case CK_C3_2: 1330 // K6 1331 case CK_K6: 1332 case CK_K6_2: 1333 case CK_K6_3: 1334 // Geode 1335 case CK_Geode: 1336 return 32; 1337 1338 // Netburst 1339 case CK_Pentium4: 1340 case CK_Prescott: 1341 case CK_Nocona: 1342 // Atom 1343 case CK_Bonnell: 1344 case CK_Silvermont: 1345 case CK_Goldmont: 1346 case CK_GoldmontPlus: 1347 case CK_Tremont: 1348 1349 case CK_Westmere: 1350 case CK_SandyBridge: 1351 case CK_IvyBridge: 1352 case CK_Haswell: 1353 case CK_Broadwell: 1354 case CK_SkylakeClient: 1355 case CK_SkylakeServer: 1356 case CK_Cascadelake: 1357 case CK_Nehalem: 1358 case CK_Cooperlake: 1359 case CK_Cannonlake: 1360 case CK_Tigerlake: 1361 case CK_SapphireRapids: 1362 case CK_IcelakeClient: 1363 case CK_Rocketlake: 1364 case CK_IcelakeServer: 1365 case CK_Alderlake: 1366 case CK_KNL: 1367 case CK_KNM: 1368 // K7 1369 case CK_Athlon: 1370 case CK_AthlonXP: 1371 // K8 1372 case CK_K8: 1373 case CK_K8SSE3: 1374 case CK_AMDFAM10: 1375 // Bobcat 1376 case CK_BTVER1: 1377 case CK_BTVER2: 1378 // Bulldozer 1379 case CK_BDVER1: 1380 case CK_BDVER2: 1381 case CK_BDVER3: 1382 case CK_BDVER4: 1383 // Zen 1384 case CK_ZNVER1: 1385 case CK_ZNVER2: 1386 case CK_ZNVER3: 1387 // Deprecated 1388 case CK_x86_64: 1389 case CK_x86_64_v2: 1390 case CK_x86_64_v3: 1391 case CK_x86_64_v4: 1392 case CK_Yonah: 1393 case CK_Penryn: 1394 case CK_Core2: 1395 return 64; 1396 1397 // The following currently have unknown cache line sizes (but they are probably all 64): 1398 // Core 1399 case CK_None: 1400 return None; 1401 } 1402 llvm_unreachable("Unknown CPU kind"); 1403 } 1404 1405 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1406 StringRef Constraint, 1407 unsigned Size) const { 1408 // Strip off constraint modifiers. 1409 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 1410 Constraint = Constraint.substr(1); 1411 1412 return validateOperandSize(FeatureMap, Constraint, Size); 1413 } 1414 1415 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1416 StringRef Constraint, 1417 unsigned Size) const { 1418 return validateOperandSize(FeatureMap, Constraint, Size); 1419 } 1420 1421 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1422 StringRef Constraint, 1423 unsigned Size) const { 1424 switch (Constraint[0]) { 1425 default: 1426 break; 1427 case 'k': 1428 // Registers k0-k7 (AVX512) size limit is 64 bit. 1429 case 'y': 1430 return Size <= 64; 1431 case 'f': 1432 case 't': 1433 case 'u': 1434 return Size <= 128; 1435 case 'Y': 1436 // 'Y' is the first character for several 2-character constraints. 1437 switch (Constraint[1]) { 1438 default: 1439 return false; 1440 case 'm': 1441 // 'Ym' is synonymous with 'y'. 1442 case 'k': 1443 return Size <= 64; 1444 case 'z': 1445 // XMM0/YMM/ZMM0 1446 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1447 // ZMM0 can be used if target supports AVX512F. 1448 return Size <= 512U; 1449 else if (hasFeatureEnabled(FeatureMap, "avx")) 1450 // YMM0 can be used if target supports AVX. 1451 return Size <= 256U; 1452 else if (hasFeatureEnabled(FeatureMap, "sse")) 1453 return Size <= 128U; 1454 return false; 1455 case 'i': 1456 case 't': 1457 case '2': 1458 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1459 if (SSELevel < SSE2) 1460 return false; 1461 break; 1462 } 1463 break; 1464 case 'v': 1465 case 'x': 1466 if (hasFeatureEnabled(FeatureMap, "avx512f")) 1467 // 512-bit zmm registers can be used if target supports AVX512F. 1468 return Size <= 512U; 1469 else if (hasFeatureEnabled(FeatureMap, "avx")) 1470 // 256-bit ymm registers can be used if target supports AVX. 1471 return Size <= 256U; 1472 return Size <= 128U; 1473 1474 } 1475 1476 return true; 1477 } 1478 1479 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1480 switch (*Constraint) { 1481 case '@': 1482 if (auto Len = matchAsmCCConstraint(Constraint)) { 1483 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1484 Constraint += Len - 1; 1485 return Converted; 1486 } 1487 return std::string(1, *Constraint); 1488 case 'a': 1489 return std::string("{ax}"); 1490 case 'b': 1491 return std::string("{bx}"); 1492 case 'c': 1493 return std::string("{cx}"); 1494 case 'd': 1495 return std::string("{dx}"); 1496 case 'S': 1497 return std::string("{si}"); 1498 case 'D': 1499 return std::string("{di}"); 1500 case 'p': // Keep 'p' constraint (address). 1501 return std::string("p"); 1502 case 't': // top of floating point stack. 1503 return std::string("{st}"); 1504 case 'u': // second from top of floating point stack. 1505 return std::string("{st(1)}"); // second from top of floating point stack. 1506 case 'Y': 1507 switch (Constraint[1]) { 1508 default: 1509 // Break from inner switch and fall through (copy single char), 1510 // continue parsing after copying the current constraint into 1511 // the return string. 1512 break; 1513 case 'k': 1514 case 'm': 1515 case 'i': 1516 case 't': 1517 case 'z': 1518 case '2': 1519 // "^" hints llvm that this is a 2 letter constraint. 1520 // "Constraint++" is used to promote the string iterator 1521 // to the next constraint. 1522 return std::string("^") + std::string(Constraint++, 2); 1523 } 1524 LLVM_FALLTHROUGH; 1525 default: 1526 return std::string(1, *Constraint); 1527 } 1528 } 1529 1530 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1531 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1532 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1533 } 1534 1535 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1536 llvm::X86::fillValidTuneCPUList(Values); 1537 } 1538 1539 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1540 return llvm::makeArrayRef(GCCRegNames); 1541 } 1542 1543 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1544 return llvm::makeArrayRef(AddlRegNames); 1545 } 1546 1547 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1548 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1549 Builtin::FirstTSBuiltin + 1); 1550 } 1551 1552 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1553 return llvm::makeArrayRef(BuiltinInfoX86, 1554 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1555 } 1556