1*fe6060f1SDimitry Andric //===----------------------------------------------------------------------===// 2*fe6060f1SDimitry Andric // 3*fe6060f1SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*fe6060f1SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*fe6060f1SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*fe6060f1SDimitry Andric // 7*fe6060f1SDimitry Andric //===----------------------------------------------------------------------===// 8*fe6060f1SDimitry Andric 9*fe6060f1SDimitry Andric #ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_ 10*fe6060f1SDimitry Andric #define _HEXAGON_CIRC_BREV_INTRINSICS_H_ 1 11*fe6060f1SDimitry Andric 12*fe6060f1SDimitry Andric #include <hexagon_protos.h> 13*fe6060f1SDimitry Andric #include <stdint.h> 14*fe6060f1SDimitry Andric 15*fe6060f1SDimitry Andric /* Circular Load */ 16*fe6060f1SDimitry Andric /* ========================================================================== 17*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 18*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_circ_load_update_D(Word64 dst, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) 19*fe6060f1SDimitry Andric Instruction Type: InstructionType 20*fe6060f1SDimitry Andric Execution Slots: SLOT0123 21*fe6060f1SDimitry Andric ========================================================================== */ 22*fe6060f1SDimitry Andric #define Q6_circ_load_update_D(dest,ptr,incr,bufsize,K) \ 23*fe6060f1SDimitry Andric { ptr = (int64_t *) HEXAGON_circ_ldd (ptr, &(dest), ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); } 24*fe6060f1SDimitry Andric 25*fe6060f1SDimitry Andric /* ========================================================================== 26*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 27*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_circ_load_update_W(Word32 dst, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) 28*fe6060f1SDimitry Andric Instruction Type: InstructionType 29*fe6060f1SDimitry Andric Execution Slots: SLOT0123 30*fe6060f1SDimitry Andric ========================================================================== */ 31*fe6060f1SDimitry Andric #define Q6_circ_load_update_W(dest,ptr,incr,bufsize,K) \ 32*fe6060f1SDimitry Andric { ptr = (int *) HEXAGON_circ_ldw (ptr, &(dest), (((K)<<24)|((bufsize)<<2)), ((incr)*4)); } 33*fe6060f1SDimitry Andric 34*fe6060f1SDimitry Andric /* ========================================================================== 35*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 36*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_circ_load_update_H(Word16 dst, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) 37*fe6060f1SDimitry Andric Instruction Type: InstructionType 38*fe6060f1SDimitry Andric Execution Slots: SLOT0123 39*fe6060f1SDimitry Andric ========================================================================== */ 40*fe6060f1SDimitry Andric #define Q6_circ_load_update_H(dest,ptr,incr,bufsize,K) \ 41*fe6060f1SDimitry Andric { ptr = (int16_t *) HEXAGON_circ_ldh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } 42*fe6060f1SDimitry Andric 43*fe6060f1SDimitry Andric /* ========================================================================== 44*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 45*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_circ_load_update_UH( UWord16 dst, UWord16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) 46*fe6060f1SDimitry Andric Instruction Type: InstructionType 47*fe6060f1SDimitry Andric Execution Slots: SLOT0123 48*fe6060f1SDimitry Andric ========================================================================== */ 49*fe6060f1SDimitry Andric #define Q6_circ_load_update_UH(dest,ptr,incr,bufsize,K) \ 50*fe6060f1SDimitry Andric { ptr = (uint16_t *) HEXAGON_circ_lduh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } 51*fe6060f1SDimitry Andric 52*fe6060f1SDimitry Andric /* ========================================================================== 53*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 54*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_circ_load_update_B(Word8 dst, Word8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) 55*fe6060f1SDimitry Andric Instruction Type: InstructionType 56*fe6060f1SDimitry Andric Execution Slots: SLOT0123 57*fe6060f1SDimitry Andric ========================================================================== */ 58*fe6060f1SDimitry Andric #define Q6_circ_load_update_B(dest,ptr,incr,bufsize,K) \ 59*fe6060f1SDimitry Andric { ptr = (int8_t *) HEXAGON_circ_ldb (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); } 60*fe6060f1SDimitry Andric 61*fe6060f1SDimitry Andric /* ========================================================================== 62*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 63*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_circ_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) 64*fe6060f1SDimitry Andric Instruction Type: InstructionType 65*fe6060f1SDimitry Andric Execution Slots: SLOT0123 66*fe6060f1SDimitry Andric ========================================================================== */ 67*fe6060f1SDimitry Andric #define Q6_circ_load_update_UB(dest,ptr,incr,bufsize,K) \ 68*fe6060f1SDimitry Andric { ptr = (uint8_t *) HEXAGON_circ_ldub (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); } 69*fe6060f1SDimitry Andric 70*fe6060f1SDimitry Andric /* Circular Store */ 71*fe6060f1SDimitry Andric /* ========================================================================== 72*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 73*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_circ_store_update_D(Word64 *src, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) 74*fe6060f1SDimitry Andric Instruction Type: InstructionType 75*fe6060f1SDimitry Andric Execution Slots: SLOT0123 76*fe6060f1SDimitry Andric ========================================================================== */ 77*fe6060f1SDimitry Andric #define Q6_circ_store_update_D(src,ptr,incr,bufsize,K) \ 78*fe6060f1SDimitry Andric { ptr = (int64_t *) HEXAGON_circ_std (ptr, src, ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); } 79*fe6060f1SDimitry Andric 80*fe6060f1SDimitry Andric /* ========================================================================== 81*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 82*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_circ_store_update_W(Word32 *src, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) 83*fe6060f1SDimitry Andric Instruction Type: InstructionType 84*fe6060f1SDimitry Andric Execution Slots: SLOT0123 85*fe6060f1SDimitry Andric ========================================================================== */ 86*fe6060f1SDimitry Andric #define Q6_circ_store_update_W(src,ptr,incr,bufsize,K) \ 87*fe6060f1SDimitry Andric { ptr = (int *) HEXAGON_circ_stw (ptr, src, (((K)<<24)|((bufsize)<<2)), ((incr)*4)); } 88*fe6060f1SDimitry Andric 89*fe6060f1SDimitry Andric /* ========================================================================== 90*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 91*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_circ_store_update_HL(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) 92*fe6060f1SDimitry Andric Instruction Type: InstructionType 93*fe6060f1SDimitry Andric Execution Slots: SLOT0123 94*fe6060f1SDimitry Andric ========================================================================== */ 95*fe6060f1SDimitry Andric #define Q6_circ_store_update_HL(src,ptr,incr,bufsize,K) \ 96*fe6060f1SDimitry Andric { ptr = (int16_t *) HEXAGON_circ_sth (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } 97*fe6060f1SDimitry Andric 98*fe6060f1SDimitry Andric /* ========================================================================== 99*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 100*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_circ_store_update_HH(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) 101*fe6060f1SDimitry Andric Instruction Type: InstructionType 102*fe6060f1SDimitry Andric Execution Slots: SLOT0123 103*fe6060f1SDimitry Andric ========================================================================== */ 104*fe6060f1SDimitry Andric #define Q6_circ_store_update_HH(src,ptr,incr,bufsize,K) \ 105*fe6060f1SDimitry Andric { ptr = (int16_t *) HEXAGON_circ_sthhi (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); } 106*fe6060f1SDimitry Andric 107*fe6060f1SDimitry Andric /* ========================================================================== 108*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 109*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_circ_store_update_B(Word8 *src, Word8 *ptr, UWord32 I4, UWord32 bufsize, UWord64 K) 110*fe6060f1SDimitry Andric Instruction Type: InstructionType 111*fe6060f1SDimitry Andric Execution Slots: SLOT0123 112*fe6060f1SDimitry Andric ========================================================================== */ 113*fe6060f1SDimitry Andric #define Q6_circ_store_update_B(src,ptr,incr,bufsize,K) \ 114*fe6060f1SDimitry Andric { ptr = (int8_t *) HEXAGON_circ_stb (ptr, src, ((((K)-2)<<24)|(bufsize)), incr); } 115*fe6060f1SDimitry Andric 116*fe6060f1SDimitry Andric 117*fe6060f1SDimitry Andric /* Bit Reverse Load */ 118*fe6060f1SDimitry Andric /* ========================================================================== 119*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 120*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_bitrev_load_update_D(Word64 dst, Word64 *ptr, UWord32 Iu4) 121*fe6060f1SDimitry Andric Instruction Type: InstructionType 122*fe6060f1SDimitry Andric Execution Slots: SLOT0123 123*fe6060f1SDimitry Andric ========================================================================== */ 124*fe6060f1SDimitry Andric #define Q6_bitrev_load_update_D(dest,ptr,log2bufsize) \ 125*fe6060f1SDimitry Andric { ptr = (int64_t *) HEXAGON_brev_ldd (ptr, &(dest), (1<<(16-((log2bufsize) + 3)))); } 126*fe6060f1SDimitry Andric 127*fe6060f1SDimitry Andric /* ========================================================================== 128*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 129*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_bitrev_load_update_W(Word32 dst, Word32 *ptr, UWord32 Iu4) 130*fe6060f1SDimitry Andric Instruction Type: InstructionType 131*fe6060f1SDimitry Andric Execution Slots: SLOT0123 132*fe6060f1SDimitry Andric ========================================================================== */ 133*fe6060f1SDimitry Andric #define Q6_bitrev_load_update_W(dest,ptr,log2bufsize) \ 134*fe6060f1SDimitry Andric { ptr = (int *) HEXAGON_brev_ldw (ptr, &(dest), (1<<(16-((log2bufsize) + 2)))); } 135*fe6060f1SDimitry Andric 136*fe6060f1SDimitry Andric /* ========================================================================== 137*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 138*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_bitrev_load_update_H(Word16 dst, Word16 *ptr, UWord32 Iu4) 139*fe6060f1SDimitry Andric Instruction Type: InstructionType 140*fe6060f1SDimitry Andric Execution Slots: SLOT0123 141*fe6060f1SDimitry Andric ========================================================================== */ 142*fe6060f1SDimitry Andric #define Q6_bitrev_load_update_H(dest,ptr,log2bufsize) \ 143*fe6060f1SDimitry Andric { ptr = (int16_t *) HEXAGON_brev_ldh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); } 144*fe6060f1SDimitry Andric 145*fe6060f1SDimitry Andric /* ========================================================================== 146*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 147*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_bitrev_load_update_UH(UWord16 dst, UWord16 *ptr, UWord32 Iu4) 148*fe6060f1SDimitry Andric Instruction Type: InstructionType 149*fe6060f1SDimitry Andric Execution Slots: SLOT0123 150*fe6060f1SDimitry Andric ========================================================================== */ 151*fe6060f1SDimitry Andric #define Q6_bitrev_load_update_UH(dest,ptr,log2bufsize) \ 152*fe6060f1SDimitry Andric { ptr = (uint16_t *) HEXAGON_brev_lduh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); } 153*fe6060f1SDimitry Andric 154*fe6060f1SDimitry Andric /* ========================================================================== 155*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 156*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_bitrev_load_update_B(Word8 dst, Word8 *ptr, UWord32 Iu4) 157*fe6060f1SDimitry Andric Instruction Type: InstructionType 158*fe6060f1SDimitry Andric Execution Slots: SLOT0123 159*fe6060f1SDimitry Andric ========================================================================== */ 160*fe6060f1SDimitry Andric #define Q6_bitrev_load_update_B(dest,ptr,log2bufsize) \ 161*fe6060f1SDimitry Andric { ptr = (int8_t *) HEXAGON_brev_ldb (ptr, &(dest), (1<<(16-((log2bufsize))))); } 162*fe6060f1SDimitry Andric 163*fe6060f1SDimitry Andric /* ========================================================================== 164*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 165*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_bitrev_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 Iu4) 166*fe6060f1SDimitry Andric Instruction Type: InstructionType 167*fe6060f1SDimitry Andric Execution Slots: SLOT0123 168*fe6060f1SDimitry Andric ========================================================================== */ 169*fe6060f1SDimitry Andric #define Q6_bitrev_load_update_UB(dest,ptr,log2bufsize) \ 170*fe6060f1SDimitry Andric { ptr = (uint8_t *) HEXAGON_brev_ldub (ptr, &(dest), (1<<(16-((log2bufsize))))); } 171*fe6060f1SDimitry Andric 172*fe6060f1SDimitry Andric /* Bit Reverse Store */ 173*fe6060f1SDimitry Andric 174*fe6060f1SDimitry Andric /* ========================================================================== 175*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 176*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_bitrev_store_update_D(Word64 *src, Word64 *ptr, UWord32 Iu4) 177*fe6060f1SDimitry Andric Instruction Type: InstructionType 178*fe6060f1SDimitry Andric Execution Slots: SLOT0123 179*fe6060f1SDimitry Andric ========================================================================== */ 180*fe6060f1SDimitry Andric #define Q6_bitrev_store_update_D(src,ptr,log2bufsize) \ 181*fe6060f1SDimitry Andric { ptr = (int64_t *) HEXAGON_brev_std (ptr, src, (1<<(16-((log2bufsize) + 3)))); } 182*fe6060f1SDimitry Andric 183*fe6060f1SDimitry Andric /* ========================================================================== 184*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 185*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_bitrev_store_update_W(Word32 *src, Word32 *ptr, UWord32 Iu4) 186*fe6060f1SDimitry Andric Instruction Type: InstructionType 187*fe6060f1SDimitry Andric Execution Slots: SLOT0123 188*fe6060f1SDimitry Andric ========================================================================== */ 189*fe6060f1SDimitry Andric #define Q6_bitrev_store_update_W(src,ptr,log2bufsize) \ 190*fe6060f1SDimitry Andric { ptr = (int *) HEXAGON_brev_stw (ptr, src, (1<<(16-((log2bufsize) + 2)))); } 191*fe6060f1SDimitry Andric 192*fe6060f1SDimitry Andric /* ========================================================================== 193*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 194*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_bitrev_store_update_HL(Word16 *src, Word16 *ptr, Word32 Iu4) 195*fe6060f1SDimitry Andric Instruction Type: InstructionType 196*fe6060f1SDimitry Andric Execution Slots: SLOT0123 197*fe6060f1SDimitry Andric ========================================================================== */ 198*fe6060f1SDimitry Andric #define Q6_bitrev_store_update_HL(src,ptr,log2bufsize) \ 199*fe6060f1SDimitry Andric { ptr = (int16_t *) HEXAGON_brev_sth (ptr, src, (1<<(16-((log2bufsize) + 1)))); } 200*fe6060f1SDimitry Andric 201*fe6060f1SDimitry Andric /* ========================================================================== 202*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 203*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_bitrev_store_update_HH(Word16 *src, Word16 *ptr, UWord32 Iu4) 204*fe6060f1SDimitry Andric Instruction Type: InstructionType 205*fe6060f1SDimitry Andric Execution Slots: SLOT0123 206*fe6060f1SDimitry Andric ========================================================================== */ 207*fe6060f1SDimitry Andric #define Q6_bitrev_store_update_HH(src,ptr,log2bufsize) \ 208*fe6060f1SDimitry Andric { ptr = (int16_t *) HEXAGON_brev_sthhi (ptr, src, (1<<(16-((log2bufsize) + 1)))); } 209*fe6060f1SDimitry Andric 210*fe6060f1SDimitry Andric /* ========================================================================== 211*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 212*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_bitrev_store_update_B(Word8 *src, Word8 *ptr, UWord32 Iu4) 213*fe6060f1SDimitry Andric Instruction Type: InstructionType 214*fe6060f1SDimitry Andric Execution Slots: SLOT0123 215*fe6060f1SDimitry Andric ========================================================================== */ 216*fe6060f1SDimitry Andric #define Q6_bitrev_store_update_B(src,ptr,log2bufsize) \ 217*fe6060f1SDimitry Andric { ptr = (int8_t *) HEXAGON_brev_stb (ptr, src, (1<<(16-((log2bufsize))))); } 218*fe6060f1SDimitry Andric 219*fe6060f1SDimitry Andric 220*fe6060f1SDimitry Andric #define HEXAGON_circ_ldd __builtin_circ_ldd 221*fe6060f1SDimitry Andric #define HEXAGON_circ_ldw __builtin_circ_ldw 222*fe6060f1SDimitry Andric #define HEXAGON_circ_ldh __builtin_circ_ldh 223*fe6060f1SDimitry Andric #define HEXAGON_circ_lduh __builtin_circ_lduh 224*fe6060f1SDimitry Andric #define HEXAGON_circ_ldb __builtin_circ_ldb 225*fe6060f1SDimitry Andric #define HEXAGON_circ_ldub __builtin_circ_ldub 226*fe6060f1SDimitry Andric 227*fe6060f1SDimitry Andric 228*fe6060f1SDimitry Andric #define HEXAGON_circ_std __builtin_circ_std 229*fe6060f1SDimitry Andric #define HEXAGON_circ_stw __builtin_circ_stw 230*fe6060f1SDimitry Andric #define HEXAGON_circ_sth __builtin_circ_sth 231*fe6060f1SDimitry Andric #define HEXAGON_circ_sthhi __builtin_circ_sthhi 232*fe6060f1SDimitry Andric #define HEXAGON_circ_stb __builtin_circ_stb 233*fe6060f1SDimitry Andric 234*fe6060f1SDimitry Andric 235*fe6060f1SDimitry Andric #define HEXAGON_brev_ldd __builtin_brev_ldd 236*fe6060f1SDimitry Andric #define HEXAGON_brev_ldw __builtin_brev_ldw 237*fe6060f1SDimitry Andric #define HEXAGON_brev_ldh __builtin_brev_ldh 238*fe6060f1SDimitry Andric #define HEXAGON_brev_lduh __builtin_brev_lduh 239*fe6060f1SDimitry Andric #define HEXAGON_brev_ldb __builtin_brev_ldb 240*fe6060f1SDimitry Andric #define HEXAGON_brev_ldub __builtin_brev_ldub 241*fe6060f1SDimitry Andric 242*fe6060f1SDimitry Andric #define HEXAGON_brev_std __builtin_brev_std 243*fe6060f1SDimitry Andric #define HEXAGON_brev_stw __builtin_brev_stw 244*fe6060f1SDimitry Andric #define HEXAGON_brev_sth __builtin_brev_sth 245*fe6060f1SDimitry Andric #define HEXAGON_brev_sthhi __builtin_brev_sthhi 246*fe6060f1SDimitry Andric #define HEXAGON_brev_stb __builtin_brev_stb 247*fe6060f1SDimitry Andric 248*fe6060f1SDimitry Andric #ifdef __HVX__ 249*fe6060f1SDimitry Andric /* ========================================================================== 250*fe6060f1SDimitry Andric Assembly Syntax: if (Qt) vmem(Rt+#0) = Vs 251*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vmaskedstoreq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) 252*fe6060f1SDimitry Andric Instruction Type: COPROC_VMEM 253*fe6060f1SDimitry Andric Execution Slots: SLOT0 254*fe6060f1SDimitry Andric ========================================================================== */ 255*fe6060f1SDimitry Andric 256*fe6060f1SDimitry Andric #define Q6_vmaskedstoreq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstoreq) 257*fe6060f1SDimitry Andric 258*fe6060f1SDimitry Andric /* ========================================================================== 259*fe6060f1SDimitry Andric Assembly Syntax: if (!Qt) vmem(Rt+#0) = Vs 260*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vmaskedstorenq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) 261*fe6060f1SDimitry Andric Instruction Type: COPROC_VMEM 262*fe6060f1SDimitry Andric Execution Slots: SLOT0 263*fe6060f1SDimitry Andric ========================================================================== */ 264*fe6060f1SDimitry Andric 265*fe6060f1SDimitry Andric #define Q6_vmaskedstorenq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorenq) 266*fe6060f1SDimitry Andric 267*fe6060f1SDimitry Andric /* ========================================================================== 268*fe6060f1SDimitry Andric Assembly Syntax: if (Qt) vmem(Rt+#0):nt = Vs 269*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vmaskedstorentq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) 270*fe6060f1SDimitry Andric Instruction Type: COPROC_VMEM 271*fe6060f1SDimitry Andric Execution Slots: SLOT0 272*fe6060f1SDimitry Andric ========================================================================== */ 273*fe6060f1SDimitry Andric 274*fe6060f1SDimitry Andric #define Q6_vmaskedstorentq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentq) 275*fe6060f1SDimitry Andric 276*fe6060f1SDimitry Andric /* ========================================================================== 277*fe6060f1SDimitry Andric Assembly Syntax: if (!Qt) vmem(Rt+#0):nt = Vs 278*fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vmaskedstorentnq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs) 279*fe6060f1SDimitry Andric Instruction Type: COPROC_VMEM 280*fe6060f1SDimitry Andric Execution Slots: SLOT0 281*fe6060f1SDimitry Andric ========================================================================== */ 282*fe6060f1SDimitry Andric 283*fe6060f1SDimitry Andric #define Q6_vmaskedstorentnq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentnq) 284*fe6060f1SDimitry Andric 285*fe6060f1SDimitry Andric #endif 286*fe6060f1SDimitry Andric 287*fe6060f1SDimitry Andric 288*fe6060f1SDimitry Andric #endif /* #ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_ */ 289*fe6060f1SDimitry Andric 290*fe6060f1SDimitry Andric #ifdef __NOT_DEFINED__ 291*fe6060f1SDimitry Andric /*** comment block template ***/ 292*fe6060f1SDimitry Andric /* ========================================================================== 293*fe6060f1SDimitry Andric Assembly Syntax: Return=instruction() 294*fe6060f1SDimitry Andric C Intrinsic Prototype: ReturnType Intrinsic(ParamType Rs, ParamType Rt) 295*fe6060f1SDimitry Andric Instruction Type: InstructionType 296*fe6060f1SDimitry Andric Execution Slots: SLOT0123 297*fe6060f1SDimitry Andric ========================================================================== */ 298*fe6060f1SDimitry Andric #endif /*** __NOT_DEFINED__ ***/ 299