1 //===-- ABIX86.cpp --------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifdef LLDB_ENABLE_ALL 10 #include "ABIMacOSX_i386.h" 11 #endif // LLDB_ENABLE_ALL 12 #include "ABISysV_i386.h" 13 #include "ABISysV_x86_64.h" 14 #ifdef LLDB_ENABLE_ALL 15 #include "ABIWindows_x86_64.h" 16 #endif // LLDB_ENABLE_ALL 17 #include "ABIX86.h" 18 #include "lldb/Core/PluginManager.h" 19 #include "lldb/Target/Process.h" 20 #include <optional> 21 22 using namespace lldb; 23 using namespace lldb_private; 24 25 LLDB_PLUGIN_DEFINE(ABIX86) 26 27 void ABIX86::Initialize() { 28 #ifdef LLDB_ENABLE_ALL 29 ABIMacOSX_i386::Initialize(); 30 #endif // LLDB_ENABLE_ALL 31 ABISysV_i386::Initialize(); 32 ABISysV_x86_64::Initialize(); 33 #ifdef LLDB_ENABLE_ALL 34 ABIWindows_x86_64::Initialize(); 35 #endif // LLDB_ENABLE_ALL 36 } 37 38 void ABIX86::Terminate() { 39 #ifdef LLDB_ENABLE_ALL 40 ABIMacOSX_i386::Terminate(); 41 #endif // LLDB_ENABLE_ALL 42 ABISysV_i386::Terminate(); 43 ABISysV_x86_64::Terminate(); 44 #ifdef LLDB_ENABLE_ALL 45 ABIWindows_x86_64::Terminate(); 46 #endif // LLDB_ENABLE_ALL 47 } 48 49 namespace { 50 enum RegKind { 51 GPR32, 52 GPR16, 53 GPR8h, 54 GPR8, 55 MM, 56 YMM_YMMh, 57 YMM_XMM, 58 59 RegKindCount 60 }; 61 } 62 63 struct RegData { 64 RegKind subreg_kind; 65 llvm::StringRef subreg_name; 66 std::optional<uint32_t> base_index; 67 }; 68 69 static void 70 addPartialRegisters(std::vector<DynamicRegisterInfo::Register> ®s, 71 llvm::ArrayRef<RegData *> subregs, uint32_t base_size, 72 lldb::Encoding encoding, lldb::Format format, 73 uint32_t subreg_size, uint32_t subreg_offset = 0) { 74 for (const RegData *subreg : subregs) { 75 assert(subreg); 76 uint32_t base_index = *subreg->base_index; 77 DynamicRegisterInfo::Register &full_reg = regs[base_index]; 78 if (full_reg.byte_size != base_size) 79 continue; 80 81 lldb_private::DynamicRegisterInfo::Register new_reg{ 82 lldb_private::ConstString(subreg->subreg_name), 83 lldb_private::ConstString(), 84 lldb_private::ConstString("supplementary registers"), 85 subreg_size, 86 LLDB_INVALID_INDEX32, 87 encoding, 88 format, 89 LLDB_INVALID_REGNUM, 90 LLDB_INVALID_REGNUM, 91 LLDB_INVALID_REGNUM, 92 LLDB_INVALID_REGNUM, 93 {base_index}, 94 {}, 95 subreg_offset}; 96 97 addSupplementaryRegister(regs, new_reg); 98 } 99 } 100 101 static void 102 addCombinedRegisters(std::vector<DynamicRegisterInfo::Register> ®s, 103 llvm::ArrayRef<RegData *> subregs1, 104 llvm::ArrayRef<RegData *> subregs2, uint32_t base_size, 105 lldb::Encoding encoding, lldb::Format format) { 106 for (auto it : llvm::zip(subregs1, subregs2)) { 107 RegData *regdata1, *regdata2; 108 std::tie(regdata1, regdata2) = it; 109 assert(regdata1); 110 assert(regdata2); 111 112 // verify that we've got matching target registers 113 if (regdata1->subreg_name != regdata2->subreg_name) 114 continue; 115 116 uint32_t base_index1 = *regdata1->base_index; 117 uint32_t base_index2 = *regdata2->base_index; 118 if (regs[base_index1].byte_size != base_size || 119 regs[base_index2].byte_size != base_size) 120 continue; 121 122 lldb_private::DynamicRegisterInfo::Register new_reg{ 123 lldb_private::ConstString(regdata1->subreg_name), 124 lldb_private::ConstString(), 125 lldb_private::ConstString("supplementary registers"), 126 base_size * 2, 127 LLDB_INVALID_INDEX32, 128 encoding, 129 format, 130 LLDB_INVALID_REGNUM, 131 LLDB_INVALID_REGNUM, 132 LLDB_INVALID_REGNUM, 133 LLDB_INVALID_REGNUM, 134 {base_index1, base_index2}, 135 {}}; 136 137 addSupplementaryRegister(regs, new_reg); 138 } 139 } 140 141 typedef llvm::SmallDenseMap<llvm::StringRef, llvm::SmallVector<RegData, 4>, 64> 142 BaseRegToRegsMap; 143 144 #define GPRh(l) \ 145 { \ 146 is64bit ? BaseRegToRegsMap::value_type("r" l "x", \ 147 {{GPR32, "e" l "x", std::nullopt}, \ 148 {GPR16, l "x", std::nullopt}, \ 149 {GPR8h, l "h", std::nullopt}, \ 150 {GPR8, l "l", std::nullopt}}) \ 151 : BaseRegToRegsMap::value_type("e" l "x", \ 152 {{GPR16, l "x", std::nullopt}, \ 153 {GPR8h, l "h", std::nullopt}, \ 154 {GPR8, l "l", std::nullopt}}) \ 155 } 156 157 #define GPR(r16) \ 158 { \ 159 is64bit ? BaseRegToRegsMap::value_type("r" r16, \ 160 {{GPR32, "e" r16, std::nullopt}, \ 161 {GPR16, r16, std::nullopt}, \ 162 {GPR8, r16 "l", std::nullopt}}) \ 163 : BaseRegToRegsMap::value_type( \ 164 "e" r16, \ 165 {{GPR16, r16, std::nullopt}, {GPR8, r16 "l", std::nullopt}}) \ 166 } 167 168 #define GPR64(n) \ 169 { \ 170 BaseRegToRegsMap::value_type("r" #n, {{GPR32, "r" #n "d", std::nullopt}, \ 171 {GPR16, "r" #n "w", std::nullopt}, \ 172 {GPR8, "r" #n "l", std::nullopt}}) \ 173 } 174 175 #define STMM(n) \ 176 { BaseRegToRegsMap::value_type("st" #n, {{MM, "mm" #n, std::nullopt}}) } 177 178 #define YMM(n) \ 179 {BaseRegToRegsMap::value_type("ymm" #n "h", \ 180 {{YMM_YMMh, "ymm" #n, std::nullopt}})}, \ 181 { \ 182 BaseRegToRegsMap::value_type("xmm" #n, \ 183 {{YMM_XMM, "ymm" #n, std::nullopt}}) \ 184 } 185 186 BaseRegToRegsMap makeBaseRegMap(bool is64bit) { 187 BaseRegToRegsMap out{ 188 {// GPRs common to amd64 & i386 189 GPRh("a"), GPRh("b"), GPRh("c"), GPRh("d"), GPR("si"), GPR("di"), 190 GPR("bp"), GPR("sp"), 191 192 // ST/MM registers 193 STMM(0), STMM(1), STMM(2), STMM(3), STMM(4), STMM(5), STMM(6), STMM(7), 194 195 // lower YMM registers (common to amd64 & i386) 196 YMM(0), YMM(1), YMM(2), YMM(3), YMM(4), YMM(5), YMM(6), YMM(7)}}; 197 198 if (is64bit) { 199 BaseRegToRegsMap amd64_regs{{// GPRs specific to amd64 200 GPR64(8), GPR64(9), GPR64(10), GPR64(11), 201 GPR64(12), GPR64(13), GPR64(14), GPR64(15), 202 203 // higher YMM registers (specific to amd64) 204 YMM(8), YMM(9), YMM(10), YMM(11), YMM(12), 205 YMM(13), YMM(14), YMM(15)}}; 206 out.insert(amd64_regs.begin(), amd64_regs.end()); 207 } 208 209 return out; 210 } 211 212 void ABIX86::AugmentRegisterInfo( 213 std::vector<DynamicRegisterInfo::Register> ®s) { 214 MCBasedABI::AugmentRegisterInfo(regs); 215 216 ProcessSP process_sp = GetProcessSP(); 217 if (!process_sp) 218 return; 219 220 uint32_t gpr_base_size = 221 process_sp->GetTarget().GetArchitecture().GetAddressByteSize(); 222 223 // primary map from a base register to its subregisters 224 BaseRegToRegsMap base_reg_map = makeBaseRegMap(gpr_base_size == 8); 225 // set used for fast matching of register names to subregisters 226 llvm::SmallDenseSet<llvm::StringRef, 64> subreg_name_set; 227 // convenience array providing access to all subregisters of given kind, 228 // sorted by base register index 229 std::array<llvm::SmallVector<RegData *, 16>, RegKindCount> subreg_by_kind; 230 231 // prepare the set of all known subregisters 232 for (const auto &x : base_reg_map) { 233 for (const auto &subreg : x.second) 234 subreg_name_set.insert(subreg.subreg_name); 235 } 236 237 // iterate over all registers 238 for (const auto &x : llvm::enumerate(regs)) { 239 llvm::StringRef reg_name = x.value().name.GetStringRef(); 240 // abort if at least one sub-register is already present 241 if (llvm::is_contained(subreg_name_set, reg_name)) 242 return; 243 244 auto found = base_reg_map.find(reg_name); 245 if (found == base_reg_map.end()) 246 continue; 247 248 for (auto &subreg : found->second) { 249 // fill in base register indices 250 subreg.base_index = x.index(); 251 // fill subreg_by_kind map-array 252 subreg_by_kind[static_cast<size_t>(subreg.subreg_kind)].push_back( 253 &subreg); 254 } 255 } 256 257 // now add registers by kind 258 addPartialRegisters(regs, subreg_by_kind[GPR32], gpr_base_size, eEncodingUint, 259 eFormatHex, 4); 260 addPartialRegisters(regs, subreg_by_kind[GPR16], gpr_base_size, eEncodingUint, 261 eFormatHex, 2); 262 addPartialRegisters(regs, subreg_by_kind[GPR8h], gpr_base_size, eEncodingUint, 263 eFormatHex, 1, 1); 264 addPartialRegisters(regs, subreg_by_kind[GPR8], gpr_base_size, eEncodingUint, 265 eFormatHex, 1); 266 267 addPartialRegisters(regs, subreg_by_kind[MM], 10, eEncodingUint, eFormatHex, 268 8); 269 270 addCombinedRegisters(regs, subreg_by_kind[YMM_XMM], subreg_by_kind[YMM_YMMh], 271 16, eEncodingVector, eFormatVectorOfUInt8); 272 } 273