1 //===-- ABIX86.cpp --------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifdef LLDB_ENABLE_ALL 10 #include "ABIMacOSX_i386.h" 11 #endif // LLDB_ENABLE_ALL 12 #include "ABISysV_i386.h" 13 #include "ABISysV_x86_64.h" 14 #ifdef LLDB_ENABLE_ALL 15 #include "ABIWindows_x86_64.h" 16 #endif // LLDB_ENABLE_ALL 17 #include "ABIX86.h" 18 #include "lldb/Core/PluginManager.h" 19 #include "lldb/Target/Process.h" 20 21 using namespace lldb; 22 using namespace lldb_private; 23 24 LLDB_PLUGIN_DEFINE(ABIX86) 25 26 void ABIX86::Initialize() { 27 #ifdef LLDB_ENABLE_ALL 28 ABIMacOSX_i386::Initialize(); 29 #endif // LLDB_ENABLE_ALL 30 ABISysV_i386::Initialize(); 31 ABISysV_x86_64::Initialize(); 32 #ifdef LLDB_ENABLE_ALL 33 ABIWindows_x86_64::Initialize(); 34 #endif // LLDB_ENABLE_ALL 35 } 36 37 void ABIX86::Terminate() { 38 #ifdef LLDB_ENABLE_ALL 39 ABIMacOSX_i386::Terminate(); 40 #endif // LLDB_ENABLE_ALL 41 ABISysV_i386::Terminate(); 42 ABISysV_x86_64::Terminate(); 43 #ifdef LLDB_ENABLE_ALL 44 ABIWindows_x86_64::Terminate(); 45 #endif // LLDB_ENABLE_ALL 46 } 47 48 namespace { 49 enum RegKind { 50 GPR32, 51 GPR16, 52 GPR8h, 53 GPR8, 54 MM, 55 YMM_YMMh, 56 YMM_XMM, 57 58 RegKindCount 59 }; 60 } 61 62 struct RegData { 63 RegKind subreg_kind; 64 llvm::StringRef subreg_name; 65 llvm::Optional<uint32_t> base_index; 66 }; 67 68 static void 69 addPartialRegisters(std::vector<DynamicRegisterInfo::Register> ®s, 70 llvm::ArrayRef<RegData *> subregs, uint32_t base_size, 71 lldb::Encoding encoding, lldb::Format format, 72 uint32_t subreg_size, uint32_t subreg_offset = 0) { 73 for (const RegData *subreg : subregs) { 74 assert(subreg); 75 uint32_t base_index = subreg->base_index.getValue(); 76 DynamicRegisterInfo::Register &full_reg = regs[base_index]; 77 if (full_reg.byte_size != base_size) 78 continue; 79 80 lldb_private::DynamicRegisterInfo::Register new_reg{ 81 lldb_private::ConstString(subreg->subreg_name), 82 lldb_private::ConstString(), 83 lldb_private::ConstString("supplementary registers"), 84 subreg_size, 85 LLDB_INVALID_INDEX32, 86 encoding, 87 format, 88 LLDB_INVALID_REGNUM, 89 LLDB_INVALID_REGNUM, 90 LLDB_INVALID_REGNUM, 91 LLDB_INVALID_REGNUM, 92 {base_index}, 93 {}, 94 subreg_offset}; 95 96 addSupplementaryRegister(regs, new_reg); 97 } 98 } 99 100 static void 101 addCombinedRegisters(std::vector<DynamicRegisterInfo::Register> ®s, 102 llvm::ArrayRef<RegData *> subregs1, 103 llvm::ArrayRef<RegData *> subregs2, uint32_t base_size, 104 lldb::Encoding encoding, lldb::Format format) { 105 for (auto it : llvm::zip(subregs1, subregs2)) { 106 RegData *regdata1, *regdata2; 107 std::tie(regdata1, regdata2) = it; 108 assert(regdata1); 109 assert(regdata2); 110 111 // verify that we've got matching target registers 112 if (regdata1->subreg_name != regdata2->subreg_name) 113 continue; 114 115 uint32_t base_index1 = regdata1->base_index.getValue(); 116 uint32_t base_index2 = regdata2->base_index.getValue(); 117 if (regs[base_index1].byte_size != base_size || 118 regs[base_index2].byte_size != base_size) 119 continue; 120 121 lldb_private::DynamicRegisterInfo::Register new_reg{ 122 lldb_private::ConstString(regdata1->subreg_name), 123 lldb_private::ConstString(), 124 lldb_private::ConstString("supplementary registers"), 125 base_size * 2, 126 LLDB_INVALID_INDEX32, 127 encoding, 128 format, 129 LLDB_INVALID_REGNUM, 130 LLDB_INVALID_REGNUM, 131 LLDB_INVALID_REGNUM, 132 LLDB_INVALID_REGNUM, 133 {base_index1, base_index2}, 134 {}}; 135 136 addSupplementaryRegister(regs, new_reg); 137 } 138 } 139 140 typedef llvm::SmallDenseMap<llvm::StringRef, llvm::SmallVector<RegData, 4>, 64> 141 BaseRegToRegsMap; 142 143 #define GPRh(l) \ 144 { \ 145 is64bit \ 146 ? BaseRegToRegsMap::value_type("r" l "x", \ 147 {{GPR32, "e" l "x", llvm::None}, \ 148 {GPR16, l "x", llvm::None}, \ 149 {GPR8h, l "h", llvm::None}, \ 150 {GPR8, l "l", llvm::None}}) \ 151 : BaseRegToRegsMap::value_type("e" l "x", {{GPR16, l "x", llvm::None}, \ 152 {GPR8h, l "h", llvm::None}, \ 153 {GPR8, l "l", llvm::None}}) \ 154 } 155 156 #define GPR(r16) \ 157 { \ 158 is64bit \ 159 ? BaseRegToRegsMap::value_type("r" r16, {{GPR32, "e" r16, llvm::None}, \ 160 {GPR16, r16, llvm::None}, \ 161 {GPR8, r16 "l", llvm::None}}) \ 162 : BaseRegToRegsMap::value_type("e" r16, {{GPR16, r16, llvm::None}, \ 163 {GPR8, r16 "l", llvm::None}}) \ 164 } 165 166 #define GPR64(n) \ 167 { \ 168 BaseRegToRegsMap::value_type("r" #n, {{GPR32, "r" #n "d", llvm::None}, \ 169 {GPR16, "r" #n "w", llvm::None}, \ 170 {GPR8, "r" #n "l", llvm::None}}) \ 171 } 172 173 #define STMM(n) \ 174 { BaseRegToRegsMap::value_type("st" #n, {{MM, "mm" #n, llvm::None}}) } 175 176 #define YMM(n) \ 177 {BaseRegToRegsMap::value_type("ymm" #n "h", \ 178 {{YMM_YMMh, "ymm" #n, llvm::None}})}, \ 179 { \ 180 BaseRegToRegsMap::value_type("xmm" #n, {{YMM_XMM, "ymm" #n, llvm::None}}) \ 181 } 182 183 BaseRegToRegsMap makeBaseRegMap(bool is64bit) { 184 BaseRegToRegsMap out{ 185 {// GPRs common to amd64 & i386 186 GPRh("a"), GPRh("b"), GPRh("c"), GPRh("d"), GPR("si"), GPR("di"), 187 GPR("bp"), GPR("sp"), 188 189 // ST/MM registers 190 STMM(0), STMM(1), STMM(2), STMM(3), STMM(4), STMM(5), STMM(6), STMM(7), 191 192 // lower YMM registers (common to amd64 & i386) 193 YMM(0), YMM(1), YMM(2), YMM(3), YMM(4), YMM(5), YMM(6), YMM(7)}}; 194 195 if (is64bit) { 196 BaseRegToRegsMap amd64_regs{{// GPRs specific to amd64 197 GPR64(8), GPR64(9), GPR64(10), GPR64(11), 198 GPR64(12), GPR64(13), GPR64(14), GPR64(15), 199 200 // higher YMM registers (specific to amd64) 201 YMM(8), YMM(9), YMM(10), YMM(11), YMM(12), 202 YMM(13), YMM(14), YMM(15)}}; 203 out.insert(amd64_regs.begin(), amd64_regs.end()); 204 } 205 206 return out; 207 } 208 209 void ABIX86::AugmentRegisterInfo( 210 std::vector<DynamicRegisterInfo::Register> ®s) { 211 MCBasedABI::AugmentRegisterInfo(regs); 212 213 ProcessSP process_sp = GetProcessSP(); 214 if (!process_sp) 215 return; 216 217 uint32_t gpr_base_size = 218 process_sp->GetTarget().GetArchitecture().GetAddressByteSize(); 219 220 // primary map from a base register to its subregisters 221 BaseRegToRegsMap base_reg_map = makeBaseRegMap(gpr_base_size == 8); 222 // set used for fast matching of register names to subregisters 223 llvm::SmallDenseSet<llvm::StringRef, 64> subreg_name_set; 224 // convenience array providing access to all subregisters of given kind, 225 // sorted by base register index 226 std::array<llvm::SmallVector<RegData *, 16>, RegKindCount> subreg_by_kind; 227 228 // prepare the set of all known subregisters 229 for (const auto &x : base_reg_map) { 230 for (const auto &subreg : x.second) 231 subreg_name_set.insert(subreg.subreg_name); 232 } 233 234 // iterate over all registers 235 for (const auto &x : llvm::enumerate(regs)) { 236 llvm::StringRef reg_name = x.value().name.GetStringRef(); 237 // abort if at least one sub-register is already present 238 if (llvm::is_contained(subreg_name_set, reg_name)) 239 return; 240 241 auto found = base_reg_map.find(reg_name); 242 if (found == base_reg_map.end()) 243 continue; 244 245 for (auto &subreg : found->second) { 246 // fill in base register indices 247 subreg.base_index = x.index(); 248 // fill subreg_by_kind map-array 249 subreg_by_kind[static_cast<size_t>(subreg.subreg_kind)].push_back( 250 &subreg); 251 } 252 } 253 254 // now add registers by kind 255 addPartialRegisters(regs, subreg_by_kind[GPR32], gpr_base_size, eEncodingUint, 256 eFormatHex, 4); 257 addPartialRegisters(regs, subreg_by_kind[GPR16], gpr_base_size, eEncodingUint, 258 eFormatHex, 2); 259 addPartialRegisters(regs, subreg_by_kind[GPR8h], gpr_base_size, eEncodingUint, 260 eFormatHex, 1, 1); 261 addPartialRegisters(regs, subreg_by_kind[GPR8], gpr_base_size, eEncodingUint, 262 eFormatHex, 1); 263 264 addPartialRegisters(regs, subreg_by_kind[MM], 10, eEncodingUint, eFormatHex, 265 8); 266 267 addCombinedRegisters(regs, subreg_by_kind[YMM_XMM], subreg_by_kind[YMM_YMMh], 268 16, eEncodingVector, eFormatVectorOfUInt8); 269 } 270