1 //===-- EmulateInstructionARM.h ---------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H 10 #define LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H 11 12 #include "Plugins/Process/Utility/ARMDefines.h" 13 #include "lldb/Core/EmulateInstruction.h" 14 #include "lldb/Utility/ConstString.h" 15 #include "lldb/Utility/Status.h" 16 17 namespace lldb_private { 18 19 // ITSession - Keep track of the IT Block progression. 20 class ITSession { 21 public: 22 ITSession() = default; 23 ~ITSession() = default; 24 25 // InitIT - Initializes ITCounter/ITState. 26 bool InitIT(uint32_t bits7_0); 27 28 // ITAdvance - Updates ITCounter/ITState as IT Block progresses. 29 void ITAdvance(); 30 31 // InITBlock - Returns true if we're inside an IT Block. 32 bool InITBlock(); 33 34 // LastInITBlock - Returns true if we're the last instruction inside an IT 35 // Block. 36 bool LastInITBlock(); 37 38 // GetCond - Gets condition bits for the current thumb instruction. 39 uint32_t GetCond(); 40 41 private: 42 uint32_t ITCounter = 0; // Possible values: 0, 1, 2, 3, 4. 43 uint32_t ITState = 0; // A2.5.2 Consists of IT[7:5] and IT[4:0] initially. 44 }; 45 46 class EmulateInstructionARM : public EmulateInstruction { 47 public: 48 enum ARMEncoding { 49 eEncodingA1, 50 eEncodingA2, 51 eEncodingA3, 52 eEncodingA4, 53 eEncodingA5, 54 eEncodingT1, 55 eEncodingT2, 56 eEncodingT3, 57 eEncodingT4, 58 eEncodingT5 59 }; 60 61 static void Initialize(); 62 63 static void Terminate(); 64 65 static llvm::StringRef GetPluginNameStatic() { return "arm"; } 66 67 static llvm::StringRef GetPluginDescriptionStatic(); 68 69 static lldb_private::EmulateInstruction * 70 CreateInstance(const lldb_private::ArchSpec &arch, InstructionType inst_type); 71 72 static bool 73 SupportsEmulatingInstructionsOfTypeStatic(InstructionType inst_type) { 74 switch (inst_type) { 75 case eInstructionTypeAny: 76 case eInstructionTypePrologueEpilogue: 77 case eInstructionTypePCModifying: 78 return true; 79 80 case eInstructionTypeAll: 81 return false; 82 } 83 return false; 84 } 85 86 llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); } 87 88 bool SetTargetTriple(const ArchSpec &arch) override; 89 90 enum Mode { eModeInvalid = -1, eModeARM, eModeThumb }; 91 92 EmulateInstructionARM(const ArchSpec &arch) 93 : EmulateInstruction(arch), m_arm_isa(0), m_opcode_mode(eModeInvalid), 94 m_opcode_cpsr(0), m_it_session(), m_ignore_conditions(false) { 95 SetArchitecture(arch); 96 } 97 98 // EmulateInstructionARM (const ArchSpec &arch, 99 // bool ignore_conditions, 100 // void *baton, 101 // ReadMemory read_mem_callback, 102 // WriteMemory write_mem_callback, 103 // ReadRegister read_reg_callback, 104 // WriteRegister write_reg_callback) : 105 // EmulateInstruction (arch, 106 // ignore_conditions, 107 // baton, 108 // read_mem_callback, 109 // write_mem_callback, 110 // read_reg_callback, 111 // write_reg_callback), 112 // m_arm_isa (0), 113 // m_opcode_mode (eModeInvalid), 114 // m_opcode_cpsr (0), 115 // m_it_session () 116 // { 117 // } 118 119 bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override { 120 return SupportsEmulatingInstructionsOfTypeStatic(inst_type); 121 } 122 123 virtual bool SetArchitecture(const ArchSpec &arch); 124 125 bool ReadInstruction() override; 126 127 bool SetInstruction(const Opcode &insn_opcode, const Address &inst_addr, 128 Target *target) override; 129 130 bool EvaluateInstruction(uint32_t evaluate_options) override; 131 132 InstructionCondition GetInstructionCondition() override; 133 134 bool TestEmulation(Stream *out_stream, ArchSpec &arch, 135 OptionValueDictionary *test_data) override; 136 137 bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num, 138 RegisterInfo ®_info) override; 139 140 bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override; 141 142 uint32_t ArchVersion(); 143 144 bool ConditionPassed(const uint32_t opcode); 145 146 uint32_t CurrentCond(const uint32_t opcode); 147 148 // InITBlock - Returns true if we're in Thumb mode and inside an IT Block. 149 bool InITBlock(); 150 151 // LastInITBlock - Returns true if we're in Thumb mode and the last 152 // instruction inside an IT Block. 153 bool LastInITBlock(); 154 155 bool BadMode(uint32_t mode); 156 157 bool CurrentModeIsPrivileged(); 158 159 void CPSRWriteByInstr(uint32_t value, uint32_t bytemask, 160 bool affect_execstate); 161 162 bool BranchWritePC(const Context &context, uint32_t addr); 163 164 bool BXWritePC(Context &context, uint32_t addr); 165 166 bool LoadWritePC(Context &context, uint32_t addr); 167 168 bool ALUWritePC(Context &context, uint32_t addr); 169 170 Mode CurrentInstrSet(); 171 172 bool SelectInstrSet(Mode arm_or_thumb); 173 174 bool WriteBits32Unknown(int n); 175 176 bool WriteBits32UnknownToMemory(lldb::addr_t address); 177 178 bool UnalignedSupport(); 179 180 typedef struct { 181 uint32_t result; 182 uint8_t carry_out; 183 uint8_t overflow; 184 } AddWithCarryResult; 185 186 AddWithCarryResult AddWithCarry(uint32_t x, uint32_t y, uint8_t carry_in); 187 188 // Helper method to read the content of an ARM core register. 189 uint32_t ReadCoreReg(uint32_t regnum, bool *success); 190 191 // See A8.6.96 MOV (immediate) Operation. 192 // Default arguments are specified for carry and overflow parameters, which 193 // means 194 // not to update the respective flags even if setflags is true. 195 bool WriteCoreRegOptionalFlags(Context &context, const uint32_t result, 196 const uint32_t Rd, bool setflags, 197 const uint32_t carry = ~0u, 198 const uint32_t overflow = ~0u); 199 200 bool WriteCoreReg(Context &context, const uint32_t result, 201 const uint32_t Rd) { 202 // Don't set the flags. 203 return WriteCoreRegOptionalFlags(context, result, Rd, false); 204 } 205 206 // See A8.6.35 CMP (immediate) Operation. 207 // Default arguments are specified for carry and overflow parameters, which 208 // means 209 // not to update the respective flags. 210 bool WriteFlags(Context &context, const uint32_t result, 211 const uint32_t carry = ~0u, const uint32_t overflow = ~0u); 212 213 inline uint64_t MemARead(EmulateInstruction::Context &context, 214 lldb::addr_t address, uint32_t size, 215 uint64_t fail_value, bool *success_ptr) { 216 // This is a stub function corresponding to "MemA[]" in the ARM manual 217 // pseudocode, for 218 // aligned reads from memory. Since we are not trying to write a full 219 // hardware simulator, and since 220 // we are running in User mode (rather than Kernel mode) and therefore won't 221 // have access to many of the 222 // system registers we would need in order to fully implement this function, 223 // we will just call 224 // ReadMemoryUnsigned from here. In the future, if we decide we do need to 225 // do more faithful emulation of 226 // the hardware, we can update this function appropriately. 227 228 return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr); 229 } 230 231 inline bool MemAWrite(EmulateInstruction::Context &context, 232 lldb::addr_t address, uint64_t data_val, uint32_t size) 233 234 { 235 // This is a stub function corresponding to "MemA[]" in the ARM manual 236 // pseudocode, for 237 // aligned writes to memory. Since we are not trying to write a full 238 // hardware simulator, and since 239 // we are running in User mode (rather than Kernel mode) and therefore won't 240 // have access to many of the 241 // system registers we would need in order to fully implement this function, 242 // we will just call 243 // WriteMemoryUnsigned from here. In the future, if we decide we do need to 244 // do more faithful emulation of 245 // the hardware, we can update this function appropriately. 246 247 return WriteMemoryUnsigned(context, address, data_val, size); 248 } 249 250 inline uint64_t MemURead(EmulateInstruction::Context &context, 251 lldb::addr_t address, uint32_t size, 252 uint64_t fail_value, bool *success_ptr) { 253 // This is a stub function corresponding to "MemU[]" in the ARM manual 254 // pseudocode, for 255 // unaligned reads from memory. Since we are not trying to write a full 256 // hardware simulator, and since 257 // we are running in User mode (rather than Kernel mode) and therefore won't 258 // have access to many of the 259 // system registers we would need in order to fully implement this function, 260 // we will just call 261 // ReadMemoryUnsigned from here. In the future, if we decide we do need to 262 // do more faithful emulation of 263 // the hardware, we can update this function appropriately. 264 265 return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr); 266 } 267 268 inline bool MemUWrite(EmulateInstruction::Context &context, 269 lldb::addr_t address, uint64_t data_val, uint32_t size) 270 271 { 272 // This is a stub function corresponding to "MemU[]" in the ARM manual 273 // pseudocode, for 274 // unaligned writes to memory. Since we are not trying to write a full 275 // hardware simulator, and since 276 // we are running in User mode (rather than Kernel mode) and therefore won't 277 // have access to many of the 278 // system registers we would need in order to fully implement this function, 279 // we will just call 280 // WriteMemoryUnsigned from here. In the future, if we decide we do need to 281 // do more faithful emulation of 282 // the hardware, we can update this function appropriately. 283 284 return WriteMemoryUnsigned(context, address, data_val, size); 285 } 286 287 protected: 288 // Typedef for the callback function used during the emulation. 289 // Pass along (ARMEncoding)encoding as the callback data. 290 enum ARMInstrSize { eSize16, eSize32 }; 291 292 typedef struct { 293 uint32_t mask; 294 uint32_t value; 295 uint32_t variants; 296 EmulateInstructionARM::ARMEncoding encoding; 297 uint32_t vfp_variants; 298 ARMInstrSize size; 299 bool (EmulateInstructionARM::*callback)( 300 const uint32_t opcode, 301 const EmulateInstructionARM::ARMEncoding encoding); 302 const char *name; 303 } ARMOpcode; 304 305 uint32_t GetFramePointerRegisterNumber() const; 306 307 uint32_t GetFramePointerDWARFRegisterNumber() const; 308 309 static ARMOpcode *GetARMOpcodeForInstruction(const uint32_t opcode, 310 uint32_t isa_mask); 311 312 static ARMOpcode *GetThumbOpcodeForInstruction(const uint32_t opcode, 313 uint32_t isa_mask); 314 315 // A8.6.123 PUSH 316 bool EmulatePUSH(const uint32_t opcode, const ARMEncoding encoding); 317 318 // A8.6.122 POP 319 bool EmulatePOP(const uint32_t opcode, const ARMEncoding encoding); 320 321 // A8.6.8 ADD (SP plus immediate) 322 bool EmulateADDRdSPImm(const uint32_t opcode, const ARMEncoding encoding); 323 324 // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp 325 bool EmulateMOVRdSP(const uint32_t opcode, const ARMEncoding encoding); 326 327 // A8.6.97 MOV (register) -- move from r8-r15 to r0-r7 328 bool EmulateMOVLowHigh(const uint32_t opcode, const ARMEncoding encoding); 329 330 // A8.6.59 LDR (literal) 331 bool EmulateLDRRtPCRelative(const uint32_t opcode, 332 const ARMEncoding encoding); 333 334 // A8.6.8 ADD (SP plus immediate) 335 bool EmulateADDSPImm(const uint32_t opcode, const ARMEncoding encoding); 336 337 // A8.6.9 ADD (SP plus register) 338 bool EmulateADDSPRm(const uint32_t opcode, const ARMEncoding encoding); 339 340 // A8.6.23 BL, BLX (immediate) 341 bool EmulateBLXImmediate(const uint32_t opcode, const ARMEncoding encoding); 342 343 // A8.6.24 BLX (register) 344 bool EmulateBLXRm(const uint32_t opcode, const ARMEncoding encoding); 345 346 // A8.6.25 BX 347 bool EmulateBXRm(const uint32_t opcode, const ARMEncoding encoding); 348 349 // A8.6.26 BXJ 350 bool EmulateBXJRm(const uint32_t opcode, const ARMEncoding encoding); 351 352 // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip 353 bool EmulateSUBR7IPImm(const uint32_t opcode, const ARMEncoding encoding); 354 355 // A8.6.215 SUB (SP minus immediate) -- Rd == ip 356 bool EmulateSUBIPSPImm(const uint32_t opcode, const ARMEncoding encoding); 357 358 // A8.6.215 SUB (SP minus immediate) 359 bool EmulateSUBSPImm(const uint32_t opcode, const ARMEncoding encoding); 360 361 // A8.6.216 SUB (SP minus register) 362 bool EmulateSUBSPReg(const uint32_t opcode, const ARMEncoding encoding); 363 364 // A8.6.194 STR (immediate, ARM) -- Rn == sp 365 bool EmulateSTRRtSP(const uint32_t opcode, const ARMEncoding encoding); 366 367 // A8.6.355 VPUSH 368 bool EmulateVPUSH(const uint32_t opcode, const ARMEncoding encoding); 369 370 // A8.6.354 VPOP 371 bool EmulateVPOP(const uint32_t opcode, const ARMEncoding encoding); 372 373 // A8.6.218 SVC (previously SWI) 374 bool EmulateSVC(const uint32_t opcode, const ARMEncoding encoding); 375 376 // A8.6.50 IT 377 bool EmulateIT(const uint32_t opcode, const ARMEncoding encoding); 378 379 // NOP 380 bool EmulateNop(const uint32_t opcode, const ARMEncoding encoding); 381 382 // A8.6.16 B 383 bool EmulateB(const uint32_t opcode, const ARMEncoding encoding); 384 385 // A8.6.27 CBNZ, CBZ 386 bool EmulateCB(const uint32_t opcode, const ARMEncoding encoding); 387 388 // A8.6.226 TBB, TBH 389 bool EmulateTB(const uint32_t opcode, const ARMEncoding encoding); 390 391 // A8.6.4 ADD (immediate, Thumb) 392 bool EmulateADDImmThumb(const uint32_t opcode, const ARMEncoding encoding); 393 394 // A8.6.5 ADD (immediate, ARM) 395 bool EmulateADDImmARM(const uint32_t opcode, const ARMEncoding encoding); 396 397 // A8.6.6 ADD (register) 398 bool EmulateADDReg(const uint32_t opcode, const ARMEncoding encoding); 399 400 // A8.6.7 ADD (register-shifted register) 401 bool EmulateADDRegShift(const uint32_t opcode, const ARMEncoding encoding); 402 403 // A8.6.97 MOV (register) 404 bool EmulateMOVRdRm(const uint32_t opcode, const ARMEncoding encoding); 405 406 // A8.6.96 MOV (immediate) 407 bool EmulateMOVRdImm(const uint32_t opcode, const ARMEncoding encoding); 408 409 // A8.6.35 CMP (immediate) 410 bool EmulateCMPImm(const uint32_t opcode, const ARMEncoding encoding); 411 412 // A8.6.36 CMP (register) 413 bool EmulateCMPReg(const uint32_t opcode, const ARMEncoding encoding); 414 415 // A8.6.14 ASR (immediate) 416 bool EmulateASRImm(const uint32_t opcode, const ARMEncoding encoding); 417 418 // A8.6.15 ASR (register) 419 bool EmulateASRReg(const uint32_t opcode, const ARMEncoding encoding); 420 421 // A8.6.88 LSL (immediate) 422 bool EmulateLSLImm(const uint32_t opcode, const ARMEncoding encoding); 423 424 // A8.6.89 LSL (register) 425 bool EmulateLSLReg(const uint32_t opcode, const ARMEncoding encoding); 426 427 // A8.6.90 LSR (immediate) 428 bool EmulateLSRImm(const uint32_t opcode, const ARMEncoding encoding); 429 430 // A8.6.91 LSR (register) 431 bool EmulateLSRReg(const uint32_t opcode, const ARMEncoding encoding); 432 433 // A8.6.139 ROR (immediate) 434 bool EmulateRORImm(const uint32_t opcode, const ARMEncoding encoding); 435 436 // A8.6.140 ROR (register) 437 bool EmulateRORReg(const uint32_t opcode, const ARMEncoding encoding); 438 439 // A8.6.141 RRX 440 bool EmulateRRX(const uint32_t opcode, const ARMEncoding encoding); 441 442 // Helper method for ASR, LSL, LSR, ROR (immediate), and RRX 443 bool EmulateShiftImm(const uint32_t opcode, const ARMEncoding encoding, 444 ARM_ShifterType shift_type); 445 446 // Helper method for ASR, LSL, LSR, and ROR (register) 447 bool EmulateShiftReg(const uint32_t opcode, const ARMEncoding encoding, 448 ARM_ShifterType shift_type); 449 450 // LOAD FUNCTIONS 451 452 // A8.6.53 LDM/LDMIA/LDMFD 453 bool EmulateLDM(const uint32_t opcode, const ARMEncoding encoding); 454 455 // A8.6.54 LDMDA/LDMFA 456 bool EmulateLDMDA(const uint32_t opcode, const ARMEncoding encoding); 457 458 // A8.6.55 LDMDB/LDMEA 459 bool EmulateLDMDB(const uint32_t opcode, const ARMEncoding encoding); 460 461 // A8.6.56 LDMIB/LDMED 462 bool EmulateLDMIB(const uint32_t opcode, const ARMEncoding encoding); 463 464 // A8.6.57 LDR (immediate, Thumb) -- Encoding T1 465 bool EmulateLDRRtRnImm(const uint32_t opcode, const ARMEncoding encoding); 466 467 // A8.6.58 LDR (immediate, ARM) - Encoding A1 468 bool EmulateLDRImmediateARM(const uint32_t opcode, 469 const ARMEncoding encoding); 470 471 // A8.6.59 LDR (literal) 472 bool EmulateLDRLiteral(const uint32_t, const ARMEncoding encoding); 473 474 // A8.6.60 LDR (register) - Encoding T1, T2, A1 475 bool EmulateLDRRegister(const uint32_t opcode, const ARMEncoding encoding); 476 477 // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2, T3 478 bool EmulateLDRBImmediate(const uint32_t opcode, const ARMEncoding encoding); 479 480 // A8.6.62 LDRB (immediate, ARM) 481 bool EmulateLDRBImmediateARM(const uint32_t opcode, 482 const ARMEncoding encoding); 483 484 // A8.6.63 LDRB (literal) - Encoding T1, A1 485 bool EmulateLDRBLiteral(const uint32_t opcode, const ARMEncoding encoding); 486 487 // A8.6.64 LDRB (register) - Encoding T1, T2, A1 488 bool EmulateLDRBRegister(const uint32_t opcode, const ARMEncoding encoding); 489 490 // A8.6.65 LDRBT 491 bool EmulateLDRBT(const uint32_t opcode, const ARMEncoding encoding); 492 493 // A8.6.66 LDRD (immediate) 494 bool EmulateLDRDImmediate(const uint32_t opcode, const ARMEncoding encoding); 495 496 // A8.6.67 497 bool EmulateLDRDLiteral(const uint32_t opcode, const ARMEncoding encoding); 498 499 // A8.6.68 LDRD (register) 500 bool EmulateLDRDRegister(const uint32_t opcode, const ARMEncoding encoding); 501 502 // A8.6.69 LDREX 503 bool EmulateLDREX(const uint32_t opcode, const ARMEncoding encoding); 504 505 // A8.6.70 LDREXB 506 bool EmulateLDREXB(const uint32_t opcode, const ARMEncoding encoding); 507 508 // A8.6.71 LDREXD 509 bool EmulateLDREXD(const uint32_t opcode, const ARMEncoding encoding); 510 511 // A8.6.72 LDREXH 512 bool EmulateLDREXH(const uint32_t opcode, const ARMEncoding encoding); 513 514 // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2, T3 515 bool EmulateLDRHImmediate(const uint32_t opcode, const ARMEncoding encoding); 516 517 // A8.6.74 LDRS (immediate, ARM) 518 bool EmulateLDRHImmediateARM(const uint32_t opcode, 519 const ARMEncoding encoding); 520 521 // A8.6.75 LDRH (literal) - Encoding T1, A1 522 bool EmulateLDRHLiteral(const uint32_t opcode, const ARMEncoding encoding); 523 524 // A8.6.76 LDRH (register) - Encoding T1, T2, A1 525 bool EmulateLDRHRegister(const uint32_t opcode, const ARMEncoding encoding); 526 527 // A8.6.77 LDRHT 528 bool EmulateLDRHT(const uint32_t opcode, const ARMEncoding encoding); 529 530 // A8.6.78 LDRSB (immediate) - Encoding T1, T2, A1 531 bool EmulateLDRSBImmediate(const uint32_t opcode, const ARMEncoding encoding); 532 533 // A8.6.79 LDRSB (literal) - Encoding T1, A1 534 bool EmulateLDRSBLiteral(const uint32_t opcode, const ARMEncoding encoding); 535 536 // A8.6.80 LDRSB (register) - Encoding T1, T2, A1 537 bool EmulateLDRSBRegister(const uint32_t opcode, const ARMEncoding encoding); 538 539 // A8.6.81 LDRSBT 540 bool EmulateLDRSBT(const uint32_t opcode, const ARMEncoding encoding); 541 542 // A8.6.82 LDRSH (immediate) - Encoding T1, T2, A1 543 bool EmulateLDRSHImmediate(const uint32_t opcode, const ARMEncoding encoding); 544 545 // A8.6.83 LDRSH (literal) - Encoding T1, A1 546 bool EmulateLDRSHLiteral(const uint32_t opcode, const ARMEncoding encoding); 547 548 // A8.6.84 LDRSH (register) - Encoding T1, T2, A1 549 bool EmulateLDRSHRegister(const uint32_t opcode, const ARMEncoding encoding); 550 551 // A8.6.85 LDRSHT 552 bool EmulateLDRSHT(const uint32_t opcode, const ARMEncoding encoding); 553 554 // A8.6.86 555 bool EmulateLDRT(const uint32_t opcode, const ARMEncoding encoding); 556 557 // STORE FUNCTIONS 558 559 // A8.6.189 STM/STMIA/STMEA 560 bool EmulateSTM(const uint32_t opcode, const ARMEncoding encoding); 561 562 // A8.6.190 STMDA/STMED 563 bool EmulateSTMDA(const uint32_t opcode, const ARMEncoding encoding); 564 565 // A8.6.191 STMDB/STMFD 566 bool EmulateSTMDB(const uint32_t opcode, const ARMEncoding encoding); 567 568 // A8.6.192 STMIB/STMFA 569 bool EmulateSTMIB(const uint32_t opcode, const ARMEncoding encoding); 570 571 // A8.6.193 STR (immediate, Thumb) 572 bool EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding); 573 574 // A8.6.194 STR (immediate, ARM) 575 bool EmulateSTRImmARM(const uint32_t opcode, const ARMEncoding encoding); 576 577 // A8.6.195 STR (register) 578 bool EmulateSTRRegister(const uint32_t opcode, const ARMEncoding encoding); 579 580 // A8.6.196 STRB (immediate, Thumb) 581 bool EmulateSTRBThumb(const uint32_t opcode, const ARMEncoding encoding); 582 583 // A8.6.197 STRB (immediate, ARM) 584 bool EmulateSTRBImmARM(const uint32_t opcode, const ARMEncoding encoding); 585 586 // A8.6.198 STRB (register) 587 bool EmulateSTRBReg(const uint32_t opcode, const ARMEncoding encoding); 588 589 // A8.6.199 STRBT 590 bool EmulateSTRBT(const uint32_t opcode, const ARMEncoding encoding); 591 592 // A8.6.200 STRD (immediate) 593 bool EmulateSTRDImm(const uint32_t opcode, const ARMEncoding encoding); 594 595 // A8.6.201 STRD (register) 596 bool EmulateSTRDReg(const uint32_t opcode, const ARMEncoding encoding); 597 598 // A8.6.202 STREX 599 bool EmulateSTREX(const uint32_t opcode, const ARMEncoding encoding); 600 601 // A8.6.203 STREXB 602 bool EmulateSTREXB(const uint32_t opcode, const ARMEncoding encoding); 603 604 // A8.6.204 STREXD 605 bool EmulateSTREXD(const uint32_t opcode, const ARMEncoding encoding); 606 607 // A8.6.205 STREXH 608 bool EmulateSTREXH(const uint32_t opcode, const ARMEncoding encoding); 609 610 // A8.6.206 STRH (immediate, Thumb) 611 bool EmulateSTRHImmThumb(const uint32_t opcode, const ARMEncoding encoding); 612 613 // A8.6.207 STRH (immediate, ARM) 614 bool EmulateSTRHImmARM(const uint32_t opcode, const ARMEncoding encoding); 615 616 // A8.6.208 STRH (register) 617 bool EmulateSTRHRegister(const uint32_t opcode, const ARMEncoding encoding); 618 619 // A8.6.209 STRHT 620 bool EmulateSTRHT(const uint32_t opcode, const ARMEncoding encoding); 621 622 // A8.6.210 STRT 623 bool EmulateSTRT(const uint32_t opcode, const ARMEncoding encoding); 624 625 // A8.6.1 ADC (immediate) 626 bool EmulateADCImm(const uint32_t opcode, const ARMEncoding encoding); 627 628 // A8.6.2 ADC (Register) 629 bool EmulateADCReg(const uint32_t opcode, const ARMEncoding encoding); 630 631 // A8.6.10 ADR 632 bool EmulateADR(const uint32_t opcode, const ARMEncoding encoding); 633 634 // A8.6.11 AND (immediate) 635 bool EmulateANDImm(const uint32_t opcode, const ARMEncoding encoding); 636 637 // A8.6.12 AND (register) 638 bool EmulateANDReg(const uint32_t opcode, const ARMEncoding encoding); 639 640 // A8.6.19 BIC (immediate) 641 bool EmulateBICImm(const uint32_t opcode, const ARMEncoding encoding); 642 643 // A8.6.20 BIC (register) 644 bool EmulateBICReg(const uint32_t opcode, const ARMEncoding encoding); 645 646 // A8.6.26 BXJ 647 bool EmulateBXJ(const uint32_t opcode, const ARMEncoding encoding); 648 649 // A8.6.32 CMN (immediate) 650 bool EmulateCMNImm(const uint32_t opcode, const ARMEncoding encoding); 651 652 // A8.6.33 CMN (register) 653 bool EmulateCMNReg(const uint32_t opcode, const ARMEncoding encoding); 654 655 // A8.6.44 EOR (immediate) 656 bool EmulateEORImm(const uint32_t opcode, const ARMEncoding encoding); 657 658 // A8.6.45 EOR (register) 659 bool EmulateEORReg(const uint32_t opcode, const ARMEncoding encoding); 660 661 // A8.6.105 MUL 662 bool EmulateMUL(const uint32_t opcode, const ARMEncoding encoding); 663 664 // A8.6.106 MVN (immediate) 665 bool EmulateMVNImm(const uint32_t opcode, const ARMEncoding encoding); 666 667 // A8.6.107 MVN (register) 668 bool EmulateMVNReg(const uint32_t opcode, const ARMEncoding encoding); 669 670 // A8.6.113 ORR (immediate) 671 bool EmulateORRImm(const uint32_t opcode, const ARMEncoding encoding); 672 673 // A8.6.114 ORR (register) 674 bool EmulateORRReg(const uint32_t opcode, const ARMEncoding encoding); 675 676 // A8.6.117 PLD (immediate, literal) - Encoding T1, T2, T3, A1 677 bool EmulatePLDImmediate(const uint32_t opcode, const ARMEncoding encoding); 678 679 // A8.6.119 PLI (immediate,literal) - Encoding T3, A1 680 bool EmulatePLIImmediate(const uint32_t opcode, const ARMEncoding encoding); 681 682 // A8.6.120 PLI (register) - Encoding T1, A1 683 bool EmulatePLIRegister(const uint32_t opcode, const ARMEncoding encoding); 684 685 // A8.6.141 RSB (immediate) 686 bool EmulateRSBImm(const uint32_t opcode, const ARMEncoding encoding); 687 688 // A8.6.142 RSB (register) 689 bool EmulateRSBReg(const uint32_t opcode, const ARMEncoding encoding); 690 691 // A8.6.144 RSC (immediate) 692 bool EmulateRSCImm(const uint32_t opcode, const ARMEncoding encoding); 693 694 // A8.6.145 RSC (register) 695 bool EmulateRSCReg(const uint32_t opcode, const ARMEncoding encoding); 696 697 // A8.6.150 SBC (immediate) 698 bool EmulateSBCImm(const uint32_t opcode, const ARMEncoding encoding); 699 700 // A8.6.151 SBC (register) 701 bool EmulateSBCReg(const uint32_t opcode, const ARMEncoding encoding); 702 703 // A8.6.211 SUB (immediate, Thumb) 704 bool EmulateSUBImmThumb(const uint32_t opcode, const ARMEncoding encoding); 705 706 // A8.6.212 SUB (immediate, ARM) 707 bool EmulateSUBImmARM(const uint32_t opcode, const ARMEncoding encoding); 708 709 // A8.6.213 SUB (register) 710 bool EmulateSUBReg(const uint32_t opcode, const ARMEncoding encoding); 711 712 // A8.6.214 SUB (register-shifted register) 713 bool EmulateSUBRegShift(const uint32_t opcode, const ARMEncoding encoding); 714 715 // A8.6.222 SXTB - Encoding T1 716 bool EmulateSXTB(const uint32_t opcode, const ARMEncoding encoding); 717 718 // A8.6.224 SXTH - EncodingT1 719 bool EmulateSXTH(const uint32_t opcode, const ARMEncoding encoding); 720 721 // A8.6.227 TEQ (immediate) - Encoding A1 722 bool EmulateTEQImm(const uint32_t opcode, const ARMEncoding encoding); 723 724 // A8.6.228 TEQ (register) - Encoding A1 725 bool EmulateTEQReg(const uint32_t opcode, const ARMEncoding encoding); 726 727 // A8.6.230 TST (immediate) - Encoding A1 728 bool EmulateTSTImm(const uint32_t opcode, const ARMEncoding encoding); 729 730 // A8.6.231 TST (register) - Encoding T1, A1 731 bool EmulateTSTReg(const uint32_t opcode, const ARMEncoding encoding); 732 733 // A8.6.262 UXTB - Encoding T1 734 bool EmulateUXTB(const uint32_t opcode, const ARMEncoding encoding); 735 736 // A8.6.264 UXTH - Encoding T1 737 bool EmulateUXTH(const uint32_t opcode, const ARMEncoding encoding); 738 739 // B6.1.8 RFE 740 bool EmulateRFE(const uint32_t opcode, const ARMEncoding encoding); 741 742 // A8.6.319 VLDM 743 bool EmulateVLDM(const uint32_t opcode, const ARMEncoding encoding); 744 745 // A8.6.399 VSTM 746 bool EmulateVSTM(const uint32_t opcode, const ARMEncoding encoding); 747 748 // A8.6.307 VLD1 (multiple single elements) 749 bool EmulateVLD1Multiple(const uint32_t opcode, const ARMEncoding encoding); 750 751 // A8.6.308 VLD1 (single element to one lane) 752 bool EmulateVLD1Single(const uint32_t opcode, const ARMEncoding encoding); 753 754 // A8.6.309 VLD1 (single element to all lanes) 755 bool EmulateVLD1SingleAll(const uint32_t opcode, const ARMEncoding encoding); 756 757 // A8.6.391 VST1 (multiple single elements) 758 bool EmulateVST1Multiple(const uint32_t opcode, const ARMEncoding encoding); 759 760 // A8.6.392 VST1 (single element from one lane) 761 bool EmulateVST1Single(const uint32_t opcode, const ARMEncoding encoding); 762 763 // A8.6.317 VLDR 764 bool EmulateVLDR(const uint32_t opcode, const ARMEncoding encoding); 765 766 // A8.6.400 VSTR 767 bool EmulateVSTR(const uint32_t opcode, const ARMEncoding encoding); 768 769 // B6.2.13 SUBS PC, LR and related instructions 770 bool EmulateSUBSPcLrEtc(const uint32_t opcode, const ARMEncoding encoding); 771 772 uint32_t m_arm_isa; 773 Mode m_opcode_mode; 774 uint32_t m_opcode_cpsr; 775 uint32_t m_new_inst_cpsr; // This can get updated by the opcode. 776 ITSession m_it_session; 777 bool m_ignore_conditions; 778 }; 779 780 } // namespace lldb_private 781 782 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_ARM_EMULATEINSTRUCTIONARM_H 783