1*0eae32dcSDimitry Andric //===-- RegisterContextFreeBSDKernel_arm64.cpp ----------------------------===//
2*0eae32dcSDimitry Andric //
3*0eae32dcSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0eae32dcSDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*0eae32dcSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0eae32dcSDimitry Andric //
7*0eae32dcSDimitry Andric //===----------------------------------------------------------------------===//
8*0eae32dcSDimitry Andric
9*0eae32dcSDimitry Andric #include "RegisterContextFreeBSDKernel_arm64.h"
10*0eae32dcSDimitry Andric #include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
11*0eae32dcSDimitry Andric
12*0eae32dcSDimitry Andric #include "lldb/Target/Process.h"
13*0eae32dcSDimitry Andric #include "lldb/Target/Thread.h"
14*0eae32dcSDimitry Andric #include "lldb/Utility/RegisterValue.h"
15*0eae32dcSDimitry Andric #include "llvm/Support/Endian.h"
16*0eae32dcSDimitry Andric
17*0eae32dcSDimitry Andric using namespace lldb;
18*0eae32dcSDimitry Andric using namespace lldb_private;
19*0eae32dcSDimitry Andric
RegisterContextFreeBSDKernel_arm64(Thread & thread,std::unique_ptr<RegisterInfoPOSIX_arm64> register_info_up,lldb::addr_t pcb_addr)20*0eae32dcSDimitry Andric RegisterContextFreeBSDKernel_arm64::RegisterContextFreeBSDKernel_arm64(
21*0eae32dcSDimitry Andric Thread &thread, std::unique_ptr<RegisterInfoPOSIX_arm64> register_info_up,
22*0eae32dcSDimitry Andric lldb::addr_t pcb_addr)
23*0eae32dcSDimitry Andric : RegisterContextPOSIX_arm64(thread, std::move(register_info_up)),
24*0eae32dcSDimitry Andric m_pcb_addr(pcb_addr) {}
25*0eae32dcSDimitry Andric
ReadGPR()26*0eae32dcSDimitry Andric bool RegisterContextFreeBSDKernel_arm64::ReadGPR() { return true; }
27*0eae32dcSDimitry Andric
ReadFPR()28*0eae32dcSDimitry Andric bool RegisterContextFreeBSDKernel_arm64::ReadFPR() { return true; }
29*0eae32dcSDimitry Andric
WriteGPR()30*0eae32dcSDimitry Andric bool RegisterContextFreeBSDKernel_arm64::WriteGPR() {
31*0eae32dcSDimitry Andric assert(0);
32*0eae32dcSDimitry Andric return false;
33*0eae32dcSDimitry Andric }
34*0eae32dcSDimitry Andric
WriteFPR()35*0eae32dcSDimitry Andric bool RegisterContextFreeBSDKernel_arm64::WriteFPR() {
36*0eae32dcSDimitry Andric assert(0);
37*0eae32dcSDimitry Andric return false;
38*0eae32dcSDimitry Andric }
39*0eae32dcSDimitry Andric
ReadRegister(const RegisterInfo * reg_info,RegisterValue & value)40*0eae32dcSDimitry Andric bool RegisterContextFreeBSDKernel_arm64::ReadRegister(
41*0eae32dcSDimitry Andric const RegisterInfo *reg_info, RegisterValue &value) {
42*0eae32dcSDimitry Andric if (m_pcb_addr == LLDB_INVALID_ADDRESS)
43*0eae32dcSDimitry Andric return false;
44*0eae32dcSDimitry Andric
45*0eae32dcSDimitry Andric struct {
46*0eae32dcSDimitry Andric llvm::support::ulittle64_t x[30];
47*0eae32dcSDimitry Andric llvm::support::ulittle64_t lr;
48*0eae32dcSDimitry Andric llvm::support::ulittle64_t _reserved;
49*0eae32dcSDimitry Andric llvm::support::ulittle64_t sp;
50*0eae32dcSDimitry Andric } pcb;
51*0eae32dcSDimitry Andric
52*0eae32dcSDimitry Andric Status error;
53*0eae32dcSDimitry Andric size_t rd =
54*0eae32dcSDimitry Andric m_thread.GetProcess()->ReadMemory(m_pcb_addr, &pcb, sizeof(pcb), error);
55*0eae32dcSDimitry Andric if (rd != sizeof(pcb))
56*0eae32dcSDimitry Andric return false;
57*0eae32dcSDimitry Andric
58*0eae32dcSDimitry Andric uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
59*0eae32dcSDimitry Andric switch (reg) {
60*0eae32dcSDimitry Andric case gpr_x0_arm64:
61*0eae32dcSDimitry Andric case gpr_x1_arm64:
62*0eae32dcSDimitry Andric case gpr_x2_arm64:
63*0eae32dcSDimitry Andric case gpr_x3_arm64:
64*0eae32dcSDimitry Andric case gpr_x4_arm64:
65*0eae32dcSDimitry Andric case gpr_x5_arm64:
66*0eae32dcSDimitry Andric case gpr_x6_arm64:
67*0eae32dcSDimitry Andric case gpr_x7_arm64:
68*0eae32dcSDimitry Andric case gpr_x8_arm64:
69*0eae32dcSDimitry Andric case gpr_x9_arm64:
70*0eae32dcSDimitry Andric case gpr_x10_arm64:
71*0eae32dcSDimitry Andric case gpr_x11_arm64:
72*0eae32dcSDimitry Andric case gpr_x12_arm64:
73*0eae32dcSDimitry Andric case gpr_x13_arm64:
74*0eae32dcSDimitry Andric case gpr_x14_arm64:
75*0eae32dcSDimitry Andric case gpr_x15_arm64:
76*0eae32dcSDimitry Andric case gpr_x16_arm64:
77*0eae32dcSDimitry Andric case gpr_x17_arm64:
78*0eae32dcSDimitry Andric case gpr_x18_arm64:
79*0eae32dcSDimitry Andric case gpr_x19_arm64:
80*0eae32dcSDimitry Andric case gpr_x20_arm64:
81*0eae32dcSDimitry Andric case gpr_x21_arm64:
82*0eae32dcSDimitry Andric case gpr_x22_arm64:
83*0eae32dcSDimitry Andric case gpr_x23_arm64:
84*0eae32dcSDimitry Andric case gpr_x24_arm64:
85*0eae32dcSDimitry Andric case gpr_x25_arm64:
86*0eae32dcSDimitry Andric case gpr_x26_arm64:
87*0eae32dcSDimitry Andric case gpr_x27_arm64:
88*0eae32dcSDimitry Andric case gpr_x28_arm64:
89*0eae32dcSDimitry Andric case gpr_fp_arm64:
90*0eae32dcSDimitry Andric static_assert(gpr_fp_arm64 - gpr_x0_arm64 == 29,
91*0eae32dcSDimitry Andric "nonconsecutive arm64 register numbers");
92*0eae32dcSDimitry Andric value = pcb.x[reg - gpr_x0_arm64];
93*0eae32dcSDimitry Andric break;
94*0eae32dcSDimitry Andric case gpr_sp_arm64:
95*0eae32dcSDimitry Andric value = pcb.sp;
96*0eae32dcSDimitry Andric break;
97*0eae32dcSDimitry Andric case gpr_pc_arm64:
98*0eae32dcSDimitry Andric // The pc of crashing thread is stored in lr.
99*0eae32dcSDimitry Andric value = pcb.lr;
100*0eae32dcSDimitry Andric break;
101*0eae32dcSDimitry Andric default:
102*0eae32dcSDimitry Andric return false;
103*0eae32dcSDimitry Andric }
104*0eae32dcSDimitry Andric return true;
105*0eae32dcSDimitry Andric }
106*0eae32dcSDimitry Andric
WriteRegister(const RegisterInfo * reg_info,const RegisterValue & value)107*0eae32dcSDimitry Andric bool RegisterContextFreeBSDKernel_arm64::WriteRegister(
108*0eae32dcSDimitry Andric const RegisterInfo *reg_info, const RegisterValue &value) {
109*0eae32dcSDimitry Andric return false;
110*0eae32dcSDimitry Andric }
111