1d409305fSDimitry Andric //===-- NativeRegisterContextDBReg_arm64.h ----------------------*- C++ -*-===//
2d409305fSDimitry Andric //
3d409305fSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4d409305fSDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5d409305fSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6d409305fSDimitry Andric //
7d409305fSDimitry Andric //===----------------------------------------------------------------------===//
8d409305fSDimitry Andric 
9d409305fSDimitry Andric #ifndef lldb_NativeRegisterContextDBReg_arm64_h
10d409305fSDimitry Andric #define lldb_NativeRegisterContextDBReg_arm64_h
11d409305fSDimitry Andric 
12d409305fSDimitry Andric #include "Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h"
13d409305fSDimitry Andric 
14d409305fSDimitry Andric #include <array>
15d409305fSDimitry Andric 
16d409305fSDimitry Andric namespace lldb_private {
17d409305fSDimitry Andric 
18d409305fSDimitry Andric class NativeRegisterContextDBReg_arm64
19d409305fSDimitry Andric     : public virtual NativeRegisterContextRegisterInfo {
20d409305fSDimitry Andric public:
21d409305fSDimitry Andric   uint32_t NumSupportedHardwareBreakpoints() override;
22d409305fSDimitry Andric 
23d409305fSDimitry Andric   uint32_t SetHardwareBreakpoint(lldb::addr_t addr, size_t size) override;
24d409305fSDimitry Andric 
25d409305fSDimitry Andric   bool ClearHardwareBreakpoint(uint32_t hw_idx) override;
26d409305fSDimitry Andric 
27d409305fSDimitry Andric   Status ClearAllHardwareBreakpoints() override;
28d409305fSDimitry Andric 
29d409305fSDimitry Andric   Status GetHardwareBreakHitIndex(uint32_t &bp_index,
30d409305fSDimitry Andric                                   lldb::addr_t trap_addr) override;
31d409305fSDimitry Andric 
32d409305fSDimitry Andric   bool BreakpointIsEnabled(uint32_t bp_index);
33d409305fSDimitry Andric 
34d409305fSDimitry Andric   uint32_t NumSupportedHardwareWatchpoints() override;
35d409305fSDimitry Andric 
36d409305fSDimitry Andric   uint32_t SetHardwareWatchpoint(lldb::addr_t addr, size_t size,
37d409305fSDimitry Andric                                  uint32_t watch_flags) override;
38d409305fSDimitry Andric 
39d409305fSDimitry Andric   bool ClearHardwareWatchpoint(uint32_t hw_index) override;
40d409305fSDimitry Andric 
41d409305fSDimitry Andric   Status ClearAllHardwareWatchpoints() override;
42d409305fSDimitry Andric 
43d409305fSDimitry Andric   Status GetWatchpointHitIndex(uint32_t &wp_index,
44d409305fSDimitry Andric                                lldb::addr_t trap_addr) override;
45d409305fSDimitry Andric 
46d409305fSDimitry Andric   lldb::addr_t GetWatchpointHitAddress(uint32_t wp_index) override;
47d409305fSDimitry Andric 
48d409305fSDimitry Andric   lldb::addr_t GetWatchpointAddress(uint32_t wp_index) override;
49d409305fSDimitry Andric 
50d409305fSDimitry Andric   uint32_t GetWatchpointSize(uint32_t wp_index);
51d409305fSDimitry Andric 
52d409305fSDimitry Andric   bool WatchpointIsEnabled(uint32_t wp_index);
53d409305fSDimitry Andric 
54d409305fSDimitry Andric   // Debug register type select
55d409305fSDimitry Andric   enum DREGType { eDREGTypeWATCH = 0, eDREGTypeBREAK };
56d409305fSDimitry Andric 
57d409305fSDimitry Andric protected:
58*06c3fb27SDimitry Andric   /// Debug register info for hardware breakpoints and watchpoints management.
59*06c3fb27SDimitry Andric   /// Watchpoints: For a user requested size 4 at addr 0x1004, where BAS
60*06c3fb27SDimitry Andric   /// watchpoints are at doubleword (8-byte) alignment.
61*06c3fb27SDimitry Andric   ///   \a real_addr is 0x1004
62*06c3fb27SDimitry Andric   ///   \a address is 0x1000
63*06c3fb27SDimitry Andric   ///   size is 8
64*06c3fb27SDimitry Andric   ///   If a one-byte write to 0x1006 is the most recent watchpoint trap,
65*06c3fb27SDimitry Andric   ///   \a hit_addr is 0x1006
66d409305fSDimitry Andric   struct DREG {
67d409305fSDimitry Andric     lldb::addr_t address;  // Breakpoint/watchpoint address value.
68d409305fSDimitry Andric     lldb::addr_t hit_addr; // Address at which last watchpoint trigger exception
69d409305fSDimitry Andric                            // occurred.
70d409305fSDimitry Andric     lldb::addr_t real_addr; // Address value that should cause target to stop.
71d409305fSDimitry Andric     uint32_t control;       // Breakpoint/watchpoint control value.
72d409305fSDimitry Andric   };
73d409305fSDimitry Andric 
74d409305fSDimitry Andric   std::array<struct DREG, 16> m_hbp_regs; // hardware breakpoints
75d409305fSDimitry Andric   std::array<struct DREG, 16> m_hwp_regs; // hardware watchpoints
76d409305fSDimitry Andric 
77d409305fSDimitry Andric   uint32_t m_max_hbp_supported;
78d409305fSDimitry Andric   uint32_t m_max_hwp_supported;
79d409305fSDimitry Andric 
80d409305fSDimitry Andric   virtual llvm::Error ReadHardwareDebugInfo() = 0;
81d409305fSDimitry Andric   virtual llvm::Error WriteHardwareDebugRegs(DREGType hwbType) = 0;
FixWatchpointHitAddress(lldb::addr_t hit_addr)82fe6060f1SDimitry Andric   virtual lldb::addr_t FixWatchpointHitAddress(lldb::addr_t hit_addr) {
83fe6060f1SDimitry Andric     return hit_addr;
84fe6060f1SDimitry Andric   }
85d409305fSDimitry Andric };
86d409305fSDimitry Andric 
87d409305fSDimitry Andric } // namespace lldb_private
88d409305fSDimitry Andric 
89d409305fSDimitry Andric #endif // #ifndef lldb_NativeRegisterContextDBReg_arm64_h
90