10b57cec5SDimitry Andric //===-- RegisterContextDarwin_arm.cpp ---------------------------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 90b57cec5SDimitry Andric #include "RegisterContextDarwin_arm.h" 100b57cec5SDimitry Andric #include "RegisterContextDarwinConstants.h" 110b57cec5SDimitry Andric 120b57cec5SDimitry Andric #include "lldb/Utility/DataBufferHeap.h" 130b57cec5SDimitry Andric #include "lldb/Utility/DataExtractor.h" 140b57cec5SDimitry Andric #include "lldb/Utility/Endian.h" 150b57cec5SDimitry Andric #include "lldb/Utility/Log.h" 160b57cec5SDimitry Andric #include "lldb/Utility/RegisterValue.h" 170b57cec5SDimitry Andric #include "lldb/Utility/Scalar.h" 180b57cec5SDimitry Andric #include "llvm/Support/Compiler.h" 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric #include "Plugins/Process/Utility/InstructionUtils.h" 210b57cec5SDimitry Andric 220b57cec5SDimitry Andric #include <memory> 230b57cec5SDimitry Andric 240b57cec5SDimitry Andric // Support building against older versions of LLVM, this macro was added 250b57cec5SDimitry Andric // recently. 260b57cec5SDimitry Andric #ifndef LLVM_EXTENSION 270b57cec5SDimitry Andric #define LLVM_EXTENSION 280b57cec5SDimitry Andric #endif 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric #include "Utility/ARM_DWARF_Registers.h" 310b57cec5SDimitry Andric #include "Utility/ARM_ehframe_Registers.h" 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric #include "llvm/ADT/STLExtras.h" 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric using namespace lldb; 360b57cec5SDimitry Andric using namespace lldb_private; 370b57cec5SDimitry Andric 380b57cec5SDimitry Andric enum { 390b57cec5SDimitry Andric gpr_r0 = 0, 400b57cec5SDimitry Andric gpr_r1, 410b57cec5SDimitry Andric gpr_r2, 420b57cec5SDimitry Andric gpr_r3, 430b57cec5SDimitry Andric gpr_r4, 440b57cec5SDimitry Andric gpr_r5, 450b57cec5SDimitry Andric gpr_r6, 460b57cec5SDimitry Andric gpr_r7, 470b57cec5SDimitry Andric gpr_r8, 480b57cec5SDimitry Andric gpr_r9, 490b57cec5SDimitry Andric gpr_r10, 500b57cec5SDimitry Andric gpr_r11, 510b57cec5SDimitry Andric gpr_r12, 520b57cec5SDimitry Andric gpr_r13, 530b57cec5SDimitry Andric gpr_sp = gpr_r13, 540b57cec5SDimitry Andric gpr_r14, 550b57cec5SDimitry Andric gpr_lr = gpr_r14, 560b57cec5SDimitry Andric gpr_r15, 570b57cec5SDimitry Andric gpr_pc = gpr_r15, 580b57cec5SDimitry Andric gpr_cpsr, 590b57cec5SDimitry Andric 600b57cec5SDimitry Andric fpu_s0, 610b57cec5SDimitry Andric fpu_s1, 620b57cec5SDimitry Andric fpu_s2, 630b57cec5SDimitry Andric fpu_s3, 640b57cec5SDimitry Andric fpu_s4, 650b57cec5SDimitry Andric fpu_s5, 660b57cec5SDimitry Andric fpu_s6, 670b57cec5SDimitry Andric fpu_s7, 680b57cec5SDimitry Andric fpu_s8, 690b57cec5SDimitry Andric fpu_s9, 700b57cec5SDimitry Andric fpu_s10, 710b57cec5SDimitry Andric fpu_s11, 720b57cec5SDimitry Andric fpu_s12, 730b57cec5SDimitry Andric fpu_s13, 740b57cec5SDimitry Andric fpu_s14, 750b57cec5SDimitry Andric fpu_s15, 760b57cec5SDimitry Andric fpu_s16, 770b57cec5SDimitry Andric fpu_s17, 780b57cec5SDimitry Andric fpu_s18, 790b57cec5SDimitry Andric fpu_s19, 800b57cec5SDimitry Andric fpu_s20, 810b57cec5SDimitry Andric fpu_s21, 820b57cec5SDimitry Andric fpu_s22, 830b57cec5SDimitry Andric fpu_s23, 840b57cec5SDimitry Andric fpu_s24, 850b57cec5SDimitry Andric fpu_s25, 860b57cec5SDimitry Andric fpu_s26, 870b57cec5SDimitry Andric fpu_s27, 880b57cec5SDimitry Andric fpu_s28, 890b57cec5SDimitry Andric fpu_s29, 900b57cec5SDimitry Andric fpu_s30, 910b57cec5SDimitry Andric fpu_s31, 920b57cec5SDimitry Andric fpu_fpscr, 930b57cec5SDimitry Andric 940b57cec5SDimitry Andric exc_exception, 950b57cec5SDimitry Andric exc_fsr, 960b57cec5SDimitry Andric exc_far, 970b57cec5SDimitry Andric 980b57cec5SDimitry Andric dbg_bvr0, 990b57cec5SDimitry Andric dbg_bvr1, 1000b57cec5SDimitry Andric dbg_bvr2, 1010b57cec5SDimitry Andric dbg_bvr3, 1020b57cec5SDimitry Andric dbg_bvr4, 1030b57cec5SDimitry Andric dbg_bvr5, 1040b57cec5SDimitry Andric dbg_bvr6, 1050b57cec5SDimitry Andric dbg_bvr7, 1060b57cec5SDimitry Andric dbg_bvr8, 1070b57cec5SDimitry Andric dbg_bvr9, 1080b57cec5SDimitry Andric dbg_bvr10, 1090b57cec5SDimitry Andric dbg_bvr11, 1100b57cec5SDimitry Andric dbg_bvr12, 1110b57cec5SDimitry Andric dbg_bvr13, 1120b57cec5SDimitry Andric dbg_bvr14, 1130b57cec5SDimitry Andric dbg_bvr15, 1140b57cec5SDimitry Andric 1150b57cec5SDimitry Andric dbg_bcr0, 1160b57cec5SDimitry Andric dbg_bcr1, 1170b57cec5SDimitry Andric dbg_bcr2, 1180b57cec5SDimitry Andric dbg_bcr3, 1190b57cec5SDimitry Andric dbg_bcr4, 1200b57cec5SDimitry Andric dbg_bcr5, 1210b57cec5SDimitry Andric dbg_bcr6, 1220b57cec5SDimitry Andric dbg_bcr7, 1230b57cec5SDimitry Andric dbg_bcr8, 1240b57cec5SDimitry Andric dbg_bcr9, 1250b57cec5SDimitry Andric dbg_bcr10, 1260b57cec5SDimitry Andric dbg_bcr11, 1270b57cec5SDimitry Andric dbg_bcr12, 1280b57cec5SDimitry Andric dbg_bcr13, 1290b57cec5SDimitry Andric dbg_bcr14, 1300b57cec5SDimitry Andric dbg_bcr15, 1310b57cec5SDimitry Andric 1320b57cec5SDimitry Andric dbg_wvr0, 1330b57cec5SDimitry Andric dbg_wvr1, 1340b57cec5SDimitry Andric dbg_wvr2, 1350b57cec5SDimitry Andric dbg_wvr3, 1360b57cec5SDimitry Andric dbg_wvr4, 1370b57cec5SDimitry Andric dbg_wvr5, 1380b57cec5SDimitry Andric dbg_wvr6, 1390b57cec5SDimitry Andric dbg_wvr7, 1400b57cec5SDimitry Andric dbg_wvr8, 1410b57cec5SDimitry Andric dbg_wvr9, 1420b57cec5SDimitry Andric dbg_wvr10, 1430b57cec5SDimitry Andric dbg_wvr11, 1440b57cec5SDimitry Andric dbg_wvr12, 1450b57cec5SDimitry Andric dbg_wvr13, 1460b57cec5SDimitry Andric dbg_wvr14, 1470b57cec5SDimitry Andric dbg_wvr15, 1480b57cec5SDimitry Andric 1490b57cec5SDimitry Andric dbg_wcr0, 1500b57cec5SDimitry Andric dbg_wcr1, 1510b57cec5SDimitry Andric dbg_wcr2, 1520b57cec5SDimitry Andric dbg_wcr3, 1530b57cec5SDimitry Andric dbg_wcr4, 1540b57cec5SDimitry Andric dbg_wcr5, 1550b57cec5SDimitry Andric dbg_wcr6, 1560b57cec5SDimitry Andric dbg_wcr7, 1570b57cec5SDimitry Andric dbg_wcr8, 1580b57cec5SDimitry Andric dbg_wcr9, 1590b57cec5SDimitry Andric dbg_wcr10, 1600b57cec5SDimitry Andric dbg_wcr11, 1610b57cec5SDimitry Andric dbg_wcr12, 1620b57cec5SDimitry Andric dbg_wcr13, 1630b57cec5SDimitry Andric dbg_wcr14, 1640b57cec5SDimitry Andric dbg_wcr15, 1650b57cec5SDimitry Andric 1660b57cec5SDimitry Andric k_num_registers 1670b57cec5SDimitry Andric }; 1680b57cec5SDimitry Andric 1690b57cec5SDimitry Andric #define GPR_OFFSET(idx) ((idx)*4) 1700b57cec5SDimitry Andric #define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR)) 1710b57cec5SDimitry Andric #define EXC_OFFSET(idx) \ 1720b57cec5SDimitry Andric ((idx)*4 + sizeof(RegisterContextDarwin_arm::GPR) + \ 1730b57cec5SDimitry Andric sizeof(RegisterContextDarwin_arm::FPU)) 1740b57cec5SDimitry Andric #define DBG_OFFSET(reg) \ 1750b57cec5SDimitry Andric ((LLVM_EXTENSION offsetof(RegisterContextDarwin_arm::DBG, reg) + \ 1760b57cec5SDimitry Andric sizeof(RegisterContextDarwin_arm::GPR) + \ 1770b57cec5SDimitry Andric sizeof(RegisterContextDarwin_arm::FPU) + \ 1780b57cec5SDimitry Andric sizeof(RegisterContextDarwin_arm::EXC))) 1790b57cec5SDimitry Andric 1800b57cec5SDimitry Andric #define DEFINE_DBG(reg, i) \ 1810b57cec5SDimitry Andric #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *) NULL)->reg[i]), \ 1820b57cec5SDimitry Andric DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \ 1830b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 1840b57cec5SDimitry Andric LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 1850b57cec5SDimitry Andric LLDB_INVALID_REGNUM }, \ 1860b57cec5SDimitry Andric nullptr, nullptr, nullptr, 0 1870b57cec5SDimitry Andric #define REG_CONTEXT_SIZE \ 1880b57cec5SDimitry Andric (sizeof(RegisterContextDarwin_arm::GPR) + \ 1890b57cec5SDimitry Andric sizeof(RegisterContextDarwin_arm::FPU) + \ 1900b57cec5SDimitry Andric sizeof(RegisterContextDarwin_arm::EXC)) 1910b57cec5SDimitry Andric 1920b57cec5SDimitry Andric static RegisterInfo g_register_infos[] = { 1930b57cec5SDimitry Andric // General purpose registers 1940b57cec5SDimitry Andric // NAME ALT SZ OFFSET ENCODING FORMAT 1950b57cec5SDimitry Andric // EH_FRAME DWARF GENERIC 1960b57cec5SDimitry Andric // PROCESS PLUGIN LLDB NATIVE 1970b57cec5SDimitry Andric // ====== ======= == ============= ============= ============ 1980b57cec5SDimitry Andric // =============== =============== ========================= 1990b57cec5SDimitry Andric // ===================== ============= 2000b57cec5SDimitry Andric {"r0", 2010b57cec5SDimitry Andric nullptr, 2020b57cec5SDimitry Andric 4, 2030b57cec5SDimitry Andric GPR_OFFSET(0), 2040b57cec5SDimitry Andric eEncodingUint, 2050b57cec5SDimitry Andric eFormatHex, 2060b57cec5SDimitry Andric {ehframe_r0, dwarf_r0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r0}, 2070b57cec5SDimitry Andric nullptr, 2080b57cec5SDimitry Andric nullptr, 2090b57cec5SDimitry Andric nullptr, 2100b57cec5SDimitry Andric 0}, 2110b57cec5SDimitry Andric {"r1", 2120b57cec5SDimitry Andric nullptr, 2130b57cec5SDimitry Andric 4, 2140b57cec5SDimitry Andric GPR_OFFSET(1), 2150b57cec5SDimitry Andric eEncodingUint, 2160b57cec5SDimitry Andric eFormatHex, 2170b57cec5SDimitry Andric {ehframe_r1, dwarf_r1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r1}, 2180b57cec5SDimitry Andric nullptr, 2190b57cec5SDimitry Andric nullptr, 2200b57cec5SDimitry Andric nullptr, 2210b57cec5SDimitry Andric 0}, 2220b57cec5SDimitry Andric {"r2", 2230b57cec5SDimitry Andric nullptr, 2240b57cec5SDimitry Andric 4, 2250b57cec5SDimitry Andric GPR_OFFSET(2), 2260b57cec5SDimitry Andric eEncodingUint, 2270b57cec5SDimitry Andric eFormatHex, 2280b57cec5SDimitry Andric {ehframe_r2, dwarf_r2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r2}, 2290b57cec5SDimitry Andric nullptr, 2300b57cec5SDimitry Andric nullptr, 2310b57cec5SDimitry Andric nullptr, 2320b57cec5SDimitry Andric 0}, 2330b57cec5SDimitry Andric {"r3", 2340b57cec5SDimitry Andric nullptr, 2350b57cec5SDimitry Andric 4, 2360b57cec5SDimitry Andric GPR_OFFSET(3), 2370b57cec5SDimitry Andric eEncodingUint, 2380b57cec5SDimitry Andric eFormatHex, 2390b57cec5SDimitry Andric {ehframe_r3, dwarf_r3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r3}, 2400b57cec5SDimitry Andric nullptr, 2410b57cec5SDimitry Andric nullptr, 2420b57cec5SDimitry Andric nullptr, 2430b57cec5SDimitry Andric 0}, 2440b57cec5SDimitry Andric {"r4", 2450b57cec5SDimitry Andric nullptr, 2460b57cec5SDimitry Andric 4, 2470b57cec5SDimitry Andric GPR_OFFSET(4), 2480b57cec5SDimitry Andric eEncodingUint, 2490b57cec5SDimitry Andric eFormatHex, 2500b57cec5SDimitry Andric {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4}, 2510b57cec5SDimitry Andric nullptr, 2520b57cec5SDimitry Andric nullptr, 2530b57cec5SDimitry Andric nullptr, 2540b57cec5SDimitry Andric 0}, 2550b57cec5SDimitry Andric {"r5", 2560b57cec5SDimitry Andric nullptr, 2570b57cec5SDimitry Andric 4, 2580b57cec5SDimitry Andric GPR_OFFSET(5), 2590b57cec5SDimitry Andric eEncodingUint, 2600b57cec5SDimitry Andric eFormatHex, 2610b57cec5SDimitry Andric {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5}, 2620b57cec5SDimitry Andric nullptr, 2630b57cec5SDimitry Andric nullptr, 2640b57cec5SDimitry Andric nullptr, 2650b57cec5SDimitry Andric 0}, 2660b57cec5SDimitry Andric {"r6", 2670b57cec5SDimitry Andric nullptr, 2680b57cec5SDimitry Andric 4, 2690b57cec5SDimitry Andric GPR_OFFSET(6), 2700b57cec5SDimitry Andric eEncodingUint, 2710b57cec5SDimitry Andric eFormatHex, 2720b57cec5SDimitry Andric {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6}, 2730b57cec5SDimitry Andric nullptr, 2740b57cec5SDimitry Andric nullptr, 2750b57cec5SDimitry Andric nullptr, 2760b57cec5SDimitry Andric 0}, 2770b57cec5SDimitry Andric {"r7", 2780b57cec5SDimitry Andric nullptr, 2790b57cec5SDimitry Andric 4, 2800b57cec5SDimitry Andric GPR_OFFSET(7), 2810b57cec5SDimitry Andric eEncodingUint, 2820b57cec5SDimitry Andric eFormatHex, 2830b57cec5SDimitry Andric {ehframe_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, 2840b57cec5SDimitry Andric gpr_r7}, 2850b57cec5SDimitry Andric nullptr, 2860b57cec5SDimitry Andric nullptr, 2870b57cec5SDimitry Andric nullptr, 2880b57cec5SDimitry Andric 0}, 2890b57cec5SDimitry Andric {"r8", 2900b57cec5SDimitry Andric nullptr, 2910b57cec5SDimitry Andric 4, 2920b57cec5SDimitry Andric GPR_OFFSET(8), 2930b57cec5SDimitry Andric eEncodingUint, 2940b57cec5SDimitry Andric eFormatHex, 2950b57cec5SDimitry Andric {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8}, 2960b57cec5SDimitry Andric nullptr, 2970b57cec5SDimitry Andric nullptr, 2980b57cec5SDimitry Andric nullptr, 2990b57cec5SDimitry Andric 0}, 3000b57cec5SDimitry Andric {"r9", 3010b57cec5SDimitry Andric nullptr, 3020b57cec5SDimitry Andric 4, 3030b57cec5SDimitry Andric GPR_OFFSET(9), 3040b57cec5SDimitry Andric eEncodingUint, 3050b57cec5SDimitry Andric eFormatHex, 3060b57cec5SDimitry Andric {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9}, 3070b57cec5SDimitry Andric nullptr, 3080b57cec5SDimitry Andric nullptr, 3090b57cec5SDimitry Andric nullptr, 3100b57cec5SDimitry Andric 0}, 3110b57cec5SDimitry Andric {"r10", 3120b57cec5SDimitry Andric nullptr, 3130b57cec5SDimitry Andric 4, 3140b57cec5SDimitry Andric GPR_OFFSET(10), 3150b57cec5SDimitry Andric eEncodingUint, 3160b57cec5SDimitry Andric eFormatHex, 3170b57cec5SDimitry Andric {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 3180b57cec5SDimitry Andric gpr_r10}, 3190b57cec5SDimitry Andric nullptr, 3200b57cec5SDimitry Andric nullptr, 3210b57cec5SDimitry Andric nullptr, 3220b57cec5SDimitry Andric 0}, 3230b57cec5SDimitry Andric {"r11", 3240b57cec5SDimitry Andric nullptr, 3250b57cec5SDimitry Andric 4, 3260b57cec5SDimitry Andric GPR_OFFSET(11), 3270b57cec5SDimitry Andric eEncodingUint, 3280b57cec5SDimitry Andric eFormatHex, 3290b57cec5SDimitry Andric {ehframe_r11, dwarf_r11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 3300b57cec5SDimitry Andric gpr_r11}, 3310b57cec5SDimitry Andric nullptr, 3320b57cec5SDimitry Andric nullptr, 3330b57cec5SDimitry Andric nullptr, 3340b57cec5SDimitry Andric 0}, 3350b57cec5SDimitry Andric {"r12", 3360b57cec5SDimitry Andric nullptr, 3370b57cec5SDimitry Andric 4, 3380b57cec5SDimitry Andric GPR_OFFSET(12), 3390b57cec5SDimitry Andric eEncodingUint, 3400b57cec5SDimitry Andric eFormatHex, 3410b57cec5SDimitry Andric {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 3420b57cec5SDimitry Andric gpr_r12}, 3430b57cec5SDimitry Andric nullptr, 3440b57cec5SDimitry Andric nullptr, 3450b57cec5SDimitry Andric nullptr, 3460b57cec5SDimitry Andric 0}, 3470b57cec5SDimitry Andric {"sp", 3480b57cec5SDimitry Andric "r13", 3490b57cec5SDimitry Andric 4, 3500b57cec5SDimitry Andric GPR_OFFSET(13), 3510b57cec5SDimitry Andric eEncodingUint, 3520b57cec5SDimitry Andric eFormatHex, 3530b57cec5SDimitry Andric {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, 3540b57cec5SDimitry Andric gpr_sp}, 3550b57cec5SDimitry Andric nullptr, 3560b57cec5SDimitry Andric nullptr, 3570b57cec5SDimitry Andric nullptr, 3580b57cec5SDimitry Andric 0}, 3590b57cec5SDimitry Andric {"lr", 3600b57cec5SDimitry Andric "r14", 3610b57cec5SDimitry Andric 4, 3620b57cec5SDimitry Andric GPR_OFFSET(14), 3630b57cec5SDimitry Andric eEncodingUint, 3640b57cec5SDimitry Andric eFormatHex, 3650b57cec5SDimitry Andric {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, 3660b57cec5SDimitry Andric gpr_lr}, 3670b57cec5SDimitry Andric nullptr, 3680b57cec5SDimitry Andric nullptr, 3690b57cec5SDimitry Andric nullptr, 3700b57cec5SDimitry Andric 0}, 3710b57cec5SDimitry Andric {"pc", 3720b57cec5SDimitry Andric "r15", 3730b57cec5SDimitry Andric 4, 3740b57cec5SDimitry Andric GPR_OFFSET(15), 3750b57cec5SDimitry Andric eEncodingUint, 3760b57cec5SDimitry Andric eFormatHex, 3770b57cec5SDimitry Andric {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, 3780b57cec5SDimitry Andric gpr_pc}, 3790b57cec5SDimitry Andric nullptr, 3800b57cec5SDimitry Andric nullptr, 3810b57cec5SDimitry Andric nullptr, 3820b57cec5SDimitry Andric 0}, 3830b57cec5SDimitry Andric {"cpsr", 3840b57cec5SDimitry Andric "psr", 3850b57cec5SDimitry Andric 4, 3860b57cec5SDimitry Andric GPR_OFFSET(16), 3870b57cec5SDimitry Andric eEncodingUint, 3880b57cec5SDimitry Andric eFormatHex, 3890b57cec5SDimitry Andric {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM, 3900b57cec5SDimitry Andric gpr_cpsr}, 3910b57cec5SDimitry Andric nullptr, 3920b57cec5SDimitry Andric nullptr, 3930b57cec5SDimitry Andric nullptr, 3940b57cec5SDimitry Andric 0}, 3950b57cec5SDimitry Andric 3960b57cec5SDimitry Andric {"s0", 3970b57cec5SDimitry Andric nullptr, 3980b57cec5SDimitry Andric 4, 3990b57cec5SDimitry Andric FPU_OFFSET(0), 4000b57cec5SDimitry Andric eEncodingIEEE754, 4010b57cec5SDimitry Andric eFormatFloat, 4020b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 4030b57cec5SDimitry Andric fpu_s0}, 4040b57cec5SDimitry Andric nullptr, 4050b57cec5SDimitry Andric nullptr, 4060b57cec5SDimitry Andric nullptr, 4070b57cec5SDimitry Andric 0}, 4080b57cec5SDimitry Andric {"s1", 4090b57cec5SDimitry Andric nullptr, 4100b57cec5SDimitry Andric 4, 4110b57cec5SDimitry Andric FPU_OFFSET(1), 4120b57cec5SDimitry Andric eEncodingIEEE754, 4130b57cec5SDimitry Andric eFormatFloat, 4140b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 4150b57cec5SDimitry Andric fpu_s1}, 4160b57cec5SDimitry Andric nullptr, 4170b57cec5SDimitry Andric nullptr, 4180b57cec5SDimitry Andric nullptr, 4190b57cec5SDimitry Andric 0}, 4200b57cec5SDimitry Andric {"s2", 4210b57cec5SDimitry Andric nullptr, 4220b57cec5SDimitry Andric 4, 4230b57cec5SDimitry Andric FPU_OFFSET(2), 4240b57cec5SDimitry Andric eEncodingIEEE754, 4250b57cec5SDimitry Andric eFormatFloat, 4260b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 4270b57cec5SDimitry Andric fpu_s2}, 4280b57cec5SDimitry Andric nullptr, 4290b57cec5SDimitry Andric nullptr, 4300b57cec5SDimitry Andric nullptr, 4310b57cec5SDimitry Andric 0}, 4320b57cec5SDimitry Andric {"s3", 4330b57cec5SDimitry Andric nullptr, 4340b57cec5SDimitry Andric 4, 4350b57cec5SDimitry Andric FPU_OFFSET(3), 4360b57cec5SDimitry Andric eEncodingIEEE754, 4370b57cec5SDimitry Andric eFormatFloat, 4380b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 4390b57cec5SDimitry Andric fpu_s3}, 4400b57cec5SDimitry Andric nullptr, 4410b57cec5SDimitry Andric nullptr, 4420b57cec5SDimitry Andric nullptr, 4430b57cec5SDimitry Andric 0}, 4440b57cec5SDimitry Andric {"s4", 4450b57cec5SDimitry Andric nullptr, 4460b57cec5SDimitry Andric 4, 4470b57cec5SDimitry Andric FPU_OFFSET(4), 4480b57cec5SDimitry Andric eEncodingIEEE754, 4490b57cec5SDimitry Andric eFormatFloat, 4500b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 4510b57cec5SDimitry Andric fpu_s4}, 4520b57cec5SDimitry Andric nullptr, 4530b57cec5SDimitry Andric nullptr, 4540b57cec5SDimitry Andric nullptr, 4550b57cec5SDimitry Andric 0}, 4560b57cec5SDimitry Andric {"s5", 4570b57cec5SDimitry Andric nullptr, 4580b57cec5SDimitry Andric 4, 4590b57cec5SDimitry Andric FPU_OFFSET(5), 4600b57cec5SDimitry Andric eEncodingIEEE754, 4610b57cec5SDimitry Andric eFormatFloat, 4620b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 4630b57cec5SDimitry Andric fpu_s5}, 4640b57cec5SDimitry Andric nullptr, 4650b57cec5SDimitry Andric nullptr, 4660b57cec5SDimitry Andric nullptr, 4670b57cec5SDimitry Andric 0}, 4680b57cec5SDimitry Andric {"s6", 4690b57cec5SDimitry Andric nullptr, 4700b57cec5SDimitry Andric 4, 4710b57cec5SDimitry Andric FPU_OFFSET(6), 4720b57cec5SDimitry Andric eEncodingIEEE754, 4730b57cec5SDimitry Andric eFormatFloat, 4740b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 4750b57cec5SDimitry Andric fpu_s6}, 4760b57cec5SDimitry Andric nullptr, 4770b57cec5SDimitry Andric nullptr, 4780b57cec5SDimitry Andric nullptr, 4790b57cec5SDimitry Andric 0}, 4800b57cec5SDimitry Andric {"s7", 4810b57cec5SDimitry Andric nullptr, 4820b57cec5SDimitry Andric 4, 4830b57cec5SDimitry Andric FPU_OFFSET(7), 4840b57cec5SDimitry Andric eEncodingIEEE754, 4850b57cec5SDimitry Andric eFormatFloat, 4860b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 4870b57cec5SDimitry Andric fpu_s7}, 4880b57cec5SDimitry Andric nullptr, 4890b57cec5SDimitry Andric nullptr, 4900b57cec5SDimitry Andric nullptr, 4910b57cec5SDimitry Andric 0}, 4920b57cec5SDimitry Andric {"s8", 4930b57cec5SDimitry Andric nullptr, 4940b57cec5SDimitry Andric 4, 4950b57cec5SDimitry Andric FPU_OFFSET(8), 4960b57cec5SDimitry Andric eEncodingIEEE754, 4970b57cec5SDimitry Andric eFormatFloat, 4980b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 4990b57cec5SDimitry Andric fpu_s8}, 5000b57cec5SDimitry Andric nullptr, 5010b57cec5SDimitry Andric nullptr, 5020b57cec5SDimitry Andric nullptr, 5030b57cec5SDimitry Andric 0}, 5040b57cec5SDimitry Andric {"s9", 5050b57cec5SDimitry Andric nullptr, 5060b57cec5SDimitry Andric 4, 5070b57cec5SDimitry Andric FPU_OFFSET(9), 5080b57cec5SDimitry Andric eEncodingIEEE754, 5090b57cec5SDimitry Andric eFormatFloat, 5100b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 5110b57cec5SDimitry Andric fpu_s9}, 5120b57cec5SDimitry Andric nullptr, 5130b57cec5SDimitry Andric nullptr, 5140b57cec5SDimitry Andric nullptr, 5150b57cec5SDimitry Andric 0}, 5160b57cec5SDimitry Andric {"s10", 5170b57cec5SDimitry Andric nullptr, 5180b57cec5SDimitry Andric 4, 5190b57cec5SDimitry Andric FPU_OFFSET(10), 5200b57cec5SDimitry Andric eEncodingIEEE754, 5210b57cec5SDimitry Andric eFormatFloat, 5220b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 5230b57cec5SDimitry Andric fpu_s10}, 5240b57cec5SDimitry Andric nullptr, 5250b57cec5SDimitry Andric nullptr, 5260b57cec5SDimitry Andric nullptr, 5270b57cec5SDimitry Andric 0}, 5280b57cec5SDimitry Andric {"s11", 5290b57cec5SDimitry Andric nullptr, 5300b57cec5SDimitry Andric 4, 5310b57cec5SDimitry Andric FPU_OFFSET(11), 5320b57cec5SDimitry Andric eEncodingIEEE754, 5330b57cec5SDimitry Andric eFormatFloat, 5340b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 5350b57cec5SDimitry Andric fpu_s11}, 5360b57cec5SDimitry Andric nullptr, 5370b57cec5SDimitry Andric nullptr, 5380b57cec5SDimitry Andric nullptr, 5390b57cec5SDimitry Andric 0}, 5400b57cec5SDimitry Andric {"s12", 5410b57cec5SDimitry Andric nullptr, 5420b57cec5SDimitry Andric 4, 5430b57cec5SDimitry Andric FPU_OFFSET(12), 5440b57cec5SDimitry Andric eEncodingIEEE754, 5450b57cec5SDimitry Andric eFormatFloat, 5460b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 5470b57cec5SDimitry Andric fpu_s12}, 5480b57cec5SDimitry Andric nullptr, 5490b57cec5SDimitry Andric nullptr, 5500b57cec5SDimitry Andric nullptr, 5510b57cec5SDimitry Andric 0}, 5520b57cec5SDimitry Andric {"s13", 5530b57cec5SDimitry Andric nullptr, 5540b57cec5SDimitry Andric 4, 5550b57cec5SDimitry Andric FPU_OFFSET(13), 5560b57cec5SDimitry Andric eEncodingIEEE754, 5570b57cec5SDimitry Andric eFormatFloat, 5580b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 5590b57cec5SDimitry Andric fpu_s13}, 5600b57cec5SDimitry Andric nullptr, 5610b57cec5SDimitry Andric nullptr, 5620b57cec5SDimitry Andric nullptr, 5630b57cec5SDimitry Andric 0}, 5640b57cec5SDimitry Andric {"s14", 5650b57cec5SDimitry Andric nullptr, 5660b57cec5SDimitry Andric 4, 5670b57cec5SDimitry Andric FPU_OFFSET(14), 5680b57cec5SDimitry Andric eEncodingIEEE754, 5690b57cec5SDimitry Andric eFormatFloat, 5700b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 5710b57cec5SDimitry Andric fpu_s14}, 5720b57cec5SDimitry Andric nullptr, 5730b57cec5SDimitry Andric nullptr, 5740b57cec5SDimitry Andric nullptr, 5750b57cec5SDimitry Andric 0}, 5760b57cec5SDimitry Andric {"s15", 5770b57cec5SDimitry Andric nullptr, 5780b57cec5SDimitry Andric 4, 5790b57cec5SDimitry Andric FPU_OFFSET(15), 5800b57cec5SDimitry Andric eEncodingIEEE754, 5810b57cec5SDimitry Andric eFormatFloat, 5820b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 5830b57cec5SDimitry Andric fpu_s15}, 5840b57cec5SDimitry Andric nullptr, 5850b57cec5SDimitry Andric nullptr, 5860b57cec5SDimitry Andric nullptr, 5870b57cec5SDimitry Andric 0}, 5880b57cec5SDimitry Andric {"s16", 5890b57cec5SDimitry Andric nullptr, 5900b57cec5SDimitry Andric 4, 5910b57cec5SDimitry Andric FPU_OFFSET(16), 5920b57cec5SDimitry Andric eEncodingIEEE754, 5930b57cec5SDimitry Andric eFormatFloat, 5940b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 5950b57cec5SDimitry Andric fpu_s16}, 5960b57cec5SDimitry Andric nullptr, 5970b57cec5SDimitry Andric nullptr, 5980b57cec5SDimitry Andric nullptr, 5990b57cec5SDimitry Andric 0}, 6000b57cec5SDimitry Andric {"s17", 6010b57cec5SDimitry Andric nullptr, 6020b57cec5SDimitry Andric 4, 6030b57cec5SDimitry Andric FPU_OFFSET(17), 6040b57cec5SDimitry Andric eEncodingIEEE754, 6050b57cec5SDimitry Andric eFormatFloat, 6060b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 6070b57cec5SDimitry Andric fpu_s17}, 6080b57cec5SDimitry Andric nullptr, 6090b57cec5SDimitry Andric nullptr, 6100b57cec5SDimitry Andric nullptr, 6110b57cec5SDimitry Andric 0}, 6120b57cec5SDimitry Andric {"s18", 6130b57cec5SDimitry Andric nullptr, 6140b57cec5SDimitry Andric 4, 6150b57cec5SDimitry Andric FPU_OFFSET(18), 6160b57cec5SDimitry Andric eEncodingIEEE754, 6170b57cec5SDimitry Andric eFormatFloat, 6180b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 6190b57cec5SDimitry Andric fpu_s18}, 6200b57cec5SDimitry Andric nullptr, 6210b57cec5SDimitry Andric nullptr, 6220b57cec5SDimitry Andric nullptr, 6230b57cec5SDimitry Andric 0}, 6240b57cec5SDimitry Andric {"s19", 6250b57cec5SDimitry Andric nullptr, 6260b57cec5SDimitry Andric 4, 6270b57cec5SDimitry Andric FPU_OFFSET(19), 6280b57cec5SDimitry Andric eEncodingIEEE754, 6290b57cec5SDimitry Andric eFormatFloat, 6300b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 6310b57cec5SDimitry Andric fpu_s19}, 6320b57cec5SDimitry Andric nullptr, 6330b57cec5SDimitry Andric nullptr, 6340b57cec5SDimitry Andric nullptr, 6350b57cec5SDimitry Andric 0}, 6360b57cec5SDimitry Andric {"s20", 6370b57cec5SDimitry Andric nullptr, 6380b57cec5SDimitry Andric 4, 6390b57cec5SDimitry Andric FPU_OFFSET(20), 6400b57cec5SDimitry Andric eEncodingIEEE754, 6410b57cec5SDimitry Andric eFormatFloat, 6420b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 6430b57cec5SDimitry Andric fpu_s20}, 6440b57cec5SDimitry Andric nullptr, 6450b57cec5SDimitry Andric nullptr, 6460b57cec5SDimitry Andric nullptr, 6470b57cec5SDimitry Andric 0}, 6480b57cec5SDimitry Andric {"s21", 6490b57cec5SDimitry Andric nullptr, 6500b57cec5SDimitry Andric 4, 6510b57cec5SDimitry Andric FPU_OFFSET(21), 6520b57cec5SDimitry Andric eEncodingIEEE754, 6530b57cec5SDimitry Andric eFormatFloat, 6540b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 6550b57cec5SDimitry Andric fpu_s21}, 6560b57cec5SDimitry Andric nullptr, 6570b57cec5SDimitry Andric nullptr, 6580b57cec5SDimitry Andric nullptr, 6590b57cec5SDimitry Andric 0}, 6600b57cec5SDimitry Andric {"s22", 6610b57cec5SDimitry Andric nullptr, 6620b57cec5SDimitry Andric 4, 6630b57cec5SDimitry Andric FPU_OFFSET(22), 6640b57cec5SDimitry Andric eEncodingIEEE754, 6650b57cec5SDimitry Andric eFormatFloat, 6660b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 6670b57cec5SDimitry Andric fpu_s22}, 6680b57cec5SDimitry Andric nullptr, 6690b57cec5SDimitry Andric nullptr, 6700b57cec5SDimitry Andric nullptr, 6710b57cec5SDimitry Andric 0}, 6720b57cec5SDimitry Andric {"s23", 6730b57cec5SDimitry Andric nullptr, 6740b57cec5SDimitry Andric 4, 6750b57cec5SDimitry Andric FPU_OFFSET(23), 6760b57cec5SDimitry Andric eEncodingIEEE754, 6770b57cec5SDimitry Andric eFormatFloat, 6780b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 6790b57cec5SDimitry Andric fpu_s23}, 6800b57cec5SDimitry Andric nullptr, 6810b57cec5SDimitry Andric nullptr, 6820b57cec5SDimitry Andric nullptr, 6830b57cec5SDimitry Andric 0}, 6840b57cec5SDimitry Andric {"s24", 6850b57cec5SDimitry Andric nullptr, 6860b57cec5SDimitry Andric 4, 6870b57cec5SDimitry Andric FPU_OFFSET(24), 6880b57cec5SDimitry Andric eEncodingIEEE754, 6890b57cec5SDimitry Andric eFormatFloat, 6900b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 6910b57cec5SDimitry Andric fpu_s24}, 6920b57cec5SDimitry Andric nullptr, 6930b57cec5SDimitry Andric nullptr, 6940b57cec5SDimitry Andric nullptr, 6950b57cec5SDimitry Andric 0}, 6960b57cec5SDimitry Andric {"s25", 6970b57cec5SDimitry Andric nullptr, 6980b57cec5SDimitry Andric 4, 6990b57cec5SDimitry Andric FPU_OFFSET(25), 7000b57cec5SDimitry Andric eEncodingIEEE754, 7010b57cec5SDimitry Andric eFormatFloat, 7020b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 7030b57cec5SDimitry Andric fpu_s25}, 7040b57cec5SDimitry Andric nullptr, 7050b57cec5SDimitry Andric nullptr, 7060b57cec5SDimitry Andric nullptr, 7070b57cec5SDimitry Andric 0}, 7080b57cec5SDimitry Andric {"s26", 7090b57cec5SDimitry Andric nullptr, 7100b57cec5SDimitry Andric 4, 7110b57cec5SDimitry Andric FPU_OFFSET(26), 7120b57cec5SDimitry Andric eEncodingIEEE754, 7130b57cec5SDimitry Andric eFormatFloat, 7140b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 7150b57cec5SDimitry Andric fpu_s26}, 7160b57cec5SDimitry Andric nullptr, 7170b57cec5SDimitry Andric nullptr, 7180b57cec5SDimitry Andric nullptr, 7190b57cec5SDimitry Andric 0}, 7200b57cec5SDimitry Andric {"s27", 7210b57cec5SDimitry Andric nullptr, 7220b57cec5SDimitry Andric 4, 7230b57cec5SDimitry Andric FPU_OFFSET(27), 7240b57cec5SDimitry Andric eEncodingIEEE754, 7250b57cec5SDimitry Andric eFormatFloat, 7260b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 7270b57cec5SDimitry Andric fpu_s27}, 7280b57cec5SDimitry Andric nullptr, 7290b57cec5SDimitry Andric nullptr, 7300b57cec5SDimitry Andric nullptr, 7310b57cec5SDimitry Andric 0}, 7320b57cec5SDimitry Andric {"s28", 7330b57cec5SDimitry Andric nullptr, 7340b57cec5SDimitry Andric 4, 7350b57cec5SDimitry Andric FPU_OFFSET(28), 7360b57cec5SDimitry Andric eEncodingIEEE754, 7370b57cec5SDimitry Andric eFormatFloat, 7380b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 7390b57cec5SDimitry Andric fpu_s28}, 7400b57cec5SDimitry Andric nullptr, 7410b57cec5SDimitry Andric nullptr, 7420b57cec5SDimitry Andric nullptr, 7430b57cec5SDimitry Andric 0}, 7440b57cec5SDimitry Andric {"s29", 7450b57cec5SDimitry Andric nullptr, 7460b57cec5SDimitry Andric 4, 7470b57cec5SDimitry Andric FPU_OFFSET(29), 7480b57cec5SDimitry Andric eEncodingIEEE754, 7490b57cec5SDimitry Andric eFormatFloat, 7500b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 7510b57cec5SDimitry Andric fpu_s29}, 7520b57cec5SDimitry Andric nullptr, 7530b57cec5SDimitry Andric nullptr, 7540b57cec5SDimitry Andric nullptr, 7550b57cec5SDimitry Andric 0}, 7560b57cec5SDimitry Andric {"s30", 7570b57cec5SDimitry Andric nullptr, 7580b57cec5SDimitry Andric 4, 7590b57cec5SDimitry Andric FPU_OFFSET(30), 7600b57cec5SDimitry Andric eEncodingIEEE754, 7610b57cec5SDimitry Andric eFormatFloat, 7620b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 7630b57cec5SDimitry Andric fpu_s30}, 7640b57cec5SDimitry Andric nullptr, 7650b57cec5SDimitry Andric nullptr, 7660b57cec5SDimitry Andric nullptr, 7670b57cec5SDimitry Andric 0}, 7680b57cec5SDimitry Andric {"s31", 7690b57cec5SDimitry Andric nullptr, 7700b57cec5SDimitry Andric 4, 7710b57cec5SDimitry Andric FPU_OFFSET(31), 7720b57cec5SDimitry Andric eEncodingIEEE754, 7730b57cec5SDimitry Andric eFormatFloat, 7740b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 7750b57cec5SDimitry Andric fpu_s31}, 7760b57cec5SDimitry Andric nullptr, 7770b57cec5SDimitry Andric nullptr, 7780b57cec5SDimitry Andric nullptr, 7790b57cec5SDimitry Andric 0}, 7800b57cec5SDimitry Andric {"fpscr", 7810b57cec5SDimitry Andric nullptr, 7820b57cec5SDimitry Andric 4, 7830b57cec5SDimitry Andric FPU_OFFSET(32), 7840b57cec5SDimitry Andric eEncodingUint, 7850b57cec5SDimitry Andric eFormatHex, 7860b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 7870b57cec5SDimitry Andric LLDB_INVALID_REGNUM, fpu_fpscr}, 7880b57cec5SDimitry Andric nullptr, 7890b57cec5SDimitry Andric nullptr, 7900b57cec5SDimitry Andric nullptr, 7910b57cec5SDimitry Andric 0}, 7920b57cec5SDimitry Andric 7930b57cec5SDimitry Andric {"exception", 7940b57cec5SDimitry Andric nullptr, 7950b57cec5SDimitry Andric 4, 7960b57cec5SDimitry Andric EXC_OFFSET(0), 7970b57cec5SDimitry Andric eEncodingUint, 7980b57cec5SDimitry Andric eFormatHex, 7990b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 8000b57cec5SDimitry Andric LLDB_INVALID_REGNUM, exc_exception}, 8010b57cec5SDimitry Andric nullptr, 8020b57cec5SDimitry Andric nullptr, 8030b57cec5SDimitry Andric nullptr, 8040b57cec5SDimitry Andric 0}, 8050b57cec5SDimitry Andric {"fsr", 8060b57cec5SDimitry Andric nullptr, 8070b57cec5SDimitry Andric 4, 8080b57cec5SDimitry Andric EXC_OFFSET(1), 8090b57cec5SDimitry Andric eEncodingUint, 8100b57cec5SDimitry Andric eFormatHex, 8110b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 8120b57cec5SDimitry Andric LLDB_INVALID_REGNUM, exc_fsr}, 8130b57cec5SDimitry Andric nullptr, 8140b57cec5SDimitry Andric nullptr, 8150b57cec5SDimitry Andric nullptr, 8160b57cec5SDimitry Andric 0}, 8170b57cec5SDimitry Andric {"far", 8180b57cec5SDimitry Andric nullptr, 8190b57cec5SDimitry Andric 4, 8200b57cec5SDimitry Andric EXC_OFFSET(2), 8210b57cec5SDimitry Andric eEncodingUint, 8220b57cec5SDimitry Andric eFormatHex, 8230b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 8240b57cec5SDimitry Andric LLDB_INVALID_REGNUM, exc_far}, 8250b57cec5SDimitry Andric nullptr, 8260b57cec5SDimitry Andric nullptr, 8270b57cec5SDimitry Andric nullptr, 8280b57cec5SDimitry Andric 0}, 8290b57cec5SDimitry Andric 8300b57cec5SDimitry Andric {DEFINE_DBG(bvr, 0)}, 8310b57cec5SDimitry Andric {DEFINE_DBG(bvr, 1)}, 8320b57cec5SDimitry Andric {DEFINE_DBG(bvr, 2)}, 8330b57cec5SDimitry Andric {DEFINE_DBG(bvr, 3)}, 8340b57cec5SDimitry Andric {DEFINE_DBG(bvr, 4)}, 8350b57cec5SDimitry Andric {DEFINE_DBG(bvr, 5)}, 8360b57cec5SDimitry Andric {DEFINE_DBG(bvr, 6)}, 8370b57cec5SDimitry Andric {DEFINE_DBG(bvr, 7)}, 8380b57cec5SDimitry Andric {DEFINE_DBG(bvr, 8)}, 8390b57cec5SDimitry Andric {DEFINE_DBG(bvr, 9)}, 8400b57cec5SDimitry Andric {DEFINE_DBG(bvr, 10)}, 8410b57cec5SDimitry Andric {DEFINE_DBG(bvr, 11)}, 8420b57cec5SDimitry Andric {DEFINE_DBG(bvr, 12)}, 8430b57cec5SDimitry Andric {DEFINE_DBG(bvr, 13)}, 8440b57cec5SDimitry Andric {DEFINE_DBG(bvr, 14)}, 8450b57cec5SDimitry Andric {DEFINE_DBG(bvr, 15)}, 8460b57cec5SDimitry Andric 8470b57cec5SDimitry Andric {DEFINE_DBG(bcr, 0)}, 8480b57cec5SDimitry Andric {DEFINE_DBG(bcr, 1)}, 8490b57cec5SDimitry Andric {DEFINE_DBG(bcr, 2)}, 8500b57cec5SDimitry Andric {DEFINE_DBG(bcr, 3)}, 8510b57cec5SDimitry Andric {DEFINE_DBG(bcr, 4)}, 8520b57cec5SDimitry Andric {DEFINE_DBG(bcr, 5)}, 8530b57cec5SDimitry Andric {DEFINE_DBG(bcr, 6)}, 8540b57cec5SDimitry Andric {DEFINE_DBG(bcr, 7)}, 8550b57cec5SDimitry Andric {DEFINE_DBG(bcr, 8)}, 8560b57cec5SDimitry Andric {DEFINE_DBG(bcr, 9)}, 8570b57cec5SDimitry Andric {DEFINE_DBG(bcr, 10)}, 8580b57cec5SDimitry Andric {DEFINE_DBG(bcr, 11)}, 8590b57cec5SDimitry Andric {DEFINE_DBG(bcr, 12)}, 8600b57cec5SDimitry Andric {DEFINE_DBG(bcr, 13)}, 8610b57cec5SDimitry Andric {DEFINE_DBG(bcr, 14)}, 8620b57cec5SDimitry Andric {DEFINE_DBG(bcr, 15)}, 8630b57cec5SDimitry Andric 8640b57cec5SDimitry Andric {DEFINE_DBG(wvr, 0)}, 8650b57cec5SDimitry Andric {DEFINE_DBG(wvr, 1)}, 8660b57cec5SDimitry Andric {DEFINE_DBG(wvr, 2)}, 8670b57cec5SDimitry Andric {DEFINE_DBG(wvr, 3)}, 8680b57cec5SDimitry Andric {DEFINE_DBG(wvr, 4)}, 8690b57cec5SDimitry Andric {DEFINE_DBG(wvr, 5)}, 8700b57cec5SDimitry Andric {DEFINE_DBG(wvr, 6)}, 8710b57cec5SDimitry Andric {DEFINE_DBG(wvr, 7)}, 8720b57cec5SDimitry Andric {DEFINE_DBG(wvr, 8)}, 8730b57cec5SDimitry Andric {DEFINE_DBG(wvr, 9)}, 8740b57cec5SDimitry Andric {DEFINE_DBG(wvr, 10)}, 8750b57cec5SDimitry Andric {DEFINE_DBG(wvr, 11)}, 8760b57cec5SDimitry Andric {DEFINE_DBG(wvr, 12)}, 8770b57cec5SDimitry Andric {DEFINE_DBG(wvr, 13)}, 8780b57cec5SDimitry Andric {DEFINE_DBG(wvr, 14)}, 8790b57cec5SDimitry Andric {DEFINE_DBG(wvr, 15)}, 8800b57cec5SDimitry Andric 8810b57cec5SDimitry Andric {DEFINE_DBG(wcr, 0)}, 8820b57cec5SDimitry Andric {DEFINE_DBG(wcr, 1)}, 8830b57cec5SDimitry Andric {DEFINE_DBG(wcr, 2)}, 8840b57cec5SDimitry Andric {DEFINE_DBG(wcr, 3)}, 8850b57cec5SDimitry Andric {DEFINE_DBG(wcr, 4)}, 8860b57cec5SDimitry Andric {DEFINE_DBG(wcr, 5)}, 8870b57cec5SDimitry Andric {DEFINE_DBG(wcr, 6)}, 8880b57cec5SDimitry Andric {DEFINE_DBG(wcr, 7)}, 8890b57cec5SDimitry Andric {DEFINE_DBG(wcr, 8)}, 8900b57cec5SDimitry Andric {DEFINE_DBG(wcr, 9)}, 8910b57cec5SDimitry Andric {DEFINE_DBG(wcr, 10)}, 8920b57cec5SDimitry Andric {DEFINE_DBG(wcr, 11)}, 8930b57cec5SDimitry Andric {DEFINE_DBG(wcr, 12)}, 8940b57cec5SDimitry Andric {DEFINE_DBG(wcr, 13)}, 8950b57cec5SDimitry Andric {DEFINE_DBG(wcr, 14)}, 8960b57cec5SDimitry Andric {DEFINE_DBG(wcr, 15)}}; 8970b57cec5SDimitry Andric 8980b57cec5SDimitry Andric // General purpose registers 8990b57cec5SDimitry Andric static uint32_t g_gpr_regnums[] = { 9000b57cec5SDimitry Andric gpr_r0, gpr_r1, gpr_r2, gpr_r3, gpr_r4, gpr_r5, gpr_r6, gpr_r7, gpr_r8, 9010b57cec5SDimitry Andric gpr_r9, gpr_r10, gpr_r11, gpr_r12, gpr_sp, gpr_lr, gpr_pc, gpr_cpsr}; 9020b57cec5SDimitry Andric 9030b57cec5SDimitry Andric // Floating point registers 9040b57cec5SDimitry Andric static uint32_t g_fpu_regnums[] = { 9050b57cec5SDimitry Andric fpu_s0, fpu_s1, fpu_s2, fpu_s3, fpu_s4, fpu_s5, fpu_s6, 9060b57cec5SDimitry Andric fpu_s7, fpu_s8, fpu_s9, fpu_s10, fpu_s11, fpu_s12, fpu_s13, 9070b57cec5SDimitry Andric fpu_s14, fpu_s15, fpu_s16, fpu_s17, fpu_s18, fpu_s19, fpu_s20, 9080b57cec5SDimitry Andric fpu_s21, fpu_s22, fpu_s23, fpu_s24, fpu_s25, fpu_s26, fpu_s27, 9090b57cec5SDimitry Andric fpu_s28, fpu_s29, fpu_s30, fpu_s31, fpu_fpscr, 9100b57cec5SDimitry Andric }; 9110b57cec5SDimitry Andric 9120b57cec5SDimitry Andric // Exception registers 9130b57cec5SDimitry Andric 9140b57cec5SDimitry Andric static uint32_t g_exc_regnums[] = { 9150b57cec5SDimitry Andric exc_exception, exc_fsr, exc_far, 9160b57cec5SDimitry Andric }; 9170b57cec5SDimitry Andric 9180b57cec5SDimitry Andric static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos); 9190b57cec5SDimitry Andric 9200b57cec5SDimitry Andric RegisterContextDarwin_arm::RegisterContextDarwin_arm( 9210b57cec5SDimitry Andric Thread &thread, uint32_t concrete_frame_idx) 9220b57cec5SDimitry Andric : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() { 9230b57cec5SDimitry Andric uint32_t i; 9240b57cec5SDimitry Andric for (i = 0; i < kNumErrors; i++) { 9250b57cec5SDimitry Andric gpr_errs[i] = -1; 9260b57cec5SDimitry Andric fpu_errs[i] = -1; 9270b57cec5SDimitry Andric exc_errs[i] = -1; 9280b57cec5SDimitry Andric } 9290b57cec5SDimitry Andric } 9300b57cec5SDimitry Andric 9310b57cec5SDimitry Andric RegisterContextDarwin_arm::~RegisterContextDarwin_arm() {} 9320b57cec5SDimitry Andric 9330b57cec5SDimitry Andric void RegisterContextDarwin_arm::InvalidateAllRegisters() { 9340b57cec5SDimitry Andric InvalidateAllRegisterStates(); 9350b57cec5SDimitry Andric } 9360b57cec5SDimitry Andric 9370b57cec5SDimitry Andric size_t RegisterContextDarwin_arm::GetRegisterCount() { 9380b57cec5SDimitry Andric assert(k_num_register_infos == k_num_registers); 9390b57cec5SDimitry Andric return k_num_registers; 9400b57cec5SDimitry Andric } 9410b57cec5SDimitry Andric 9420b57cec5SDimitry Andric const RegisterInfo * 9430b57cec5SDimitry Andric RegisterContextDarwin_arm::GetRegisterInfoAtIndex(size_t reg) { 9440b57cec5SDimitry Andric assert(k_num_register_infos == k_num_registers); 9450b57cec5SDimitry Andric if (reg < k_num_registers) 9460b57cec5SDimitry Andric return &g_register_infos[reg]; 9470b57cec5SDimitry Andric return nullptr; 9480b57cec5SDimitry Andric } 9490b57cec5SDimitry Andric 9500b57cec5SDimitry Andric size_t RegisterContextDarwin_arm::GetRegisterInfosCount() { 9510b57cec5SDimitry Andric return k_num_register_infos; 9520b57cec5SDimitry Andric } 9530b57cec5SDimitry Andric 9540b57cec5SDimitry Andric const RegisterInfo *RegisterContextDarwin_arm::GetRegisterInfos() { 9550b57cec5SDimitry Andric return g_register_infos; 9560b57cec5SDimitry Andric } 9570b57cec5SDimitry Andric 9580b57cec5SDimitry Andric // Number of registers in each register set 9590b57cec5SDimitry Andric const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums); 9600b57cec5SDimitry Andric const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums); 9610b57cec5SDimitry Andric const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums); 9620b57cec5SDimitry Andric 9630b57cec5SDimitry Andric // Register set definitions. The first definitions at register set index of 9640b57cec5SDimitry Andric // zero is for all registers, followed by other registers sets. The register 9650b57cec5SDimitry Andric // information for the all register set need not be filled in. 9660b57cec5SDimitry Andric static const RegisterSet g_reg_sets[] = { 9670b57cec5SDimitry Andric { 9680b57cec5SDimitry Andric "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, 9690b57cec5SDimitry Andric }, 9700b57cec5SDimitry Andric {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums}, 9710b57cec5SDimitry Andric {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}}; 9720b57cec5SDimitry Andric 9730b57cec5SDimitry Andric const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets); 9740b57cec5SDimitry Andric 9750b57cec5SDimitry Andric size_t RegisterContextDarwin_arm::GetRegisterSetCount() { 9760b57cec5SDimitry Andric return k_num_regsets; 9770b57cec5SDimitry Andric } 9780b57cec5SDimitry Andric 9790b57cec5SDimitry Andric const RegisterSet *RegisterContextDarwin_arm::GetRegisterSet(size_t reg_set) { 9800b57cec5SDimitry Andric if (reg_set < k_num_regsets) 9810b57cec5SDimitry Andric return &g_reg_sets[reg_set]; 9820b57cec5SDimitry Andric return nullptr; 9830b57cec5SDimitry Andric } 9840b57cec5SDimitry Andric 9850b57cec5SDimitry Andric // Register information definitions for 32 bit i386. 9860b57cec5SDimitry Andric int RegisterContextDarwin_arm::GetSetForNativeRegNum(int reg) { 9870b57cec5SDimitry Andric if (reg < fpu_s0) 9880b57cec5SDimitry Andric return GPRRegSet; 9890b57cec5SDimitry Andric else if (reg < exc_exception) 9900b57cec5SDimitry Andric return FPURegSet; 9910b57cec5SDimitry Andric else if (reg < k_num_registers) 9920b57cec5SDimitry Andric return EXCRegSet; 9930b57cec5SDimitry Andric return -1; 9940b57cec5SDimitry Andric } 9950b57cec5SDimitry Andric 9960b57cec5SDimitry Andric int RegisterContextDarwin_arm::ReadGPR(bool force) { 9970b57cec5SDimitry Andric int set = GPRRegSet; 9980b57cec5SDimitry Andric if (force || !RegisterSetIsCached(set)) { 9990b57cec5SDimitry Andric SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr)); 10000b57cec5SDimitry Andric } 10010b57cec5SDimitry Andric return GetError(GPRRegSet, Read); 10020b57cec5SDimitry Andric } 10030b57cec5SDimitry Andric 10040b57cec5SDimitry Andric int RegisterContextDarwin_arm::ReadFPU(bool force) { 10050b57cec5SDimitry Andric int set = FPURegSet; 10060b57cec5SDimitry Andric if (force || !RegisterSetIsCached(set)) { 10070b57cec5SDimitry Andric SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu)); 10080b57cec5SDimitry Andric } 10090b57cec5SDimitry Andric return GetError(FPURegSet, Read); 10100b57cec5SDimitry Andric } 10110b57cec5SDimitry Andric 10120b57cec5SDimitry Andric int RegisterContextDarwin_arm::ReadEXC(bool force) { 10130b57cec5SDimitry Andric int set = EXCRegSet; 10140b57cec5SDimitry Andric if (force || !RegisterSetIsCached(set)) { 10150b57cec5SDimitry Andric SetError(set, Read, DoReadEXC(GetThreadID(), set, exc)); 10160b57cec5SDimitry Andric } 10170b57cec5SDimitry Andric return GetError(EXCRegSet, Read); 10180b57cec5SDimitry Andric } 10190b57cec5SDimitry Andric 10200b57cec5SDimitry Andric int RegisterContextDarwin_arm::ReadDBG(bool force) { 10210b57cec5SDimitry Andric int set = DBGRegSet; 10220b57cec5SDimitry Andric if (force || !RegisterSetIsCached(set)) { 10230b57cec5SDimitry Andric SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg)); 10240b57cec5SDimitry Andric } 10250b57cec5SDimitry Andric return GetError(DBGRegSet, Read); 10260b57cec5SDimitry Andric } 10270b57cec5SDimitry Andric 10280b57cec5SDimitry Andric int RegisterContextDarwin_arm::WriteGPR() { 10290b57cec5SDimitry Andric int set = GPRRegSet; 10300b57cec5SDimitry Andric if (!RegisterSetIsCached(set)) { 10310b57cec5SDimitry Andric SetError(set, Write, -1); 10320b57cec5SDimitry Andric return KERN_INVALID_ARGUMENT; 10330b57cec5SDimitry Andric } 10340b57cec5SDimitry Andric SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr)); 10350b57cec5SDimitry Andric SetError(set, Read, -1); 10360b57cec5SDimitry Andric return GetError(GPRRegSet, Write); 10370b57cec5SDimitry Andric } 10380b57cec5SDimitry Andric 10390b57cec5SDimitry Andric int RegisterContextDarwin_arm::WriteFPU() { 10400b57cec5SDimitry Andric int set = FPURegSet; 10410b57cec5SDimitry Andric if (!RegisterSetIsCached(set)) { 10420b57cec5SDimitry Andric SetError(set, Write, -1); 10430b57cec5SDimitry Andric return KERN_INVALID_ARGUMENT; 10440b57cec5SDimitry Andric } 10450b57cec5SDimitry Andric SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu)); 10460b57cec5SDimitry Andric SetError(set, Read, -1); 10470b57cec5SDimitry Andric return GetError(FPURegSet, Write); 10480b57cec5SDimitry Andric } 10490b57cec5SDimitry Andric 10500b57cec5SDimitry Andric int RegisterContextDarwin_arm::WriteEXC() { 10510b57cec5SDimitry Andric int set = EXCRegSet; 10520b57cec5SDimitry Andric if (!RegisterSetIsCached(set)) { 10530b57cec5SDimitry Andric SetError(set, Write, -1); 10540b57cec5SDimitry Andric return KERN_INVALID_ARGUMENT; 10550b57cec5SDimitry Andric } 10560b57cec5SDimitry Andric SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc)); 10570b57cec5SDimitry Andric SetError(set, Read, -1); 10580b57cec5SDimitry Andric return GetError(EXCRegSet, Write); 10590b57cec5SDimitry Andric } 10600b57cec5SDimitry Andric 10610b57cec5SDimitry Andric int RegisterContextDarwin_arm::WriteDBG() { 10620b57cec5SDimitry Andric int set = DBGRegSet; 10630b57cec5SDimitry Andric if (!RegisterSetIsCached(set)) { 10640b57cec5SDimitry Andric SetError(set, Write, -1); 10650b57cec5SDimitry Andric return KERN_INVALID_ARGUMENT; 10660b57cec5SDimitry Andric } 10670b57cec5SDimitry Andric SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg)); 10680b57cec5SDimitry Andric SetError(set, Read, -1); 10690b57cec5SDimitry Andric return GetError(DBGRegSet, Write); 10700b57cec5SDimitry Andric } 10710b57cec5SDimitry Andric 10720b57cec5SDimitry Andric int RegisterContextDarwin_arm::ReadRegisterSet(uint32_t set, bool force) { 10730b57cec5SDimitry Andric switch (set) { 10740b57cec5SDimitry Andric case GPRRegSet: 10750b57cec5SDimitry Andric return ReadGPR(force); 10760b57cec5SDimitry Andric case GPRAltRegSet: 10770b57cec5SDimitry Andric return ReadGPR(force); 10780b57cec5SDimitry Andric case FPURegSet: 10790b57cec5SDimitry Andric return ReadFPU(force); 10800b57cec5SDimitry Andric case EXCRegSet: 10810b57cec5SDimitry Andric return ReadEXC(force); 10820b57cec5SDimitry Andric case DBGRegSet: 10830b57cec5SDimitry Andric return ReadDBG(force); 10840b57cec5SDimitry Andric default: 10850b57cec5SDimitry Andric break; 10860b57cec5SDimitry Andric } 10870b57cec5SDimitry Andric return KERN_INVALID_ARGUMENT; 10880b57cec5SDimitry Andric } 10890b57cec5SDimitry Andric 10900b57cec5SDimitry Andric int RegisterContextDarwin_arm::WriteRegisterSet(uint32_t set) { 10910b57cec5SDimitry Andric // Make sure we have a valid context to set. 10920b57cec5SDimitry Andric if (RegisterSetIsCached(set)) { 10930b57cec5SDimitry Andric switch (set) { 10940b57cec5SDimitry Andric case GPRRegSet: 10950b57cec5SDimitry Andric return WriteGPR(); 10960b57cec5SDimitry Andric case GPRAltRegSet: 10970b57cec5SDimitry Andric return WriteGPR(); 10980b57cec5SDimitry Andric case FPURegSet: 10990b57cec5SDimitry Andric return WriteFPU(); 11000b57cec5SDimitry Andric case EXCRegSet: 11010b57cec5SDimitry Andric return WriteEXC(); 11020b57cec5SDimitry Andric case DBGRegSet: 11030b57cec5SDimitry Andric return WriteDBG(); 11040b57cec5SDimitry Andric default: 11050b57cec5SDimitry Andric break; 11060b57cec5SDimitry Andric } 11070b57cec5SDimitry Andric } 11080b57cec5SDimitry Andric return KERN_INVALID_ARGUMENT; 11090b57cec5SDimitry Andric } 11100b57cec5SDimitry Andric 11110b57cec5SDimitry Andric void RegisterContextDarwin_arm::LogDBGRegisters(Log *log, const DBG &dbg) { 11120b57cec5SDimitry Andric if (log) { 11130b57cec5SDimitry Andric for (uint32_t i = 0; i < 16; i++) 11149dba64beSDimitry Andric LLDB_LOGF(log, 11159dba64beSDimitry Andric "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { " 11160b57cec5SDimitry Andric "0x%8.8x, 0x%8.8x }", 11170b57cec5SDimitry Andric i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]); 11180b57cec5SDimitry Andric } 11190b57cec5SDimitry Andric } 11200b57cec5SDimitry Andric 11210b57cec5SDimitry Andric bool RegisterContextDarwin_arm::ReadRegister(const RegisterInfo *reg_info, 11220b57cec5SDimitry Andric RegisterValue &value) { 11230b57cec5SDimitry Andric const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 11240b57cec5SDimitry Andric int set = RegisterContextDarwin_arm::GetSetForNativeRegNum(reg); 11250b57cec5SDimitry Andric 11260b57cec5SDimitry Andric if (set == -1) 11270b57cec5SDimitry Andric return false; 11280b57cec5SDimitry Andric 11290b57cec5SDimitry Andric if (ReadRegisterSet(set, false) != KERN_SUCCESS) 11300b57cec5SDimitry Andric return false; 11310b57cec5SDimitry Andric 11320b57cec5SDimitry Andric switch (reg) { 11330b57cec5SDimitry Andric case gpr_r0: 11340b57cec5SDimitry Andric case gpr_r1: 11350b57cec5SDimitry Andric case gpr_r2: 11360b57cec5SDimitry Andric case gpr_r3: 11370b57cec5SDimitry Andric case gpr_r4: 11380b57cec5SDimitry Andric case gpr_r5: 11390b57cec5SDimitry Andric case gpr_r6: 11400b57cec5SDimitry Andric case gpr_r7: 11410b57cec5SDimitry Andric case gpr_r8: 11420b57cec5SDimitry Andric case gpr_r9: 11430b57cec5SDimitry Andric case gpr_r10: 11440b57cec5SDimitry Andric case gpr_r11: 11450b57cec5SDimitry Andric case gpr_r12: 11460b57cec5SDimitry Andric case gpr_sp: 11470b57cec5SDimitry Andric case gpr_lr: 11480b57cec5SDimitry Andric case gpr_pc: 11490b57cec5SDimitry Andric case gpr_cpsr: 11500b57cec5SDimitry Andric value.SetUInt32(gpr.r[reg - gpr_r0]); 11510b57cec5SDimitry Andric break; 11520b57cec5SDimitry Andric 11530b57cec5SDimitry Andric case fpu_s0: 11540b57cec5SDimitry Andric case fpu_s1: 11550b57cec5SDimitry Andric case fpu_s2: 11560b57cec5SDimitry Andric case fpu_s3: 11570b57cec5SDimitry Andric case fpu_s4: 11580b57cec5SDimitry Andric case fpu_s5: 11590b57cec5SDimitry Andric case fpu_s6: 11600b57cec5SDimitry Andric case fpu_s7: 11610b57cec5SDimitry Andric case fpu_s8: 11620b57cec5SDimitry Andric case fpu_s9: 11630b57cec5SDimitry Andric case fpu_s10: 11640b57cec5SDimitry Andric case fpu_s11: 11650b57cec5SDimitry Andric case fpu_s12: 11660b57cec5SDimitry Andric case fpu_s13: 11670b57cec5SDimitry Andric case fpu_s14: 11680b57cec5SDimitry Andric case fpu_s15: 11690b57cec5SDimitry Andric case fpu_s16: 11700b57cec5SDimitry Andric case fpu_s17: 11710b57cec5SDimitry Andric case fpu_s18: 11720b57cec5SDimitry Andric case fpu_s19: 11730b57cec5SDimitry Andric case fpu_s20: 11740b57cec5SDimitry Andric case fpu_s21: 11750b57cec5SDimitry Andric case fpu_s22: 11760b57cec5SDimitry Andric case fpu_s23: 11770b57cec5SDimitry Andric case fpu_s24: 11780b57cec5SDimitry Andric case fpu_s25: 11790b57cec5SDimitry Andric case fpu_s26: 11800b57cec5SDimitry Andric case fpu_s27: 11810b57cec5SDimitry Andric case fpu_s28: 11820b57cec5SDimitry Andric case fpu_s29: 11830b57cec5SDimitry Andric case fpu_s30: 11840b57cec5SDimitry Andric case fpu_s31: 11850b57cec5SDimitry Andric value.SetUInt32(fpu.floats.s[reg], RegisterValue::eTypeFloat); 11860b57cec5SDimitry Andric break; 11870b57cec5SDimitry Andric 11880b57cec5SDimitry Andric case fpu_fpscr: 11890b57cec5SDimitry Andric value.SetUInt32(fpu.fpscr); 11900b57cec5SDimitry Andric break; 11910b57cec5SDimitry Andric 11920b57cec5SDimitry Andric case exc_exception: 11930b57cec5SDimitry Andric value.SetUInt32(exc.exception); 11940b57cec5SDimitry Andric break; 11950b57cec5SDimitry Andric case exc_fsr: 11960b57cec5SDimitry Andric value.SetUInt32(exc.fsr); 11970b57cec5SDimitry Andric break; 11980b57cec5SDimitry Andric case exc_far: 11990b57cec5SDimitry Andric value.SetUInt32(exc.far); 12000b57cec5SDimitry Andric break; 12010b57cec5SDimitry Andric 12020b57cec5SDimitry Andric default: 12030b57cec5SDimitry Andric value.SetValueToInvalid(); 12040b57cec5SDimitry Andric return false; 12050b57cec5SDimitry Andric } 12060b57cec5SDimitry Andric return true; 12070b57cec5SDimitry Andric } 12080b57cec5SDimitry Andric 12090b57cec5SDimitry Andric bool RegisterContextDarwin_arm::WriteRegister(const RegisterInfo *reg_info, 12100b57cec5SDimitry Andric const RegisterValue &value) { 12110b57cec5SDimitry Andric const uint32_t reg = reg_info->kinds[eRegisterKindLLDB]; 12120b57cec5SDimitry Andric int set = GetSetForNativeRegNum(reg); 12130b57cec5SDimitry Andric 12140b57cec5SDimitry Andric if (set == -1) 12150b57cec5SDimitry Andric return false; 12160b57cec5SDimitry Andric 12170b57cec5SDimitry Andric if (ReadRegisterSet(set, false) != KERN_SUCCESS) 12180b57cec5SDimitry Andric return false; 12190b57cec5SDimitry Andric 12200b57cec5SDimitry Andric switch (reg) { 12210b57cec5SDimitry Andric case gpr_r0: 12220b57cec5SDimitry Andric case gpr_r1: 12230b57cec5SDimitry Andric case gpr_r2: 12240b57cec5SDimitry Andric case gpr_r3: 12250b57cec5SDimitry Andric case gpr_r4: 12260b57cec5SDimitry Andric case gpr_r5: 12270b57cec5SDimitry Andric case gpr_r6: 12280b57cec5SDimitry Andric case gpr_r7: 12290b57cec5SDimitry Andric case gpr_r8: 12300b57cec5SDimitry Andric case gpr_r9: 12310b57cec5SDimitry Andric case gpr_r10: 12320b57cec5SDimitry Andric case gpr_r11: 12330b57cec5SDimitry Andric case gpr_r12: 12340b57cec5SDimitry Andric case gpr_sp: 12350b57cec5SDimitry Andric case gpr_lr: 12360b57cec5SDimitry Andric case gpr_pc: 12370b57cec5SDimitry Andric case gpr_cpsr: 12380b57cec5SDimitry Andric gpr.r[reg - gpr_r0] = value.GetAsUInt32(); 12390b57cec5SDimitry Andric break; 12400b57cec5SDimitry Andric 12410b57cec5SDimitry Andric case fpu_s0: 12420b57cec5SDimitry Andric case fpu_s1: 12430b57cec5SDimitry Andric case fpu_s2: 12440b57cec5SDimitry Andric case fpu_s3: 12450b57cec5SDimitry Andric case fpu_s4: 12460b57cec5SDimitry Andric case fpu_s5: 12470b57cec5SDimitry Andric case fpu_s6: 12480b57cec5SDimitry Andric case fpu_s7: 12490b57cec5SDimitry Andric case fpu_s8: 12500b57cec5SDimitry Andric case fpu_s9: 12510b57cec5SDimitry Andric case fpu_s10: 12520b57cec5SDimitry Andric case fpu_s11: 12530b57cec5SDimitry Andric case fpu_s12: 12540b57cec5SDimitry Andric case fpu_s13: 12550b57cec5SDimitry Andric case fpu_s14: 12560b57cec5SDimitry Andric case fpu_s15: 12570b57cec5SDimitry Andric case fpu_s16: 12580b57cec5SDimitry Andric case fpu_s17: 12590b57cec5SDimitry Andric case fpu_s18: 12600b57cec5SDimitry Andric case fpu_s19: 12610b57cec5SDimitry Andric case fpu_s20: 12620b57cec5SDimitry Andric case fpu_s21: 12630b57cec5SDimitry Andric case fpu_s22: 12640b57cec5SDimitry Andric case fpu_s23: 12650b57cec5SDimitry Andric case fpu_s24: 12660b57cec5SDimitry Andric case fpu_s25: 12670b57cec5SDimitry Andric case fpu_s26: 12680b57cec5SDimitry Andric case fpu_s27: 12690b57cec5SDimitry Andric case fpu_s28: 12700b57cec5SDimitry Andric case fpu_s29: 12710b57cec5SDimitry Andric case fpu_s30: 12720b57cec5SDimitry Andric case fpu_s31: 12730b57cec5SDimitry Andric fpu.floats.s[reg] = value.GetAsUInt32(); 12740b57cec5SDimitry Andric break; 12750b57cec5SDimitry Andric 12760b57cec5SDimitry Andric case fpu_fpscr: 12770b57cec5SDimitry Andric fpu.fpscr = value.GetAsUInt32(); 12780b57cec5SDimitry Andric break; 12790b57cec5SDimitry Andric 12800b57cec5SDimitry Andric case exc_exception: 12810b57cec5SDimitry Andric exc.exception = value.GetAsUInt32(); 12820b57cec5SDimitry Andric break; 12830b57cec5SDimitry Andric case exc_fsr: 12840b57cec5SDimitry Andric exc.fsr = value.GetAsUInt32(); 12850b57cec5SDimitry Andric break; 12860b57cec5SDimitry Andric case exc_far: 12870b57cec5SDimitry Andric exc.far = value.GetAsUInt32(); 12880b57cec5SDimitry Andric break; 12890b57cec5SDimitry Andric 12900b57cec5SDimitry Andric default: 12910b57cec5SDimitry Andric return false; 12920b57cec5SDimitry Andric } 12930b57cec5SDimitry Andric return WriteRegisterSet(set) == KERN_SUCCESS; 12940b57cec5SDimitry Andric } 12950b57cec5SDimitry Andric 12960b57cec5SDimitry Andric bool RegisterContextDarwin_arm::ReadAllRegisterValues( 12970b57cec5SDimitry Andric lldb::DataBufferSP &data_sp) { 12980b57cec5SDimitry Andric data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0); 12990b57cec5SDimitry Andric if (data_sp && ReadGPR(false) == KERN_SUCCESS && 13000b57cec5SDimitry Andric ReadFPU(false) == KERN_SUCCESS && ReadEXC(false) == KERN_SUCCESS) { 13010b57cec5SDimitry Andric uint8_t *dst = data_sp->GetBytes(); 13020b57cec5SDimitry Andric ::memcpy(dst, &gpr, sizeof(gpr)); 13030b57cec5SDimitry Andric dst += sizeof(gpr); 13040b57cec5SDimitry Andric 13050b57cec5SDimitry Andric ::memcpy(dst, &fpu, sizeof(fpu)); 13060b57cec5SDimitry Andric dst += sizeof(gpr); 13070b57cec5SDimitry Andric 13080b57cec5SDimitry Andric ::memcpy(dst, &exc, sizeof(exc)); 13090b57cec5SDimitry Andric return true; 13100b57cec5SDimitry Andric } 13110b57cec5SDimitry Andric return false; 13120b57cec5SDimitry Andric } 13130b57cec5SDimitry Andric 13140b57cec5SDimitry Andric bool RegisterContextDarwin_arm::WriteAllRegisterValues( 13150b57cec5SDimitry Andric const lldb::DataBufferSP &data_sp) { 13160b57cec5SDimitry Andric if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) { 13170b57cec5SDimitry Andric const uint8_t *src = data_sp->GetBytes(); 13180b57cec5SDimitry Andric ::memcpy(&gpr, src, sizeof(gpr)); 13190b57cec5SDimitry Andric src += sizeof(gpr); 13200b57cec5SDimitry Andric 13210b57cec5SDimitry Andric ::memcpy(&fpu, src, sizeof(fpu)); 13220b57cec5SDimitry Andric src += sizeof(gpr); 13230b57cec5SDimitry Andric 13240b57cec5SDimitry Andric ::memcpy(&exc, src, sizeof(exc)); 13250b57cec5SDimitry Andric uint32_t success_count = 0; 13260b57cec5SDimitry Andric if (WriteGPR() == KERN_SUCCESS) 13270b57cec5SDimitry Andric ++success_count; 13280b57cec5SDimitry Andric if (WriteFPU() == KERN_SUCCESS) 13290b57cec5SDimitry Andric ++success_count; 13300b57cec5SDimitry Andric if (WriteEXC() == KERN_SUCCESS) 13310b57cec5SDimitry Andric ++success_count; 13320b57cec5SDimitry Andric return success_count == 3; 13330b57cec5SDimitry Andric } 13340b57cec5SDimitry Andric return false; 13350b57cec5SDimitry Andric } 13360b57cec5SDimitry Andric 13370b57cec5SDimitry Andric uint32_t RegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber( 13380b57cec5SDimitry Andric lldb::RegisterKind kind, uint32_t reg) { 13390b57cec5SDimitry Andric if (kind == eRegisterKindGeneric) { 13400b57cec5SDimitry Andric switch (reg) { 13410b57cec5SDimitry Andric case LLDB_REGNUM_GENERIC_PC: 13420b57cec5SDimitry Andric return gpr_pc; 13430b57cec5SDimitry Andric case LLDB_REGNUM_GENERIC_SP: 13440b57cec5SDimitry Andric return gpr_sp; 13450b57cec5SDimitry Andric case LLDB_REGNUM_GENERIC_FP: 13460b57cec5SDimitry Andric return gpr_r7; 13470b57cec5SDimitry Andric case LLDB_REGNUM_GENERIC_RA: 13480b57cec5SDimitry Andric return gpr_lr; 13490b57cec5SDimitry Andric case LLDB_REGNUM_GENERIC_FLAGS: 13500b57cec5SDimitry Andric return gpr_cpsr; 13510b57cec5SDimitry Andric default: 13520b57cec5SDimitry Andric break; 13530b57cec5SDimitry Andric } 13540b57cec5SDimitry Andric } else if (kind == eRegisterKindDWARF) { 13550b57cec5SDimitry Andric switch (reg) { 13560b57cec5SDimitry Andric case dwarf_r0: 13570b57cec5SDimitry Andric return gpr_r0; 13580b57cec5SDimitry Andric case dwarf_r1: 13590b57cec5SDimitry Andric return gpr_r1; 13600b57cec5SDimitry Andric case dwarf_r2: 13610b57cec5SDimitry Andric return gpr_r2; 13620b57cec5SDimitry Andric case dwarf_r3: 13630b57cec5SDimitry Andric return gpr_r3; 13640b57cec5SDimitry Andric case dwarf_r4: 13650b57cec5SDimitry Andric return gpr_r4; 13660b57cec5SDimitry Andric case dwarf_r5: 13670b57cec5SDimitry Andric return gpr_r5; 13680b57cec5SDimitry Andric case dwarf_r6: 13690b57cec5SDimitry Andric return gpr_r6; 13700b57cec5SDimitry Andric case dwarf_r7: 13710b57cec5SDimitry Andric return gpr_r7; 13720b57cec5SDimitry Andric case dwarf_r8: 13730b57cec5SDimitry Andric return gpr_r8; 13740b57cec5SDimitry Andric case dwarf_r9: 13750b57cec5SDimitry Andric return gpr_r9; 13760b57cec5SDimitry Andric case dwarf_r10: 13770b57cec5SDimitry Andric return gpr_r10; 13780b57cec5SDimitry Andric case dwarf_r11: 13790b57cec5SDimitry Andric return gpr_r11; 13800b57cec5SDimitry Andric case dwarf_r12: 13810b57cec5SDimitry Andric return gpr_r12; 13820b57cec5SDimitry Andric case dwarf_sp: 13830b57cec5SDimitry Andric return gpr_sp; 13840b57cec5SDimitry Andric case dwarf_lr: 13850b57cec5SDimitry Andric return gpr_lr; 13860b57cec5SDimitry Andric case dwarf_pc: 13870b57cec5SDimitry Andric return gpr_pc; 13880b57cec5SDimitry Andric case dwarf_spsr: 13890b57cec5SDimitry Andric return gpr_cpsr; 13900b57cec5SDimitry Andric 13910b57cec5SDimitry Andric case dwarf_s0: 13920b57cec5SDimitry Andric return fpu_s0; 13930b57cec5SDimitry Andric case dwarf_s1: 13940b57cec5SDimitry Andric return fpu_s1; 13950b57cec5SDimitry Andric case dwarf_s2: 13960b57cec5SDimitry Andric return fpu_s2; 13970b57cec5SDimitry Andric case dwarf_s3: 13980b57cec5SDimitry Andric return fpu_s3; 13990b57cec5SDimitry Andric case dwarf_s4: 14000b57cec5SDimitry Andric return fpu_s4; 14010b57cec5SDimitry Andric case dwarf_s5: 14020b57cec5SDimitry Andric return fpu_s5; 14030b57cec5SDimitry Andric case dwarf_s6: 14040b57cec5SDimitry Andric return fpu_s6; 14050b57cec5SDimitry Andric case dwarf_s7: 14060b57cec5SDimitry Andric return fpu_s7; 14070b57cec5SDimitry Andric case dwarf_s8: 14080b57cec5SDimitry Andric return fpu_s8; 14090b57cec5SDimitry Andric case dwarf_s9: 14100b57cec5SDimitry Andric return fpu_s9; 14110b57cec5SDimitry Andric case dwarf_s10: 14120b57cec5SDimitry Andric return fpu_s10; 14130b57cec5SDimitry Andric case dwarf_s11: 14140b57cec5SDimitry Andric return fpu_s11; 14150b57cec5SDimitry Andric case dwarf_s12: 14160b57cec5SDimitry Andric return fpu_s12; 14170b57cec5SDimitry Andric case dwarf_s13: 14180b57cec5SDimitry Andric return fpu_s13; 14190b57cec5SDimitry Andric case dwarf_s14: 14200b57cec5SDimitry Andric return fpu_s14; 14210b57cec5SDimitry Andric case dwarf_s15: 14220b57cec5SDimitry Andric return fpu_s15; 14230b57cec5SDimitry Andric case dwarf_s16: 14240b57cec5SDimitry Andric return fpu_s16; 14250b57cec5SDimitry Andric case dwarf_s17: 14260b57cec5SDimitry Andric return fpu_s17; 14270b57cec5SDimitry Andric case dwarf_s18: 14280b57cec5SDimitry Andric return fpu_s18; 14290b57cec5SDimitry Andric case dwarf_s19: 14300b57cec5SDimitry Andric return fpu_s19; 14310b57cec5SDimitry Andric case dwarf_s20: 14320b57cec5SDimitry Andric return fpu_s20; 14330b57cec5SDimitry Andric case dwarf_s21: 14340b57cec5SDimitry Andric return fpu_s21; 14350b57cec5SDimitry Andric case dwarf_s22: 14360b57cec5SDimitry Andric return fpu_s22; 14370b57cec5SDimitry Andric case dwarf_s23: 14380b57cec5SDimitry Andric return fpu_s23; 14390b57cec5SDimitry Andric case dwarf_s24: 14400b57cec5SDimitry Andric return fpu_s24; 14410b57cec5SDimitry Andric case dwarf_s25: 14420b57cec5SDimitry Andric return fpu_s25; 14430b57cec5SDimitry Andric case dwarf_s26: 14440b57cec5SDimitry Andric return fpu_s26; 14450b57cec5SDimitry Andric case dwarf_s27: 14460b57cec5SDimitry Andric return fpu_s27; 14470b57cec5SDimitry Andric case dwarf_s28: 14480b57cec5SDimitry Andric return fpu_s28; 14490b57cec5SDimitry Andric case dwarf_s29: 14500b57cec5SDimitry Andric return fpu_s29; 14510b57cec5SDimitry Andric case dwarf_s30: 14520b57cec5SDimitry Andric return fpu_s30; 14530b57cec5SDimitry Andric case dwarf_s31: 14540b57cec5SDimitry Andric return fpu_s31; 14550b57cec5SDimitry Andric 14560b57cec5SDimitry Andric default: 14570b57cec5SDimitry Andric break; 14580b57cec5SDimitry Andric } 14590b57cec5SDimitry Andric } else if (kind == eRegisterKindEHFrame) { 14600b57cec5SDimitry Andric switch (reg) { 14610b57cec5SDimitry Andric case ehframe_r0: 14620b57cec5SDimitry Andric return gpr_r0; 14630b57cec5SDimitry Andric case ehframe_r1: 14640b57cec5SDimitry Andric return gpr_r1; 14650b57cec5SDimitry Andric case ehframe_r2: 14660b57cec5SDimitry Andric return gpr_r2; 14670b57cec5SDimitry Andric case ehframe_r3: 14680b57cec5SDimitry Andric return gpr_r3; 14690b57cec5SDimitry Andric case ehframe_r4: 14700b57cec5SDimitry Andric return gpr_r4; 14710b57cec5SDimitry Andric case ehframe_r5: 14720b57cec5SDimitry Andric return gpr_r5; 14730b57cec5SDimitry Andric case ehframe_r6: 14740b57cec5SDimitry Andric return gpr_r6; 14750b57cec5SDimitry Andric case ehframe_r7: 14760b57cec5SDimitry Andric return gpr_r7; 14770b57cec5SDimitry Andric case ehframe_r8: 14780b57cec5SDimitry Andric return gpr_r8; 14790b57cec5SDimitry Andric case ehframe_r9: 14800b57cec5SDimitry Andric return gpr_r9; 14810b57cec5SDimitry Andric case ehframe_r10: 14820b57cec5SDimitry Andric return gpr_r10; 14830b57cec5SDimitry Andric case ehframe_r11: 14840b57cec5SDimitry Andric return gpr_r11; 14850b57cec5SDimitry Andric case ehframe_r12: 14860b57cec5SDimitry Andric return gpr_r12; 14870b57cec5SDimitry Andric case ehframe_sp: 14880b57cec5SDimitry Andric return gpr_sp; 14890b57cec5SDimitry Andric case ehframe_lr: 14900b57cec5SDimitry Andric return gpr_lr; 14910b57cec5SDimitry Andric case ehframe_pc: 14920b57cec5SDimitry Andric return gpr_pc; 14930b57cec5SDimitry Andric case ehframe_cpsr: 14940b57cec5SDimitry Andric return gpr_cpsr; 14950b57cec5SDimitry Andric } 14960b57cec5SDimitry Andric } else if (kind == eRegisterKindLLDB) { 14970b57cec5SDimitry Andric return reg; 14980b57cec5SDimitry Andric } 14990b57cec5SDimitry Andric return LLDB_INVALID_REGNUM; 15000b57cec5SDimitry Andric } 15010b57cec5SDimitry Andric 15020b57cec5SDimitry Andric uint32_t RegisterContextDarwin_arm::NumSupportedHardwareBreakpoints() { 15030b57cec5SDimitry Andric #if defined(__APPLE__) && defined(__arm__) 15040b57cec5SDimitry Andric // Set the init value to something that will let us know that we need to 15050b57cec5SDimitry Andric // autodetect how many breakpoints are supported dynamically... 15060b57cec5SDimitry Andric static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX; 15070b57cec5SDimitry Andric if (g_num_supported_hw_breakpoints == UINT32_MAX) { 15080b57cec5SDimitry Andric // Set this to zero in case we can't tell if there are any HW breakpoints 15090b57cec5SDimitry Andric g_num_supported_hw_breakpoints = 0; 15100b57cec5SDimitry Andric 15110b57cec5SDimitry Andric uint32_t register_DBGDIDR; 15120b57cec5SDimitry Andric 15130b57cec5SDimitry Andric asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 15140b57cec5SDimitry Andric g_num_supported_hw_breakpoints = Bits32(register_DBGDIDR, 27, 24); 15150b57cec5SDimitry Andric // Zero is reserved for the BRP count, so don't increment it if it is zero 15160b57cec5SDimitry Andric if (g_num_supported_hw_breakpoints > 0) 15170b57cec5SDimitry Andric g_num_supported_hw_breakpoints++; 15180b57cec5SDimitry Andric } 15190b57cec5SDimitry Andric return g_num_supported_hw_breakpoints; 15200b57cec5SDimitry Andric #else 15210b57cec5SDimitry Andric // TODO: figure out remote case here! 15220b57cec5SDimitry Andric return 6; 15230b57cec5SDimitry Andric #endif 15240b57cec5SDimitry Andric } 15250b57cec5SDimitry Andric 15260b57cec5SDimitry Andric uint32_t RegisterContextDarwin_arm::SetHardwareBreakpoint(lldb::addr_t addr, 15270b57cec5SDimitry Andric size_t size) { 15280b57cec5SDimitry Andric // Make sure our address isn't bogus 15290b57cec5SDimitry Andric if (addr & 1) 15300b57cec5SDimitry Andric return LLDB_INVALID_INDEX32; 15310b57cec5SDimitry Andric 15320b57cec5SDimitry Andric int kret = ReadDBG(false); 15330b57cec5SDimitry Andric 15340b57cec5SDimitry Andric if (kret == KERN_SUCCESS) { 15350b57cec5SDimitry Andric const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints(); 15360b57cec5SDimitry Andric uint32_t i; 15370b57cec5SDimitry Andric for (i = 0; i < num_hw_breakpoints; ++i) { 15380b57cec5SDimitry Andric if ((dbg.bcr[i] & BCR_ENABLE) == 0) 15390b57cec5SDimitry Andric break; // We found an available hw breakpoint slot (in i) 15400b57cec5SDimitry Andric } 15410b57cec5SDimitry Andric 15420b57cec5SDimitry Andric // See if we found an available hw breakpoint slot above 15430b57cec5SDimitry Andric if (i < num_hw_breakpoints) { 15440b57cec5SDimitry Andric // Make sure bits 1:0 are clear in our address 15450b57cec5SDimitry Andric dbg.bvr[i] = addr & ~((lldb::addr_t)3); 15460b57cec5SDimitry Andric 15470b57cec5SDimitry Andric if (size == 2 || addr & 2) { 15480b57cec5SDimitry Andric uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1; 15490b57cec5SDimitry Andric 15500b57cec5SDimitry Andric // We have a thumb breakpoint 15510b57cec5SDimitry Andric // We have an ARM breakpoint 15520b57cec5SDimitry Andric dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch 15530b57cec5SDimitry Andric byte_addr_select | // Set the correct byte address select 15540b57cec5SDimitry Andric // so we only trigger on the correct 15550b57cec5SDimitry Andric // opcode 15560b57cec5SDimitry Andric S_USER | // Which modes should this breakpoint stop in? 15570b57cec5SDimitry Andric BCR_ENABLE; // Enable this hardware breakpoint 15580b57cec5SDimitry Andric // if (log) log->Printf 15590b57cec5SDimitry Andric // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 15600b57cec5SDimitry Andric // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 15610b57cec5SDimitry Andric // 0x%8.8x (Thumb)", 15620b57cec5SDimitry Andric // addr, 15630b57cec5SDimitry Andric // size, 15640b57cec5SDimitry Andric // i, 15650b57cec5SDimitry Andric // i, 15660b57cec5SDimitry Andric // dbg.bvr[i], 15670b57cec5SDimitry Andric // dbg.bcr[i]); 15680b57cec5SDimitry Andric } else if (size == 4) { 15690b57cec5SDimitry Andric // We have an ARM breakpoint 15700b57cec5SDimitry Andric dbg.bcr[i] = 15710b57cec5SDimitry Andric BCR_M_IMVA_MATCH | // Stop on address mismatch 15720b57cec5SDimitry Andric BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA 15730b57cec5SDimitry Andric S_USER | // Which modes should this breakpoint stop in? 15740b57cec5SDimitry Andric BCR_ENABLE; // Enable this hardware breakpoint 15750b57cec5SDimitry Andric // if (log) log->Printf 15760b57cec5SDimitry Andric // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( 15770b57cec5SDimitry Andric // addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 15780b57cec5SDimitry Andric // 0x%8.8x (ARM)", 15790b57cec5SDimitry Andric // addr, 15800b57cec5SDimitry Andric // size, 15810b57cec5SDimitry Andric // i, 15820b57cec5SDimitry Andric // i, 15830b57cec5SDimitry Andric // dbg.bvr[i], 15840b57cec5SDimitry Andric // dbg.bcr[i]); 15850b57cec5SDimitry Andric } 15860b57cec5SDimitry Andric 15870b57cec5SDimitry Andric kret = WriteDBG(); 15880b57cec5SDimitry Andric // if (log) log->Printf 15890b57cec5SDimitry Andric // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint() 15900b57cec5SDimitry Andric // WriteDBG() => 0x%8.8x.", kret); 15910b57cec5SDimitry Andric 15920b57cec5SDimitry Andric if (kret == KERN_SUCCESS) 15930b57cec5SDimitry Andric return i; 15940b57cec5SDimitry Andric } 15950b57cec5SDimitry Andric // else 15960b57cec5SDimitry Andric // { 15970b57cec5SDimitry Andric // if (log) log->Printf 15980b57cec5SDimitry Andric // ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr = 15990b57cec5SDimitry Andric // %8.8p, size = %u) => all hardware breakpoint resources are 16000b57cec5SDimitry Andric // being used.", addr, size); 16010b57cec5SDimitry Andric // } 16020b57cec5SDimitry Andric } 16030b57cec5SDimitry Andric 16040b57cec5SDimitry Andric return LLDB_INVALID_INDEX32; 16050b57cec5SDimitry Andric } 16060b57cec5SDimitry Andric 16070b57cec5SDimitry Andric bool RegisterContextDarwin_arm::ClearHardwareBreakpoint(uint32_t hw_index) { 16080b57cec5SDimitry Andric int kret = ReadDBG(false); 16090b57cec5SDimitry Andric 16100b57cec5SDimitry Andric const uint32_t num_hw_points = NumSupportedHardwareBreakpoints(); 16110b57cec5SDimitry Andric if (kret == KERN_SUCCESS) { 16120b57cec5SDimitry Andric if (hw_index < num_hw_points) { 16130b57cec5SDimitry Andric dbg.bcr[hw_index] = 0; 16140b57cec5SDimitry Andric // if (log) log->Printf 16150b57cec5SDimitry Andric // ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) - 16160b57cec5SDimitry Andric // BVR%u = 0x%8.8x BCR%u = 0x%8.8x", 16170b57cec5SDimitry Andric // hw_index, 16180b57cec5SDimitry Andric // hw_index, 16190b57cec5SDimitry Andric // dbg.bvr[hw_index], 16200b57cec5SDimitry Andric // hw_index, 16210b57cec5SDimitry Andric // dbg.bcr[hw_index]); 16220b57cec5SDimitry Andric 16230b57cec5SDimitry Andric kret = WriteDBG(); 16240b57cec5SDimitry Andric 16250b57cec5SDimitry Andric if (kret == KERN_SUCCESS) 16260b57cec5SDimitry Andric return true; 16270b57cec5SDimitry Andric } 16280b57cec5SDimitry Andric } 16290b57cec5SDimitry Andric return false; 16300b57cec5SDimitry Andric } 16310b57cec5SDimitry Andric 16320b57cec5SDimitry Andric uint32_t RegisterContextDarwin_arm::NumSupportedHardwareWatchpoints() { 16330b57cec5SDimitry Andric #if defined(__APPLE__) && defined(__arm__) 16340b57cec5SDimitry Andric // Set the init value to something that will let us know that we need to 16350b57cec5SDimitry Andric // autodetect how many watchpoints are supported dynamically... 16360b57cec5SDimitry Andric static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX; 16370b57cec5SDimitry Andric if (g_num_supported_hw_watchpoints == UINT32_MAX) { 16380b57cec5SDimitry Andric // Set this to zero in case we can't tell if there are any HW breakpoints 16390b57cec5SDimitry Andric g_num_supported_hw_watchpoints = 0; 16400b57cec5SDimitry Andric 16410b57cec5SDimitry Andric uint32_t register_DBGDIDR; 16420b57cec5SDimitry Andric asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR)); 16430b57cec5SDimitry Andric g_num_supported_hw_watchpoints = Bits32(register_DBGDIDR, 31, 28) + 1; 16440b57cec5SDimitry Andric } 16450b57cec5SDimitry Andric return g_num_supported_hw_watchpoints; 16460b57cec5SDimitry Andric #else 16470b57cec5SDimitry Andric // TODO: figure out remote case here! 16480b57cec5SDimitry Andric return 2; 16490b57cec5SDimitry Andric #endif 16500b57cec5SDimitry Andric } 16510b57cec5SDimitry Andric 16520b57cec5SDimitry Andric uint32_t RegisterContextDarwin_arm::SetHardwareWatchpoint(lldb::addr_t addr, 16530b57cec5SDimitry Andric size_t size, 16540b57cec5SDimitry Andric bool read, 16550b57cec5SDimitry Andric bool write) { 16560b57cec5SDimitry Andric const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 16570b57cec5SDimitry Andric 16580b57cec5SDimitry Andric // Can't watch zero bytes 16590b57cec5SDimitry Andric if (size == 0) 16600b57cec5SDimitry Andric return LLDB_INVALID_INDEX32; 16610b57cec5SDimitry Andric 16620b57cec5SDimitry Andric // We must watch for either read or write 16630b57cec5SDimitry Andric if (!read && !write) 16640b57cec5SDimitry Andric return LLDB_INVALID_INDEX32; 16650b57cec5SDimitry Andric 16660b57cec5SDimitry Andric // Can't watch more than 4 bytes per WVR/WCR pair 16670b57cec5SDimitry Andric if (size > 4) 16680b57cec5SDimitry Andric return LLDB_INVALID_INDEX32; 16690b57cec5SDimitry Andric 16700b57cec5SDimitry Andric // We can only watch up to four bytes that follow a 4 byte aligned address 16710b57cec5SDimitry Andric // per watchpoint register pair. Since we have at most so we can only watch 16720b57cec5SDimitry Andric // until the next 4 byte boundary and we need to make sure we can properly 16730b57cec5SDimitry Andric // encode this. 16740b57cec5SDimitry Andric uint32_t addr_word_offset = addr % 4; 16750b57cec5SDimitry Andric // if (log) log->Printf 16760b57cec5SDimitry Andric // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - 16770b57cec5SDimitry Andric // addr_word_offset = 0x%8.8x", addr_word_offset); 16780b57cec5SDimitry Andric 16790b57cec5SDimitry Andric uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset; 16800b57cec5SDimitry Andric // if (log) log->Printf 16810b57cec5SDimitry Andric // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask = 16820b57cec5SDimitry Andric // 0x%8.8x", byte_mask); 16830b57cec5SDimitry Andric if (byte_mask > 0xfu) 16840b57cec5SDimitry Andric return LLDB_INVALID_INDEX32; 16850b57cec5SDimitry Andric 16860b57cec5SDimitry Andric // Read the debug state 16870b57cec5SDimitry Andric int kret = ReadDBG(false); 16880b57cec5SDimitry Andric 16890b57cec5SDimitry Andric if (kret == KERN_SUCCESS) { 16900b57cec5SDimitry Andric // Check to make sure we have the needed hardware support 16910b57cec5SDimitry Andric uint32_t i = 0; 16920b57cec5SDimitry Andric 16930b57cec5SDimitry Andric for (i = 0; i < num_hw_watchpoints; ++i) { 16940b57cec5SDimitry Andric if ((dbg.wcr[i] & WCR_ENABLE) == 0) 16950b57cec5SDimitry Andric break; // We found an available hw breakpoint slot (in i) 16960b57cec5SDimitry Andric } 16970b57cec5SDimitry Andric 16980b57cec5SDimitry Andric // See if we found an available hw breakpoint slot above 16990b57cec5SDimitry Andric if (i < num_hw_watchpoints) { 17000b57cec5SDimitry Andric // Make the byte_mask into a valid Byte Address Select mask 17010b57cec5SDimitry Andric uint32_t byte_address_select = byte_mask << 5; 17020b57cec5SDimitry Andric // Make sure bits 1:0 are clear in our address 17030b57cec5SDimitry Andric dbg.wvr[i] = addr & ~((lldb::addr_t)3); 17040b57cec5SDimitry Andric dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA 17050b57cec5SDimitry Andric // that we will watch 17060b57cec5SDimitry Andric S_USER | // Stop only in user mode 17070b57cec5SDimitry Andric (read ? WCR_LOAD : 0) | // Stop on read access? 17080b57cec5SDimitry Andric (write ? WCR_STORE : 0) | // Stop on write access? 17090b57cec5SDimitry Andric WCR_ENABLE; // Enable this watchpoint; 17100b57cec5SDimitry Andric 17110b57cec5SDimitry Andric kret = WriteDBG(); 17120b57cec5SDimitry Andric // if (log) log->Printf 17130b57cec5SDimitry Andric // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() 17140b57cec5SDimitry Andric // WriteDBG() => 0x%8.8x.", kret); 17150b57cec5SDimitry Andric 17160b57cec5SDimitry Andric if (kret == KERN_SUCCESS) 17170b57cec5SDimitry Andric return i; 17180b57cec5SDimitry Andric } else { 17190b57cec5SDimitry Andric // if (log) log->Printf 17200b57cec5SDimitry Andric // ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All 17210b57cec5SDimitry Andric // hardware resources (%u) are in use.", num_hw_watchpoints); 17220b57cec5SDimitry Andric } 17230b57cec5SDimitry Andric } 17240b57cec5SDimitry Andric return LLDB_INVALID_INDEX32; 17250b57cec5SDimitry Andric } 17260b57cec5SDimitry Andric 17270b57cec5SDimitry Andric bool RegisterContextDarwin_arm::ClearHardwareWatchpoint(uint32_t hw_index) { 17280b57cec5SDimitry Andric int kret = ReadDBG(false); 17290b57cec5SDimitry Andric 17300b57cec5SDimitry Andric const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 17310b57cec5SDimitry Andric if (kret == KERN_SUCCESS) { 17320b57cec5SDimitry Andric if (hw_index < num_hw_points) { 17330b57cec5SDimitry Andric dbg.wcr[hw_index] = 0; 17340b57cec5SDimitry Andric // if (log) log->Printf 17350b57cec5SDimitry Andric // ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) - 17360b57cec5SDimitry Andric // WVR%u = 0x%8.8x WCR%u = 0x%8.8x", 17370b57cec5SDimitry Andric // hw_index, 17380b57cec5SDimitry Andric // hw_index, 17390b57cec5SDimitry Andric // dbg.wvr[hw_index], 17400b57cec5SDimitry Andric // hw_index, 17410b57cec5SDimitry Andric // dbg.wcr[hw_index]); 17420b57cec5SDimitry Andric 17430b57cec5SDimitry Andric kret = WriteDBG(); 17440b57cec5SDimitry Andric 17450b57cec5SDimitry Andric if (kret == KERN_SUCCESS) 17460b57cec5SDimitry Andric return true; 17470b57cec5SDimitry Andric } 17480b57cec5SDimitry Andric } 17490b57cec5SDimitry Andric return false; 17500b57cec5SDimitry Andric } 1751