1*5f757f3fSDimitry Andric //===-- RegisterContextNetBSD_i386.cpp --------------------------*- C++ -*-===//
25ffd83dbSDimitry Andric //
35ffd83dbSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
45ffd83dbSDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
55ffd83dbSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
65ffd83dbSDimitry Andric //
7*5f757f3fSDimitry Andric //===----------------------------------------------------------------------===//
85ffd83dbSDimitry Andric 
95ffd83dbSDimitry Andric #include "RegisterContextNetBSD_i386.h"
105ffd83dbSDimitry Andric #include "RegisterContextPOSIX_x86.h"
115ffd83dbSDimitry Andric 
125ffd83dbSDimitry Andric using namespace lldb_private;
135ffd83dbSDimitry Andric using namespace lldb;
145ffd83dbSDimitry Andric 
155ffd83dbSDimitry Andric // this needs to match 'struct reg'
165ffd83dbSDimitry Andric struct GPR {
175ffd83dbSDimitry Andric   uint32_t eax;
185ffd83dbSDimitry Andric   uint32_t ecx;
195ffd83dbSDimitry Andric   uint32_t edx;
205ffd83dbSDimitry Andric   uint32_t ebx;
215ffd83dbSDimitry Andric   uint32_t esp;
225ffd83dbSDimitry Andric   uint32_t ebp;
235ffd83dbSDimitry Andric   uint32_t esi;
245ffd83dbSDimitry Andric   uint32_t edi;
255ffd83dbSDimitry Andric   uint32_t eip;
265ffd83dbSDimitry Andric   uint32_t eflags;
275ffd83dbSDimitry Andric   uint32_t cs;
285ffd83dbSDimitry Andric   uint32_t ss;
295ffd83dbSDimitry Andric   uint32_t ds;
305ffd83dbSDimitry Andric   uint32_t es;
315ffd83dbSDimitry Andric   uint32_t fs;
325ffd83dbSDimitry Andric   uint32_t gs;
335ffd83dbSDimitry Andric };
345ffd83dbSDimitry Andric 
355ffd83dbSDimitry Andric struct FPR_i386 {
365ffd83dbSDimitry Andric   uint16_t fctrl;     // FPU Control Word (fcw)
375ffd83dbSDimitry Andric   uint16_t fstat;     // FPU Status Word (fsw)
385ffd83dbSDimitry Andric   uint16_t ftag;      // FPU Tag Word (ftw)
395ffd83dbSDimitry Andric   uint16_t fop;       // Last Instruction Opcode (fop)
405ffd83dbSDimitry Andric   union {
415ffd83dbSDimitry Andric     struct {
425ffd83dbSDimitry Andric       uint64_t fip; // Instruction Pointer
435ffd83dbSDimitry Andric       uint64_t fdp; // Data Pointer
445ffd83dbSDimitry Andric     } x86_64;
455ffd83dbSDimitry Andric     struct {
465ffd83dbSDimitry Andric       uint32_t fioff; // FPU IP Offset (fip)
475ffd83dbSDimitry Andric       uint32_t fiseg; // FPU IP Selector (fcs)
485ffd83dbSDimitry Andric       uint32_t fooff; // FPU Operand Pointer Offset (foo)
495ffd83dbSDimitry Andric       uint32_t foseg; // FPU Operand Pointer Selector (fos)
505ffd83dbSDimitry Andric     } i386_; // Added _ in the end to avoid error with gcc defining i386 in some
515ffd83dbSDimitry Andric              // cases
525ffd83dbSDimitry Andric   } ptr;
535ffd83dbSDimitry Andric   uint32_t mxcsr;     // MXCSR Register State
545ffd83dbSDimitry Andric   uint32_t mxcsrmask; // MXCSR Mask
555ffd83dbSDimitry Andric   MMSReg stmm[8];     // 8*16 bytes for each FP-reg = 128 bytes
565ffd83dbSDimitry Andric   XMMReg xmm[8];      // 8*16 bytes for each XMM-reg = 128 bytes
575ffd83dbSDimitry Andric   uint32_t padding[56];
585ffd83dbSDimitry Andric };
595ffd83dbSDimitry Andric 
605ffd83dbSDimitry Andric struct UserArea {
615ffd83dbSDimitry Andric   GPR gpr;
625ffd83dbSDimitry Andric   FPR_i386 i387;
635ffd83dbSDimitry Andric   uint32_t u_debugreg[8]; // Debug registers (DR0 - DR7).
645ffd83dbSDimitry Andric   uint32_t tlsbase;
655ffd83dbSDimitry Andric };
665ffd83dbSDimitry Andric 
675ffd83dbSDimitry Andric #define DR_SIZE sizeof(((UserArea *)NULL)->u_debugreg[0])
685ffd83dbSDimitry Andric #define DR_OFFSET(reg_index)                                                   \
695ffd83dbSDimitry Andric   (LLVM_EXTENSION offsetof(UserArea, u_debugreg[reg_index]))
705ffd83dbSDimitry Andric 
715ffd83dbSDimitry Andric // Include RegisterInfos_i386 to declare our g_register_infos_i386 structure.
725ffd83dbSDimitry Andric #define DECLARE_REGISTER_INFOS_I386_STRUCT
735ffd83dbSDimitry Andric #include "RegisterInfos_i386.h"
745ffd83dbSDimitry Andric #undef DECLARE_REGISTER_INFOS_I386_STRUCT
755ffd83dbSDimitry Andric 
RegisterContextNetBSD_i386(const ArchSpec & target_arch)765ffd83dbSDimitry Andric RegisterContextNetBSD_i386::RegisterContextNetBSD_i386(
775ffd83dbSDimitry Andric     const ArchSpec &target_arch)
785ffd83dbSDimitry Andric     : RegisterInfoInterface(target_arch) {}
795ffd83dbSDimitry Andric 
GetGPRSize() const805ffd83dbSDimitry Andric size_t RegisterContextNetBSD_i386::GetGPRSize() const { return sizeof(GPR); }
815ffd83dbSDimitry Andric 
GetRegisterInfo() const825ffd83dbSDimitry Andric const RegisterInfo *RegisterContextNetBSD_i386::GetRegisterInfo() const {
83bdd1243dSDimitry Andric   switch (GetTargetArchitecture().GetMachine()) {
845ffd83dbSDimitry Andric   case llvm::Triple::x86:
855ffd83dbSDimitry Andric   case llvm::Triple::x86_64:
865ffd83dbSDimitry Andric     return g_register_infos_i386;
875ffd83dbSDimitry Andric   default:
885ffd83dbSDimitry Andric     assert(false && "Unhandled target architecture.");
895ffd83dbSDimitry Andric     return nullptr;
905ffd83dbSDimitry Andric   }
915ffd83dbSDimitry Andric }
925ffd83dbSDimitry Andric 
GetRegisterCount() const935ffd83dbSDimitry Andric uint32_t RegisterContextNetBSD_i386::GetRegisterCount() const {
945ffd83dbSDimitry Andric   return static_cast<uint32_t>(sizeof(g_register_infos_i386) /
955ffd83dbSDimitry Andric                                sizeof(g_register_infos_i386[0]));
965ffd83dbSDimitry Andric }
97