15ffd83dbSDimitry Andric //===-- RegisterInfoPOSIX_arm64.cpp ---------------------------------------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===---------------------------------------------------------------------===//
80b57cec5SDimitry Andric
90b57cec5SDimitry Andric #include <cassert>
10fe6060f1SDimitry Andric #include <cstddef>
110b57cec5SDimitry Andric #include <vector>
120b57cec5SDimitry Andric
130b57cec5SDimitry Andric #include "lldb/lldb-defines.h"
140b57cec5SDimitry Andric #include "llvm/Support/Compiler.h"
150b57cec5SDimitry Andric
160b57cec5SDimitry Andric #include "RegisterInfoPOSIX_arm64.h"
170b57cec5SDimitry Andric
180b57cec5SDimitry Andric // Based on RegisterContextDarwin_arm64.cpp
190b57cec5SDimitry Andric #define GPR_OFFSET(idx) ((idx)*8)
200b57cec5SDimitry Andric #define GPR_OFFSET_NAME(reg) \
210b57cec5SDimitry Andric (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg))
220b57cec5SDimitry Andric
230b57cec5SDimitry Andric #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR))
240b57cec5SDimitry Andric #define FPU_OFFSET_NAME(reg) \
250b57cec5SDimitry Andric (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \
260b57cec5SDimitry Andric sizeof(RegisterInfoPOSIX_arm64::GPR))
270b57cec5SDimitry Andric
28e8d8bef9SDimitry Andric // This information is based on AArch64 with SVE architecture reference manual.
29e8d8bef9SDimitry Andric // AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR
30e8d8bef9SDimitry Andric // (First Fault) register and a VG (Vector Granule) pseudo register.
31e8d8bef9SDimitry Andric
32e8d8bef9SDimitry Andric // SVE 16-byte quad word is the basic unit of expansion in vector length.
33e8d8bef9SDimitry Andric #define SVE_QUAD_WORD_BYTES 16
34e8d8bef9SDimitry Andric
35e8d8bef9SDimitry Andric // Vector length is the multiplier which decides the no of quad words,
36e8d8bef9SDimitry Andric // (multiples of 128-bits or 16-bytes) present in a Z register. Vector length
37e8d8bef9SDimitry Andric // is decided during execution and can change at runtime. SVE AArch64 register
38e8d8bef9SDimitry Andric // infos have modes one for each valid value of vector length. A change in
39e8d8bef9SDimitry Andric // vector length requires register context to update sizes of SVE Z, P and FFR.
40e8d8bef9SDimitry Andric // Also register context needs to update byte offsets of all registers affected
41e8d8bef9SDimitry Andric // by the change in vector length.
42e8d8bef9SDimitry Andric #define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoPOSIX_arm64::GPR)
43e8d8bef9SDimitry Andric
44e8d8bef9SDimitry Andric #define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX
45e8d8bef9SDimitry Andric
460b57cec5SDimitry Andric #define EXC_OFFSET_NAME(reg) \
470b57cec5SDimitry Andric (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) + \
480b57cec5SDimitry Andric sizeof(RegisterInfoPOSIX_arm64::GPR) + \
490b57cec5SDimitry Andric sizeof(RegisterInfoPOSIX_arm64::FPU))
500b57cec5SDimitry Andric #define DBG_OFFSET_NAME(reg) \
510b57cec5SDimitry Andric (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) + \
520b57cec5SDimitry Andric sizeof(RegisterInfoPOSIX_arm64::GPR) + \
530b57cec5SDimitry Andric sizeof(RegisterInfoPOSIX_arm64::FPU) + \
540b57cec5SDimitry Andric sizeof(RegisterInfoPOSIX_arm64::EXC))
550b57cec5SDimitry Andric
560b57cec5SDimitry Andric #define DEFINE_DBG(reg, i) \
570b57cec5SDimitry Andric #reg, NULL, \
580b57cec5SDimitry Andric sizeof(((RegisterInfoPOSIX_arm64::DBG *) NULL)->reg[i]), \
590b57cec5SDimitry Andric DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \
600b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
610b57cec5SDimitry Andric LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
620b57cec5SDimitry Andric dbg_##reg##i }, \
6306c3fb27SDimitry Andric NULL, NULL, NULL,
640b57cec5SDimitry Andric #define REG_CONTEXT_SIZE \
650b57cec5SDimitry Andric (sizeof(RegisterInfoPOSIX_arm64::GPR) + \
660b57cec5SDimitry Andric sizeof(RegisterInfoPOSIX_arm64::FPU) + \
670b57cec5SDimitry Andric sizeof(RegisterInfoPOSIX_arm64::EXC))
680b57cec5SDimitry Andric
690b57cec5SDimitry Andric // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
700b57cec5SDimitry Andric #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
710b57cec5SDimitry Andric #include "RegisterInfos_arm64.h"
72e8d8bef9SDimitry Andric #include "RegisterInfos_arm64_sve.h"
730b57cec5SDimitry Andric #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
740b57cec5SDimitry Andric
7581ad6265SDimitry Andric static lldb_private::RegisterInfo g_register_infos_pauth[] = {
7681ad6265SDimitry Andric DEFINE_EXTENSION_REG(data_mask), DEFINE_EXTENSION_REG(code_mask)};
7781ad6265SDimitry Andric
7881ad6265SDimitry Andric static lldb_private::RegisterInfo g_register_infos_mte[] = {
7981ad6265SDimitry Andric DEFINE_EXTENSION_REG(mte_ctrl)};
8081ad6265SDimitry Andric
8106c3fb27SDimitry Andric static lldb_private::RegisterInfo g_register_infos_tls[] = {
825f757f3fSDimitry Andric DEFINE_EXTENSION_REG(tpidr),
835f757f3fSDimitry Andric // Only present when SME is present
845f757f3fSDimitry Andric DEFINE_EXTENSION_REG(tpidr2)};
855f757f3fSDimitry Andric
865f757f3fSDimitry Andric static lldb_private::RegisterInfo g_register_infos_sme[] = {
875f757f3fSDimitry Andric DEFINE_EXTENSION_REG(svcr),
885f757f3fSDimitry Andric DEFINE_EXTENSION_REG(svg),
895f757f3fSDimitry Andric // 16 is a default size we will change later.
905f757f3fSDimitry Andric {"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
915f757f3fSDimitry Andric KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
925f757f3fSDimitry Andric
935f757f3fSDimitry Andric static lldb_private::RegisterInfo g_register_infos_sme2[] = {
945f757f3fSDimitry Andric {"zt0", nullptr, 64, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
955f757f3fSDimitry Andric KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
9606c3fb27SDimitry Andric
975ffd83dbSDimitry Andric // Number of register sets provided by this context.
985ffd83dbSDimitry Andric enum {
995ffd83dbSDimitry Andric k_num_gpr_registers = gpr_w28 - gpr_x0 + 1,
1005ffd83dbSDimitry Andric k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1,
101e8d8bef9SDimitry Andric k_num_sve_registers = sve_ffr - sve_vg + 1,
102fe6060f1SDimitry Andric k_num_mte_register = 1,
1035f757f3fSDimitry Andric // Number of TLS registers is dynamic so it is not listed here.
104fe6060f1SDimitry Andric k_num_pauth_register = 2,
1055f757f3fSDimitry Andric // SME2's ZT0 will also be added to this set if present. So this number is
1065f757f3fSDimitry Andric // only for SME1 registers.
1075f757f3fSDimitry Andric k_num_sme_register = 3,
108fe6060f1SDimitry Andric k_num_register_sets_default = 2,
109e8d8bef9SDimitry Andric k_num_register_sets = 3
1105ffd83dbSDimitry Andric };
1115ffd83dbSDimitry Andric
1125ffd83dbSDimitry Andric // ARM64 general purpose registers.
1135ffd83dbSDimitry Andric static const uint32_t g_gpr_regnums_arm64[] = {
1145ffd83dbSDimitry Andric gpr_x0, gpr_x1, gpr_x2, gpr_x3,
1155ffd83dbSDimitry Andric gpr_x4, gpr_x5, gpr_x6, gpr_x7,
1165ffd83dbSDimitry Andric gpr_x8, gpr_x9, gpr_x10, gpr_x11,
1175ffd83dbSDimitry Andric gpr_x12, gpr_x13, gpr_x14, gpr_x15,
1185ffd83dbSDimitry Andric gpr_x16, gpr_x17, gpr_x18, gpr_x19,
1195ffd83dbSDimitry Andric gpr_x20, gpr_x21, gpr_x22, gpr_x23,
1205ffd83dbSDimitry Andric gpr_x24, gpr_x25, gpr_x26, gpr_x27,
1215ffd83dbSDimitry Andric gpr_x28, gpr_fp, gpr_lr, gpr_sp,
1225ffd83dbSDimitry Andric gpr_pc, gpr_cpsr, gpr_w0, gpr_w1,
1235ffd83dbSDimitry Andric gpr_w2, gpr_w3, gpr_w4, gpr_w5,
1245ffd83dbSDimitry Andric gpr_w6, gpr_w7, gpr_w8, gpr_w9,
1255ffd83dbSDimitry Andric gpr_w10, gpr_w11, gpr_w12, gpr_w13,
1265ffd83dbSDimitry Andric gpr_w14, gpr_w15, gpr_w16, gpr_w17,
1275ffd83dbSDimitry Andric gpr_w18, gpr_w19, gpr_w20, gpr_w21,
1285ffd83dbSDimitry Andric gpr_w22, gpr_w23, gpr_w24, gpr_w25,
1295ffd83dbSDimitry Andric gpr_w26, gpr_w27, gpr_w28, LLDB_INVALID_REGNUM};
1305ffd83dbSDimitry Andric
1315ffd83dbSDimitry Andric static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) -
1325ffd83dbSDimitry Andric 1) == k_num_gpr_registers,
1335ffd83dbSDimitry Andric "g_gpr_regnums_arm64 has wrong number of register infos");
1345ffd83dbSDimitry Andric
1355ffd83dbSDimitry Andric // ARM64 floating point registers.
1365ffd83dbSDimitry Andric static const uint32_t g_fpu_regnums_arm64[] = {
1375ffd83dbSDimitry Andric fpu_v0, fpu_v1, fpu_v2,
1385ffd83dbSDimitry Andric fpu_v3, fpu_v4, fpu_v5,
1395ffd83dbSDimitry Andric fpu_v6, fpu_v7, fpu_v8,
1405ffd83dbSDimitry Andric fpu_v9, fpu_v10, fpu_v11,
1415ffd83dbSDimitry Andric fpu_v12, fpu_v13, fpu_v14,
1425ffd83dbSDimitry Andric fpu_v15, fpu_v16, fpu_v17,
1435ffd83dbSDimitry Andric fpu_v18, fpu_v19, fpu_v20,
1445ffd83dbSDimitry Andric fpu_v21, fpu_v22, fpu_v23,
1455ffd83dbSDimitry Andric fpu_v24, fpu_v25, fpu_v26,
1465ffd83dbSDimitry Andric fpu_v27, fpu_v28, fpu_v29,
1475ffd83dbSDimitry Andric fpu_v30, fpu_v31, fpu_s0,
1485ffd83dbSDimitry Andric fpu_s1, fpu_s2, fpu_s3,
1495ffd83dbSDimitry Andric fpu_s4, fpu_s5, fpu_s6,
1505ffd83dbSDimitry Andric fpu_s7, fpu_s8, fpu_s9,
1515ffd83dbSDimitry Andric fpu_s10, fpu_s11, fpu_s12,
1525ffd83dbSDimitry Andric fpu_s13, fpu_s14, fpu_s15,
1535ffd83dbSDimitry Andric fpu_s16, fpu_s17, fpu_s18,
1545ffd83dbSDimitry Andric fpu_s19, fpu_s20, fpu_s21,
1555ffd83dbSDimitry Andric fpu_s22, fpu_s23, fpu_s24,
1565ffd83dbSDimitry Andric fpu_s25, fpu_s26, fpu_s27,
1575ffd83dbSDimitry Andric fpu_s28, fpu_s29, fpu_s30,
1585ffd83dbSDimitry Andric fpu_s31, fpu_d0, fpu_d1,
1595ffd83dbSDimitry Andric fpu_d2, fpu_d3, fpu_d4,
1605ffd83dbSDimitry Andric fpu_d5, fpu_d6, fpu_d7,
1615ffd83dbSDimitry Andric fpu_d8, fpu_d9, fpu_d10,
1625ffd83dbSDimitry Andric fpu_d11, fpu_d12, fpu_d13,
1635ffd83dbSDimitry Andric fpu_d14, fpu_d15, fpu_d16,
1645ffd83dbSDimitry Andric fpu_d17, fpu_d18, fpu_d19,
1655ffd83dbSDimitry Andric fpu_d20, fpu_d21, fpu_d22,
1665ffd83dbSDimitry Andric fpu_d23, fpu_d24, fpu_d25,
1675ffd83dbSDimitry Andric fpu_d26, fpu_d27, fpu_d28,
1685ffd83dbSDimitry Andric fpu_d29, fpu_d30, fpu_d31,
1695ffd83dbSDimitry Andric fpu_fpsr, fpu_fpcr, LLDB_INVALID_REGNUM};
1705ffd83dbSDimitry Andric static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) -
1715ffd83dbSDimitry Andric 1) == k_num_fpr_registers,
1725ffd83dbSDimitry Andric "g_fpu_regnums_arm64 has wrong number of register infos");
173e8d8bef9SDimitry Andric
174e8d8bef9SDimitry Andric // ARM64 SVE registers.
175e8d8bef9SDimitry Andric static const uint32_t g_sve_regnums_arm64[] = {
176e8d8bef9SDimitry Andric sve_vg, sve_z0, sve_z1,
177e8d8bef9SDimitry Andric sve_z2, sve_z3, sve_z4,
178e8d8bef9SDimitry Andric sve_z5, sve_z6, sve_z7,
179e8d8bef9SDimitry Andric sve_z8, sve_z9, sve_z10,
180e8d8bef9SDimitry Andric sve_z11, sve_z12, sve_z13,
181e8d8bef9SDimitry Andric sve_z14, sve_z15, sve_z16,
182e8d8bef9SDimitry Andric sve_z17, sve_z18, sve_z19,
183e8d8bef9SDimitry Andric sve_z20, sve_z21, sve_z22,
184e8d8bef9SDimitry Andric sve_z23, sve_z24, sve_z25,
185e8d8bef9SDimitry Andric sve_z26, sve_z27, sve_z28,
186e8d8bef9SDimitry Andric sve_z29, sve_z30, sve_z31,
187e8d8bef9SDimitry Andric sve_p0, sve_p1, sve_p2,
188e8d8bef9SDimitry Andric sve_p3, sve_p4, sve_p5,
189e8d8bef9SDimitry Andric sve_p6, sve_p7, sve_p8,
190e8d8bef9SDimitry Andric sve_p9, sve_p10, sve_p11,
191e8d8bef9SDimitry Andric sve_p12, sve_p13, sve_p14,
192e8d8bef9SDimitry Andric sve_p15, sve_ffr, LLDB_INVALID_REGNUM};
193e8d8bef9SDimitry Andric static_assert(((sizeof g_sve_regnums_arm64 / sizeof g_sve_regnums_arm64[0]) -
194e8d8bef9SDimitry Andric 1) == k_num_sve_registers,
195e8d8bef9SDimitry Andric "g_sve_regnums_arm64 has wrong number of register infos");
196e8d8bef9SDimitry Andric
1975ffd83dbSDimitry Andric // Register sets for ARM64.
1985ffd83dbSDimitry Andric static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = {
1995ffd83dbSDimitry Andric {"General Purpose Registers", "gpr", k_num_gpr_registers,
2005ffd83dbSDimitry Andric g_gpr_regnums_arm64},
2015ffd83dbSDimitry Andric {"Floating Point Registers", "fpu", k_num_fpr_registers,
202e8d8bef9SDimitry Andric g_fpu_regnums_arm64},
203e8d8bef9SDimitry Andric {"Scalable Vector Extension Registers", "sve", k_num_sve_registers,
204e8d8bef9SDimitry Andric g_sve_regnums_arm64}};
2055ffd83dbSDimitry Andric
206fe6060f1SDimitry Andric static const lldb_private::RegisterSet g_reg_set_pauth_arm64 = {
20704eeddc0SDimitry Andric "Pointer Authentication Registers", "pauth", k_num_pauth_register, nullptr};
208fe6060f1SDimitry Andric
209fe6060f1SDimitry Andric static const lldb_private::RegisterSet g_reg_set_mte_arm64 = {
21004eeddc0SDimitry Andric "MTE Control Register", "mte", k_num_mte_register, nullptr};
2110b57cec5SDimitry Andric
2125f757f3fSDimitry Andric // The size of the TLS set is dynamic, so not listed here.
2135f757f3fSDimitry Andric
2145f757f3fSDimitry Andric static const lldb_private::RegisterSet g_reg_set_sme_arm64 = {
2155f757f3fSDimitry Andric "Scalable Matrix Extension Registers", "sme", k_num_sme_register, nullptr};
21606c3fb27SDimitry Andric
RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec & target_arch,lldb_private::Flags opt_regsets)2170b57cec5SDimitry Andric RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64(
218fe6060f1SDimitry Andric const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
2195ffd83dbSDimitry Andric : lldb_private::RegisterInfoAndSetInterface(target_arch),
220fe6060f1SDimitry Andric m_opt_regsets(opt_regsets) {
221fe6060f1SDimitry Andric switch (target_arch.GetMachine()) {
222fe6060f1SDimitry Andric case llvm::Triple::aarch64:
223fe6060f1SDimitry Andric case llvm::Triple::aarch64_32: {
224fe6060f1SDimitry Andric m_register_set_p = g_reg_sets_arm64;
225fe6060f1SDimitry Andric m_register_set_count = k_num_register_sets_default;
226fe6060f1SDimitry Andric m_per_regset_regnum_range[GPRegSet] = std::make_pair(gpr_x0, gpr_w28 + 1);
227fe6060f1SDimitry Andric m_per_regset_regnum_range[FPRegSet] = std::make_pair(fpu_v0, fpu_fpcr + 1);
228fe6060f1SDimitry Andric
229fe6060f1SDimitry Andric // Now configure register sets supported by current target. If we have a
230fe6060f1SDimitry Andric // dynamic register set like MTE, Pointer Authentication regset then we need
231fe6060f1SDimitry Andric // to create dynamic register infos and regset array. Push back all optional
232fe6060f1SDimitry Andric // register infos and regset and calculate register offsets accordingly.
2335f757f3fSDimitry Andric if (m_opt_regsets.AnySet(eRegsetMaskSVE | eRegsetMaskSSVE)) {
234fe6060f1SDimitry Andric m_register_info_p = g_register_infos_arm64_sve_le;
235fe6060f1SDimitry Andric m_register_info_count = sve_ffr + 1;
236fe6060f1SDimitry Andric m_per_regset_regnum_range[m_register_set_count++] =
237fe6060f1SDimitry Andric std::make_pair(sve_vg, sve_ffr + 1);
238fe6060f1SDimitry Andric } else {
239fe6060f1SDimitry Andric m_register_info_p = g_register_infos_arm64_le;
240fe6060f1SDimitry Andric m_register_info_count = fpu_fpcr + 1;
241fe6060f1SDimitry Andric }
242fe6060f1SDimitry Andric
243fe6060f1SDimitry Andric if (m_opt_regsets.AnySet(eRegsetMaskDynamic)) {
244fe6060f1SDimitry Andric llvm::ArrayRef<lldb_private::RegisterInfo> reg_infos_ref =
245bdd1243dSDimitry Andric llvm::ArrayRef(m_register_info_p, m_register_info_count);
246fe6060f1SDimitry Andric llvm::ArrayRef<lldb_private::RegisterSet> reg_sets_ref =
247bdd1243dSDimitry Andric llvm::ArrayRef(m_register_set_p, m_register_set_count);
248fe6060f1SDimitry Andric llvm::copy(reg_infos_ref, std::back_inserter(m_dynamic_reg_infos));
249fe6060f1SDimitry Andric llvm::copy(reg_sets_ref, std::back_inserter(m_dynamic_reg_sets));
250fe6060f1SDimitry Andric
251fe6060f1SDimitry Andric if (m_opt_regsets.AllSet(eRegsetMaskPAuth))
252fe6060f1SDimitry Andric AddRegSetPAuth();
253fe6060f1SDimitry Andric
254fe6060f1SDimitry Andric if (m_opt_regsets.AllSet(eRegsetMaskMTE))
255fe6060f1SDimitry Andric AddRegSetMTE();
256fe6060f1SDimitry Andric
2575f757f3fSDimitry Andric // The TLS set always contains tpidr but only has tpidr2 when SME is
2585f757f3fSDimitry Andric // present.
2595f757f3fSDimitry Andric AddRegSetTLS(m_opt_regsets.AllSet(eRegsetMaskSSVE));
2605f757f3fSDimitry Andric
2615f757f3fSDimitry Andric if (m_opt_regsets.AnySet(eRegsetMaskSSVE))
2625f757f3fSDimitry Andric AddRegSetSME(m_opt_regsets.AnySet(eRegsetMaskZT));
26306c3fb27SDimitry Andric
264fe6060f1SDimitry Andric m_register_info_count = m_dynamic_reg_infos.size();
265fe6060f1SDimitry Andric m_register_info_p = m_dynamic_reg_infos.data();
266fe6060f1SDimitry Andric m_register_set_p = m_dynamic_reg_sets.data();
267fe6060f1SDimitry Andric m_register_set_count = m_dynamic_reg_sets.size();
268fe6060f1SDimitry Andric }
269fe6060f1SDimitry Andric break;
270fe6060f1SDimitry Andric }
271fe6060f1SDimitry Andric default:
272fe6060f1SDimitry Andric assert(false && "Unhandled target architecture.");
273fe6060f1SDimitry Andric }
2745ffd83dbSDimitry Andric }
2755ffd83dbSDimitry Andric
GetRegisterCount() const2765ffd83dbSDimitry Andric uint32_t RegisterInfoPOSIX_arm64::GetRegisterCount() const {
277fe6060f1SDimitry Andric return m_register_info_count;
2785ffd83dbSDimitry Andric }
2790b57cec5SDimitry Andric
GetGPRSizeStatic()280bdd1243dSDimitry Andric size_t RegisterInfoPOSIX_arm64::GetGPRSizeStatic() {
2810b57cec5SDimitry Andric return sizeof(struct RegisterInfoPOSIX_arm64::GPR);
2820b57cec5SDimitry Andric }
2830b57cec5SDimitry Andric
GetFPRSize() const2845ffd83dbSDimitry Andric size_t RegisterInfoPOSIX_arm64::GetFPRSize() const {
2855ffd83dbSDimitry Andric return sizeof(struct RegisterInfoPOSIX_arm64::FPU);
2865ffd83dbSDimitry Andric }
2875ffd83dbSDimitry Andric
2880b57cec5SDimitry Andric const lldb_private::RegisterInfo *
GetRegisterInfo() const2890b57cec5SDimitry Andric RegisterInfoPOSIX_arm64::GetRegisterInfo() const {
2900b57cec5SDimitry Andric return m_register_info_p;
2910b57cec5SDimitry Andric }
2920b57cec5SDimitry Andric
GetRegisterSetCount() const2935ffd83dbSDimitry Andric size_t RegisterInfoPOSIX_arm64::GetRegisterSetCount() const {
294fe6060f1SDimitry Andric return m_register_set_count;
2955ffd83dbSDimitry Andric }
2965ffd83dbSDimitry Andric
GetRegisterSetFromRegisterIndex(uint32_t reg_index) const2975ffd83dbSDimitry Andric size_t RegisterInfoPOSIX_arm64::GetRegisterSetFromRegisterIndex(
2985ffd83dbSDimitry Andric uint32_t reg_index) const {
299fe6060f1SDimitry Andric for (const auto ®set_range : m_per_regset_regnum_range) {
300fe6060f1SDimitry Andric if (reg_index >= regset_range.second.first &&
301fe6060f1SDimitry Andric reg_index < regset_range.second.second)
302fe6060f1SDimitry Andric return regset_range.first;
303fe6060f1SDimitry Andric }
3045ffd83dbSDimitry Andric return LLDB_INVALID_REGNUM;
3055ffd83dbSDimitry Andric }
3065ffd83dbSDimitry Andric
3075ffd83dbSDimitry Andric const lldb_private::RegisterSet *
GetRegisterSet(size_t set_index) const3085ffd83dbSDimitry Andric RegisterInfoPOSIX_arm64::GetRegisterSet(size_t set_index) const {
309e8d8bef9SDimitry Andric if (set_index < GetRegisterSetCount())
310fe6060f1SDimitry Andric return &m_register_set_p[set_index];
3115ffd83dbSDimitry Andric return nullptr;
3120b57cec5SDimitry Andric }
313e8d8bef9SDimitry Andric
AddRegSetPAuth()314fe6060f1SDimitry Andric void RegisterInfoPOSIX_arm64::AddRegSetPAuth() {
315fe6060f1SDimitry Andric uint32_t pa_regnum = m_dynamic_reg_infos.size();
316fe6060f1SDimitry Andric for (uint32_t i = 0; i < k_num_pauth_register; i++) {
317fe6060f1SDimitry Andric pauth_regnum_collection.push_back(pa_regnum + i);
318fe6060f1SDimitry Andric m_dynamic_reg_infos.push_back(g_register_infos_pauth[i]);
319fe6060f1SDimitry Andric m_dynamic_reg_infos[pa_regnum + i].byte_offset =
320fe6060f1SDimitry Andric m_dynamic_reg_infos[pa_regnum + i - 1].byte_offset +
321fe6060f1SDimitry Andric m_dynamic_reg_infos[pa_regnum + i - 1].byte_size;
322fe6060f1SDimitry Andric m_dynamic_reg_infos[pa_regnum + i].kinds[lldb::eRegisterKindLLDB] =
323fe6060f1SDimitry Andric pa_regnum + i;
324fe6060f1SDimitry Andric }
325fe6060f1SDimitry Andric
326fe6060f1SDimitry Andric m_per_regset_regnum_range[m_register_set_count] =
327fe6060f1SDimitry Andric std::make_pair(pa_regnum, m_dynamic_reg_infos.size());
328fe6060f1SDimitry Andric m_dynamic_reg_sets.push_back(g_reg_set_pauth_arm64);
329fe6060f1SDimitry Andric m_dynamic_reg_sets.back().registers = pauth_regnum_collection.data();
330fe6060f1SDimitry Andric }
331fe6060f1SDimitry Andric
AddRegSetMTE()332fe6060f1SDimitry Andric void RegisterInfoPOSIX_arm64::AddRegSetMTE() {
333fe6060f1SDimitry Andric uint32_t mte_regnum = m_dynamic_reg_infos.size();
334fe6060f1SDimitry Andric m_mte_regnum_collection.push_back(mte_regnum);
335fe6060f1SDimitry Andric m_dynamic_reg_infos.push_back(g_register_infos_mte[0]);
336fe6060f1SDimitry Andric m_dynamic_reg_infos[mte_regnum].byte_offset =
337fe6060f1SDimitry Andric m_dynamic_reg_infos[mte_regnum - 1].byte_offset +
338fe6060f1SDimitry Andric m_dynamic_reg_infos[mte_regnum - 1].byte_size;
339fe6060f1SDimitry Andric m_dynamic_reg_infos[mte_regnum].kinds[lldb::eRegisterKindLLDB] = mte_regnum;
340fe6060f1SDimitry Andric
341fe6060f1SDimitry Andric m_per_regset_regnum_range[m_register_set_count] =
342fe6060f1SDimitry Andric std::make_pair(mte_regnum, mte_regnum + 1);
343fe6060f1SDimitry Andric m_dynamic_reg_sets.push_back(g_reg_set_mte_arm64);
344fe6060f1SDimitry Andric m_dynamic_reg_sets.back().registers = m_mte_regnum_collection.data();
345fe6060f1SDimitry Andric }
346fe6060f1SDimitry Andric
AddRegSetTLS(bool has_tpidr2)3475f757f3fSDimitry Andric void RegisterInfoPOSIX_arm64::AddRegSetTLS(bool has_tpidr2) {
34806c3fb27SDimitry Andric uint32_t tls_regnum = m_dynamic_reg_infos.size();
3495f757f3fSDimitry Andric uint32_t num_regs = has_tpidr2 ? 2 : 1;
3505f757f3fSDimitry Andric for (uint32_t i = 0; i < num_regs; i++) {
3515f757f3fSDimitry Andric m_tls_regnum_collection.push_back(tls_regnum + i);
3525f757f3fSDimitry Andric m_dynamic_reg_infos.push_back(g_register_infos_tls[i]);
3535f757f3fSDimitry Andric m_dynamic_reg_infos[tls_regnum + i].byte_offset =
3545f757f3fSDimitry Andric m_dynamic_reg_infos[tls_regnum + i - 1].byte_offset +
3555f757f3fSDimitry Andric m_dynamic_reg_infos[tls_regnum + i - 1].byte_size;
3565f757f3fSDimitry Andric m_dynamic_reg_infos[tls_regnum + i].kinds[lldb::eRegisterKindLLDB] =
3575f757f3fSDimitry Andric tls_regnum + i;
3585f757f3fSDimitry Andric }
35906c3fb27SDimitry Andric
36006c3fb27SDimitry Andric m_per_regset_regnum_range[m_register_set_count] =
3615f757f3fSDimitry Andric std::make_pair(tls_regnum, m_dynamic_reg_infos.size());
3625f757f3fSDimitry Andric m_dynamic_reg_sets.push_back(
3635f757f3fSDimitry Andric {"Thread Local Storage Registers", "tls", num_regs, nullptr});
36406c3fb27SDimitry Andric m_dynamic_reg_sets.back().registers = m_tls_regnum_collection.data();
36506c3fb27SDimitry Andric }
36606c3fb27SDimitry Andric
AddRegSetSME(bool has_zt)3675f757f3fSDimitry Andric void RegisterInfoPOSIX_arm64::AddRegSetSME(bool has_zt) {
3685f757f3fSDimitry Andric const uint32_t first_sme_regnum = m_dynamic_reg_infos.size();
3695f757f3fSDimitry Andric uint32_t sme_regnum = first_sme_regnum;
3705f757f3fSDimitry Andric
3715f757f3fSDimitry Andric for (uint32_t i = 0; i < k_num_sme_register; ++i, ++sme_regnum) {
3725f757f3fSDimitry Andric m_sme_regnum_collection.push_back(sme_regnum);
3735f757f3fSDimitry Andric m_dynamic_reg_infos.push_back(g_register_infos_sme[i]);
3745f757f3fSDimitry Andric m_dynamic_reg_infos[sme_regnum].byte_offset =
3755f757f3fSDimitry Andric m_dynamic_reg_infos[sme_regnum - 1].byte_offset +
3765f757f3fSDimitry Andric m_dynamic_reg_infos[sme_regnum - 1].byte_size;
3775f757f3fSDimitry Andric m_dynamic_reg_infos[sme_regnum].kinds[lldb::eRegisterKindLLDB] = sme_regnum;
3785f757f3fSDimitry Andric }
3795f757f3fSDimitry Andric
3805f757f3fSDimitry Andric lldb_private::RegisterSet sme_regset = g_reg_set_sme_arm64;
3815f757f3fSDimitry Andric
3825f757f3fSDimitry Andric if (has_zt) {
3835f757f3fSDimitry Andric m_sme_regnum_collection.push_back(sme_regnum);
3845f757f3fSDimitry Andric m_dynamic_reg_infos.push_back(g_register_infos_sme2[0]);
3855f757f3fSDimitry Andric m_dynamic_reg_infos[sme_regnum].byte_offset =
3865f757f3fSDimitry Andric m_dynamic_reg_infos[sme_regnum - 1].byte_offset +
3875f757f3fSDimitry Andric m_dynamic_reg_infos[sme_regnum - 1].byte_size;
3885f757f3fSDimitry Andric m_dynamic_reg_infos[sme_regnum].kinds[lldb::eRegisterKindLLDB] = sme_regnum;
3895f757f3fSDimitry Andric
3905f757f3fSDimitry Andric sme_regset.num_registers += 1;
3915f757f3fSDimitry Andric }
3925f757f3fSDimitry Andric
3935f757f3fSDimitry Andric m_per_regset_regnum_range[m_register_set_count] =
3945f757f3fSDimitry Andric std::make_pair(first_sme_regnum, m_dynamic_reg_infos.size());
3955f757f3fSDimitry Andric m_dynamic_reg_sets.push_back(sme_regset);
3965f757f3fSDimitry Andric m_dynamic_reg_sets.back().registers = m_sme_regnum_collection.data();
3975f757f3fSDimitry Andric
3985f757f3fSDimitry Andric // When vg is written during streaming mode, svg will also change, as vg and
3995f757f3fSDimitry Andric // svg in this state are both showing the streaming vector length.
4005f757f3fSDimitry Andric // We model this as vg invalidating svg. In non-streaming mode this doesn't
4015f757f3fSDimitry Andric // happen but to keep things simple we will invalidate svg anyway.
4025f757f3fSDimitry Andric //
4035f757f3fSDimitry Andric // This must be added now, rather than when vg is defined because SME is a
4045f757f3fSDimitry Andric // dynamic set that may or may not be present.
4055f757f3fSDimitry Andric static uint32_t vg_invalidates[] = {sme_regnum + 1 /*svg*/,
4065f757f3fSDimitry Andric LLDB_INVALID_REGNUM};
4075f757f3fSDimitry Andric m_dynamic_reg_infos[GetRegNumSVEVG()].invalidate_regs = vg_invalidates;
4085f757f3fSDimitry Andric }
4095f757f3fSDimitry Andric
ConfigureVectorLengthSVE(uint32_t sve_vq)4105f757f3fSDimitry Andric uint32_t RegisterInfoPOSIX_arm64::ConfigureVectorLengthSVE(uint32_t sve_vq) {
411e8d8bef9SDimitry Andric // sve_vq contains SVE Quad vector length in context of AArch64 SVE.
412e8d8bef9SDimitry Andric // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0.
413e8d8bef9SDimitry Andric // Also if an invalid or previously set vector length is passed to this
414e8d8bef9SDimitry Andric // function then it will exit immediately with previously set vector length.
415e8d8bef9SDimitry Andric if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq)
416e8d8bef9SDimitry Andric return m_vector_reg_vq;
417e8d8bef9SDimitry Andric
418e8d8bef9SDimitry Andric // We cannot enable AArch64 only mode if SVE was enabled.
419e8d8bef9SDimitry Andric if (sve_vq == eVectorQuadwordAArch64 &&
420e8d8bef9SDimitry Andric m_vector_reg_vq > eVectorQuadwordAArch64)
421e8d8bef9SDimitry Andric sve_vq = eVectorQuadwordAArch64SVE;
422e8d8bef9SDimitry Andric
423e8d8bef9SDimitry Andric m_vector_reg_vq = sve_vq;
424e8d8bef9SDimitry Andric
425fe6060f1SDimitry Andric if (sve_vq == eVectorQuadwordAArch64)
426e8d8bef9SDimitry Andric return m_vector_reg_vq;
427e8d8bef9SDimitry Andric std::vector<lldb_private::RegisterInfo> ®_info_ref =
428e8d8bef9SDimitry Andric m_per_vq_reg_infos[sve_vq];
429e8d8bef9SDimitry Andric
430e8d8bef9SDimitry Andric if (reg_info_ref.empty()) {
431bdd1243dSDimitry Andric reg_info_ref = llvm::ArrayRef(m_register_info_p, m_register_info_count);
432e8d8bef9SDimitry Andric
433e8d8bef9SDimitry Andric uint32_t offset = SVE_REGS_DEFAULT_OFFSET_LINUX;
434e8d8bef9SDimitry Andric reg_info_ref[fpu_fpsr].byte_offset = offset;
435e8d8bef9SDimitry Andric reg_info_ref[fpu_fpcr].byte_offset = offset + 4;
436e8d8bef9SDimitry Andric reg_info_ref[sve_vg].byte_offset = offset + 8;
437e8d8bef9SDimitry Andric offset += 16;
438e8d8bef9SDimitry Andric
439e8d8bef9SDimitry Andric // Update Z registers size and offset
440e8d8bef9SDimitry Andric uint32_t s_reg_base = fpu_s0;
441e8d8bef9SDimitry Andric uint32_t d_reg_base = fpu_d0;
442e8d8bef9SDimitry Andric uint32_t v_reg_base = fpu_v0;
443e8d8bef9SDimitry Andric uint32_t z_reg_base = sve_z0;
444e8d8bef9SDimitry Andric
445e8d8bef9SDimitry Andric for (uint32_t index = 0; index < 32; index++) {
446e8d8bef9SDimitry Andric reg_info_ref[s_reg_base + index].byte_offset = offset;
447e8d8bef9SDimitry Andric reg_info_ref[d_reg_base + index].byte_offset = offset;
448e8d8bef9SDimitry Andric reg_info_ref[v_reg_base + index].byte_offset = offset;
449e8d8bef9SDimitry Andric reg_info_ref[z_reg_base + index].byte_offset = offset;
450e8d8bef9SDimitry Andric
451e8d8bef9SDimitry Andric reg_info_ref[z_reg_base + index].byte_size = sve_vq * SVE_QUAD_WORD_BYTES;
452e8d8bef9SDimitry Andric offset += reg_info_ref[z_reg_base + index].byte_size;
453e8d8bef9SDimitry Andric }
454e8d8bef9SDimitry Andric
455e8d8bef9SDimitry Andric // Update P registers and FFR size and offset
456e8d8bef9SDimitry Andric for (uint32_t it = sve_p0; it <= sve_ffr; it++) {
457e8d8bef9SDimitry Andric reg_info_ref[it].byte_offset = offset;
458e8d8bef9SDimitry Andric reg_info_ref[it].byte_size = sve_vq * SVE_QUAD_WORD_BYTES / 8;
459e8d8bef9SDimitry Andric offset += reg_info_ref[it].byte_size;
460e8d8bef9SDimitry Andric }
461e8d8bef9SDimitry Andric
462fe6060f1SDimitry Andric for (uint32_t it = sve_ffr + 1; it < m_register_info_count; it++) {
463fe6060f1SDimitry Andric reg_info_ref[it].byte_offset = offset;
464fe6060f1SDimitry Andric offset += reg_info_ref[it].byte_size;
465fe6060f1SDimitry Andric }
466fe6060f1SDimitry Andric
467e8d8bef9SDimitry Andric m_per_vq_reg_infos[sve_vq] = reg_info_ref;
468e8d8bef9SDimitry Andric }
469e8d8bef9SDimitry Andric
470fe6060f1SDimitry Andric m_register_info_p = m_per_vq_reg_infos[sve_vq].data();
471e8d8bef9SDimitry Andric return m_vector_reg_vq;
472e8d8bef9SDimitry Andric }
473e8d8bef9SDimitry Andric
ConfigureVectorLengthZA(uint32_t za_vq)4745f757f3fSDimitry Andric void RegisterInfoPOSIX_arm64::ConfigureVectorLengthZA(uint32_t za_vq) {
4755f757f3fSDimitry Andric if (!VectorSizeIsValid(za_vq) || m_za_reg_vq == za_vq)
4765f757f3fSDimitry Andric return;
4775f757f3fSDimitry Andric
4785f757f3fSDimitry Andric m_za_reg_vq = za_vq;
4795f757f3fSDimitry Andric
4805f757f3fSDimitry Andric // For SVE changes, we replace m_register_info_p completely. ZA is in a
4815f757f3fSDimitry Andric // dynamic set and is just 1 register so we make an exception to const here.
4825f757f3fSDimitry Andric lldb_private::RegisterInfo *non_const_reginfo =
4835f757f3fSDimitry Andric const_cast<lldb_private::RegisterInfo *>(m_register_info_p);
4845f757f3fSDimitry Andric non_const_reginfo[m_sme_regnum_collection[2]].byte_size =
4855f757f3fSDimitry Andric (za_vq * 16) * (za_vq * 16);
4865f757f3fSDimitry Andric }
4875f757f3fSDimitry Andric
IsSVEReg(unsigned reg) const488fe6060f1SDimitry Andric bool RegisterInfoPOSIX_arm64::IsSVEReg(unsigned reg) const {
489fe6060f1SDimitry Andric if (m_vector_reg_vq > eVectorQuadwordAArch64)
490fe6060f1SDimitry Andric return (sve_vg <= reg && reg <= sve_ffr);
491fe6060f1SDimitry Andric else
492fe6060f1SDimitry Andric return false;
493fe6060f1SDimitry Andric }
494fe6060f1SDimitry Andric
IsSVEZReg(unsigned reg) const495e8d8bef9SDimitry Andric bool RegisterInfoPOSIX_arm64::IsSVEZReg(unsigned reg) const {
496e8d8bef9SDimitry Andric return (sve_z0 <= reg && reg <= sve_z31);
497e8d8bef9SDimitry Andric }
498e8d8bef9SDimitry Andric
IsSVEPReg(unsigned reg) const499e8d8bef9SDimitry Andric bool RegisterInfoPOSIX_arm64::IsSVEPReg(unsigned reg) const {
500e8d8bef9SDimitry Andric return (sve_p0 <= reg && reg <= sve_p15);
501e8d8bef9SDimitry Andric }
502e8d8bef9SDimitry Andric
IsSVERegVG(unsigned reg) const503e8d8bef9SDimitry Andric bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const {
504e8d8bef9SDimitry Andric return sve_vg == reg;
505e8d8bef9SDimitry Andric }
506e8d8bef9SDimitry Andric
IsSMERegZA(unsigned reg) const5075f757f3fSDimitry Andric bool RegisterInfoPOSIX_arm64::IsSMERegZA(unsigned reg) const {
5085f757f3fSDimitry Andric return reg == m_sme_regnum_collection[2];
5095f757f3fSDimitry Andric }
5105f757f3fSDimitry Andric
IsSMERegZT(unsigned reg) const5115f757f3fSDimitry Andric bool RegisterInfoPOSIX_arm64::IsSMERegZT(unsigned reg) const {
5125f757f3fSDimitry Andric // ZT0 is part of the SME register set only if SME2 is present.
5135f757f3fSDimitry Andric return m_sme_regnum_collection.size() >= 4 &&
5145f757f3fSDimitry Andric reg == m_sme_regnum_collection[3];
5155f757f3fSDimitry Andric }
5165f757f3fSDimitry Andric
IsPAuthReg(unsigned reg) const517fe6060f1SDimitry Andric bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
518fcaf7f86SDimitry Andric return llvm::is_contained(pauth_regnum_collection, reg);
519fe6060f1SDimitry Andric }
520fe6060f1SDimitry Andric
IsMTEReg(unsigned reg) const521fe6060f1SDimitry Andric bool RegisterInfoPOSIX_arm64::IsMTEReg(unsigned reg) const {
522fcaf7f86SDimitry Andric return llvm::is_contained(m_mte_regnum_collection, reg);
523fe6060f1SDimitry Andric }
524fe6060f1SDimitry Andric
IsTLSReg(unsigned reg) const52506c3fb27SDimitry Andric bool RegisterInfoPOSIX_arm64::IsTLSReg(unsigned reg) const {
52606c3fb27SDimitry Andric return llvm::is_contained(m_tls_regnum_collection, reg);
52706c3fb27SDimitry Andric }
52806c3fb27SDimitry Andric
IsSMEReg(unsigned reg) const5295f757f3fSDimitry Andric bool RegisterInfoPOSIX_arm64::IsSMEReg(unsigned reg) const {
5305f757f3fSDimitry Andric return llvm::is_contained(m_sme_regnum_collection, reg);
5315f757f3fSDimitry Andric }
5325f757f3fSDimitry Andric
GetRegNumSVEZ0() const533e8d8bef9SDimitry Andric uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; }
534e8d8bef9SDimitry Andric
GetRegNumSVEFFR() const535e8d8bef9SDimitry Andric uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
536e8d8bef9SDimitry Andric
GetRegNumFPCR() const537e8d8bef9SDimitry Andric uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
538e8d8bef9SDimitry Andric
GetRegNumFPSR() const539e8d8bef9SDimitry Andric uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
540e8d8bef9SDimitry Andric
GetRegNumSVEVG() const541e8d8bef9SDimitry Andric uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
542fe6060f1SDimitry Andric
GetRegNumSMESVG() const5435f757f3fSDimitry Andric uint32_t RegisterInfoPOSIX_arm64::GetRegNumSMESVG() const {
5445f757f3fSDimitry Andric return m_sme_regnum_collection[1];
5455f757f3fSDimitry Andric }
5465f757f3fSDimitry Andric
GetPAuthOffset() const547fe6060f1SDimitry Andric uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
548fe6060f1SDimitry Andric return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
549fe6060f1SDimitry Andric }
550fe6060f1SDimitry Andric
GetMTEOffset() const551fe6060f1SDimitry Andric uint32_t RegisterInfoPOSIX_arm64::GetMTEOffset() const {
552fe6060f1SDimitry Andric return m_register_info_p[m_mte_regnum_collection[0]].byte_offset;
553fe6060f1SDimitry Andric }
55406c3fb27SDimitry Andric
GetTLSOffset() const55506c3fb27SDimitry Andric uint32_t RegisterInfoPOSIX_arm64::GetTLSOffset() const {
55606c3fb27SDimitry Andric return m_register_info_p[m_tls_regnum_collection[0]].byte_offset;
55706c3fb27SDimitry Andric }
5585f757f3fSDimitry Andric
GetSMEOffset() const5595f757f3fSDimitry Andric uint32_t RegisterInfoPOSIX_arm64::GetSMEOffset() const {
5605f757f3fSDimitry Andric return m_register_info_p[m_sme_regnum_collection[0]].byte_offset;
5615f757f3fSDimitry Andric }
562