1 //===-- RegisterInfoPOSIX_arm64.cpp ---------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===---------------------------------------------------------------------===// 8 9 #include <cassert> 10 #include <stddef.h> 11 #include <vector> 12 13 #include "lldb/lldb-defines.h" 14 #include "llvm/Support/Compiler.h" 15 16 #include "RegisterInfoPOSIX_arm64.h" 17 18 // Based on RegisterContextDarwin_arm64.cpp 19 #define GPR_OFFSET(idx) ((idx)*8) 20 #define GPR_OFFSET_NAME(reg) \ 21 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg)) 22 23 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR)) 24 #define FPU_OFFSET_NAME(reg) \ 25 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \ 26 sizeof(RegisterInfoPOSIX_arm64::GPR)) 27 28 // This information is based on AArch64 with SVE architecture reference manual. 29 // AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR 30 // (First Fault) register and a VG (Vector Granule) pseudo register. 31 32 // SVE 16-byte quad word is the basic unit of expansion in vector length. 33 #define SVE_QUAD_WORD_BYTES 16 34 35 // Vector length is the multiplier which decides the no of quad words, 36 // (multiples of 128-bits or 16-bytes) present in a Z register. Vector length 37 // is decided during execution and can change at runtime. SVE AArch64 register 38 // infos have modes one for each valid value of vector length. A change in 39 // vector length requires register context to update sizes of SVE Z, P and FFR. 40 // Also register context needs to update byte offsets of all registers affected 41 // by the change in vector length. 42 #define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoPOSIX_arm64::GPR) 43 44 #define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX 45 46 #define EXC_OFFSET_NAME(reg) \ 47 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) + \ 48 sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 49 sizeof(RegisterInfoPOSIX_arm64::FPU)) 50 #define DBG_OFFSET_NAME(reg) \ 51 (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) + \ 52 sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 53 sizeof(RegisterInfoPOSIX_arm64::FPU) + \ 54 sizeof(RegisterInfoPOSIX_arm64::EXC)) 55 56 #define DEFINE_DBG(reg, i) \ 57 #reg, NULL, \ 58 sizeof(((RegisterInfoPOSIX_arm64::DBG *) NULL)->reg[i]), \ 59 DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \ 60 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 61 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 62 dbg_##reg##i }, \ 63 NULL, NULL, NULL, 0 64 #define REG_CONTEXT_SIZE \ 65 (sizeof(RegisterInfoPOSIX_arm64::GPR) + \ 66 sizeof(RegisterInfoPOSIX_arm64::FPU) + \ 67 sizeof(RegisterInfoPOSIX_arm64::EXC)) 68 69 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure. 70 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 71 #include "RegisterInfos_arm64.h" 72 #include "RegisterInfos_arm64_sve.h" 73 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT 74 75 static const lldb_private::RegisterInfo * 76 GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) { 77 switch (target_arch.GetMachine()) { 78 case llvm::Triple::aarch64: 79 case llvm::Triple::aarch64_32: 80 return g_register_infos_arm64_le; 81 default: 82 assert(false && "Unhandled target architecture."); 83 return nullptr; 84 } 85 } 86 87 // Number of register sets provided by this context. 88 enum { 89 k_num_gpr_registers = gpr_w28 - gpr_x0 + 1, 90 k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1, 91 k_num_sve_registers = sve_ffr - sve_vg + 1, 92 k_num_register_sets = 3 93 }; 94 95 // ARM64 general purpose registers. 96 static const uint32_t g_gpr_regnums_arm64[] = { 97 gpr_x0, gpr_x1, gpr_x2, gpr_x3, 98 gpr_x4, gpr_x5, gpr_x6, gpr_x7, 99 gpr_x8, gpr_x9, gpr_x10, gpr_x11, 100 gpr_x12, gpr_x13, gpr_x14, gpr_x15, 101 gpr_x16, gpr_x17, gpr_x18, gpr_x19, 102 gpr_x20, gpr_x21, gpr_x22, gpr_x23, 103 gpr_x24, gpr_x25, gpr_x26, gpr_x27, 104 gpr_x28, gpr_fp, gpr_lr, gpr_sp, 105 gpr_pc, gpr_cpsr, gpr_w0, gpr_w1, 106 gpr_w2, gpr_w3, gpr_w4, gpr_w5, 107 gpr_w6, gpr_w7, gpr_w8, gpr_w9, 108 gpr_w10, gpr_w11, gpr_w12, gpr_w13, 109 gpr_w14, gpr_w15, gpr_w16, gpr_w17, 110 gpr_w18, gpr_w19, gpr_w20, gpr_w21, 111 gpr_w22, gpr_w23, gpr_w24, gpr_w25, 112 gpr_w26, gpr_w27, gpr_w28, LLDB_INVALID_REGNUM}; 113 114 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) - 115 1) == k_num_gpr_registers, 116 "g_gpr_regnums_arm64 has wrong number of register infos"); 117 118 // ARM64 floating point registers. 119 static const uint32_t g_fpu_regnums_arm64[] = { 120 fpu_v0, fpu_v1, fpu_v2, 121 fpu_v3, fpu_v4, fpu_v5, 122 fpu_v6, fpu_v7, fpu_v8, 123 fpu_v9, fpu_v10, fpu_v11, 124 fpu_v12, fpu_v13, fpu_v14, 125 fpu_v15, fpu_v16, fpu_v17, 126 fpu_v18, fpu_v19, fpu_v20, 127 fpu_v21, fpu_v22, fpu_v23, 128 fpu_v24, fpu_v25, fpu_v26, 129 fpu_v27, fpu_v28, fpu_v29, 130 fpu_v30, fpu_v31, fpu_s0, 131 fpu_s1, fpu_s2, fpu_s3, 132 fpu_s4, fpu_s5, fpu_s6, 133 fpu_s7, fpu_s8, fpu_s9, 134 fpu_s10, fpu_s11, fpu_s12, 135 fpu_s13, fpu_s14, fpu_s15, 136 fpu_s16, fpu_s17, fpu_s18, 137 fpu_s19, fpu_s20, fpu_s21, 138 fpu_s22, fpu_s23, fpu_s24, 139 fpu_s25, fpu_s26, fpu_s27, 140 fpu_s28, fpu_s29, fpu_s30, 141 fpu_s31, fpu_d0, fpu_d1, 142 fpu_d2, fpu_d3, fpu_d4, 143 fpu_d5, fpu_d6, fpu_d7, 144 fpu_d8, fpu_d9, fpu_d10, 145 fpu_d11, fpu_d12, fpu_d13, 146 fpu_d14, fpu_d15, fpu_d16, 147 fpu_d17, fpu_d18, fpu_d19, 148 fpu_d20, fpu_d21, fpu_d22, 149 fpu_d23, fpu_d24, fpu_d25, 150 fpu_d26, fpu_d27, fpu_d28, 151 fpu_d29, fpu_d30, fpu_d31, 152 fpu_fpsr, fpu_fpcr, LLDB_INVALID_REGNUM}; 153 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) - 154 1) == k_num_fpr_registers, 155 "g_fpu_regnums_arm64 has wrong number of register infos"); 156 157 // ARM64 SVE registers. 158 static const uint32_t g_sve_regnums_arm64[] = { 159 sve_vg, sve_z0, sve_z1, 160 sve_z2, sve_z3, sve_z4, 161 sve_z5, sve_z6, sve_z7, 162 sve_z8, sve_z9, sve_z10, 163 sve_z11, sve_z12, sve_z13, 164 sve_z14, sve_z15, sve_z16, 165 sve_z17, sve_z18, sve_z19, 166 sve_z20, sve_z21, sve_z22, 167 sve_z23, sve_z24, sve_z25, 168 sve_z26, sve_z27, sve_z28, 169 sve_z29, sve_z30, sve_z31, 170 sve_p0, sve_p1, sve_p2, 171 sve_p3, sve_p4, sve_p5, 172 sve_p6, sve_p7, sve_p8, 173 sve_p9, sve_p10, sve_p11, 174 sve_p12, sve_p13, sve_p14, 175 sve_p15, sve_ffr, LLDB_INVALID_REGNUM}; 176 static_assert(((sizeof g_sve_regnums_arm64 / sizeof g_sve_regnums_arm64[0]) - 177 1) == k_num_sve_registers, 178 "g_sve_regnums_arm64 has wrong number of register infos"); 179 180 // Register sets for ARM64. 181 static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = { 182 {"General Purpose Registers", "gpr", k_num_gpr_registers, 183 g_gpr_regnums_arm64}, 184 {"Floating Point Registers", "fpu", k_num_fpr_registers, 185 g_fpu_regnums_arm64}, 186 {"Scalable Vector Extension Registers", "sve", k_num_sve_registers, 187 g_sve_regnums_arm64}}; 188 189 static uint32_t 190 GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) { 191 switch (target_arch.GetMachine()) { 192 case llvm::Triple::aarch64: 193 case llvm::Triple::aarch64_32: 194 return static_cast<uint32_t>(sizeof(g_register_infos_arm64_le) / 195 sizeof(g_register_infos_arm64_le[0])); 196 default: 197 assert(false && "Unhandled target architecture."); 198 return 0; 199 } 200 } 201 202 RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64( 203 const lldb_private::ArchSpec &target_arch) 204 : lldb_private::RegisterInfoAndSetInterface(target_arch), 205 m_register_info_p(GetRegisterInfoPtr(target_arch)), 206 m_register_info_count(GetRegisterInfoCount(target_arch)) { 207 } 208 209 uint32_t RegisterInfoPOSIX_arm64::GetRegisterCount() const { 210 if (IsSVEEnabled()) 211 return k_num_gpr_registers + k_num_fpr_registers + k_num_sve_registers; 212 213 return k_num_gpr_registers + k_num_fpr_registers; 214 } 215 216 size_t RegisterInfoPOSIX_arm64::GetGPRSize() const { 217 return sizeof(struct RegisterInfoPOSIX_arm64::GPR); 218 } 219 220 size_t RegisterInfoPOSIX_arm64::GetFPRSize() const { 221 return sizeof(struct RegisterInfoPOSIX_arm64::FPU); 222 } 223 224 const lldb_private::RegisterInfo * 225 RegisterInfoPOSIX_arm64::GetRegisterInfo() const { 226 return m_register_info_p; 227 } 228 229 size_t RegisterInfoPOSIX_arm64::GetRegisterSetCount() const { 230 if (IsSVEEnabled()) 231 return k_num_register_sets; 232 return k_num_register_sets - 1; 233 } 234 235 size_t RegisterInfoPOSIX_arm64::GetRegisterSetFromRegisterIndex( 236 uint32_t reg_index) const { 237 if (reg_index <= gpr_w28) 238 return GPRegSet; 239 if (reg_index <= fpu_fpcr) 240 return FPRegSet; 241 if (reg_index <= sve_ffr) 242 return SVERegSet; 243 return LLDB_INVALID_REGNUM; 244 } 245 246 const lldb_private::RegisterSet * 247 RegisterInfoPOSIX_arm64::GetRegisterSet(size_t set_index) const { 248 if (set_index < GetRegisterSetCount()) 249 return &g_reg_sets_arm64[set_index]; 250 return nullptr; 251 } 252 253 uint32_t 254 RegisterInfoPOSIX_arm64::ConfigureVectorRegisterInfos(uint32_t sve_vq) { 255 // sve_vq contains SVE Quad vector length in context of AArch64 SVE. 256 // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0. 257 // Also if an invalid or previously set vector length is passed to this 258 // function then it will exit immediately with previously set vector length. 259 if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq) 260 return m_vector_reg_vq; 261 262 // We cannot enable AArch64 only mode if SVE was enabled. 263 if (sve_vq == eVectorQuadwordAArch64 && 264 m_vector_reg_vq > eVectorQuadwordAArch64) 265 sve_vq = eVectorQuadwordAArch64SVE; 266 267 m_vector_reg_vq = sve_vq; 268 269 if (sve_vq == eVectorQuadwordAArch64) { 270 m_register_info_count = 271 static_cast<uint32_t>(sizeof(g_register_infos_arm64_le) / 272 sizeof(g_register_infos_arm64_le[0])); 273 m_register_info_p = g_register_infos_arm64_le; 274 275 return m_vector_reg_vq; 276 } 277 278 m_register_info_count = 279 static_cast<uint32_t>(sizeof(g_register_infos_arm64_sve_le) / 280 sizeof(g_register_infos_arm64_sve_le[0])); 281 282 std::vector<lldb_private::RegisterInfo> ®_info_ref = 283 m_per_vq_reg_infos[sve_vq]; 284 285 if (reg_info_ref.empty()) { 286 reg_info_ref = llvm::makeArrayRef(g_register_infos_arm64_sve_le, 287 m_register_info_count); 288 289 uint32_t offset = SVE_REGS_DEFAULT_OFFSET_LINUX; 290 291 reg_info_ref[fpu_fpsr].byte_offset = offset; 292 reg_info_ref[fpu_fpcr].byte_offset = offset + 4; 293 reg_info_ref[sve_vg].byte_offset = offset + 8; 294 offset += 16; 295 296 // Update Z registers size and offset 297 uint32_t s_reg_base = fpu_s0; 298 uint32_t d_reg_base = fpu_d0; 299 uint32_t v_reg_base = fpu_v0; 300 uint32_t z_reg_base = sve_z0; 301 302 for (uint32_t index = 0; index < 32; index++) { 303 reg_info_ref[s_reg_base + index].byte_offset = offset; 304 reg_info_ref[d_reg_base + index].byte_offset = offset; 305 reg_info_ref[v_reg_base + index].byte_offset = offset; 306 reg_info_ref[z_reg_base + index].byte_offset = offset; 307 308 reg_info_ref[z_reg_base + index].byte_size = sve_vq * SVE_QUAD_WORD_BYTES; 309 offset += reg_info_ref[z_reg_base + index].byte_size; 310 } 311 312 // Update P registers and FFR size and offset 313 for (uint32_t it = sve_p0; it <= sve_ffr; it++) { 314 reg_info_ref[it].byte_offset = offset; 315 reg_info_ref[it].byte_size = sve_vq * SVE_QUAD_WORD_BYTES / 8; 316 offset += reg_info_ref[it].byte_size; 317 } 318 319 m_per_vq_reg_infos[sve_vq] = reg_info_ref; 320 } 321 322 m_register_info_p = reg_info_ref.data(); 323 return m_vector_reg_vq; 324 } 325 326 bool RegisterInfoPOSIX_arm64::IsSVEZReg(unsigned reg) const { 327 return (sve_z0 <= reg && reg <= sve_z31); 328 } 329 330 bool RegisterInfoPOSIX_arm64::IsSVEPReg(unsigned reg) const { 331 return (sve_p0 <= reg && reg <= sve_p15); 332 } 333 334 bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const { 335 return sve_vg == reg; 336 } 337 338 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; } 339 340 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; } 341 342 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; } 343 344 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; } 345 346 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; } 347