1 //===-- RegisterInfoPOSIX_arm64.h -------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H
10 #define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H
11 
12 #include "RegisterInfoAndSetInterface.h"
13 #include "lldb/Target/RegisterContext.h"
14 #include "lldb/Utility/Flags.h"
15 #include "lldb/lldb-private.h"
16 #include <map>
17 
18 enum class SVEState { Unknown, Disabled, FPSIMD, Full };
19 
20 class RegisterInfoPOSIX_arm64
21     : public lldb_private::RegisterInfoAndSetInterface {
22 public:
23   enum { GPRegSet = 0, FPRegSet };
24 
25   // AArch64 register set mask value
26   enum {
27     eRegsetMaskDefault = 0,
28     eRegsetMaskSVE = 1,
29     eRegsetMaskPAuth = 2,
30     eRegsetMaskMTE = 4,
31     eRegsetMaskDynamic = ~1,
32   };
33 
34   // AArch64 Register set FP/SIMD feature configuration
35   enum {
36     eVectorQuadwordAArch64,
37     eVectorQuadwordAArch64SVE,
38     eVectorQuadwordAArch64SVEMax = 256
39   };
40 
41   // based on RegisterContextDarwin_arm64.h
42   LLVM_PACKED_START
43   struct GPR {
44     uint64_t x[29]; // x0-x28
45     uint64_t fp;    // x29
46     uint64_t lr;    // x30
47     uint64_t sp;    // x31
48     uint64_t pc;    // pc
49     uint32_t cpsr;  // cpsr
50   };
51   LLVM_PACKED_END
52 
53   // based on RegisterContextDarwin_arm64.h
54   struct VReg {
55     uint8_t bytes[16];
56   };
57 
58   // based on RegisterContextDarwin_arm64.h
59   struct FPU {
60     VReg v[32];
61     uint32_t fpsr;
62     uint32_t fpcr;
63   };
64 
65   // based on RegisterContextDarwin_arm64.h
66   struct EXC {
67     uint64_t far;       // Virtual Fault Address
68     uint32_t esr;       // Exception syndrome
69     uint32_t exception; // number of arm exception token
70   };
71 
72   // based on RegisterContextDarwin_arm64.h
73   struct DBG {
74     uint64_t bvr[16];
75     uint64_t bcr[16];
76     uint64_t wvr[16];
77     uint64_t wcr[16];
78     uint64_t mdscr_el1;
79   };
80 
81   RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec &target_arch,
82                           lldb_private::Flags opt_regsets);
83 
84   size_t GetGPRSize() const override;
85 
86   size_t GetFPRSize() const override;
87 
88   const lldb_private::RegisterInfo *GetRegisterInfo() const override;
89 
90   uint32_t GetRegisterCount() const override;
91 
92   const lldb_private::RegisterSet *
93   GetRegisterSet(size_t reg_set) const override;
94 
95   size_t GetRegisterSetCount() const override;
96 
97   size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
98 
99   void AddRegSetPAuth();
100 
101   void AddRegSetMTE();
102 
103   uint32_t ConfigureVectorLength(uint32_t sve_vq);
104 
105   bool VectorSizeIsValid(uint32_t vq) {
106     if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax)
107       return true;
108     return false;
109   }
110 
111   bool IsSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); }
112   bool IsPAuthEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); }
113   bool IsMTEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); }
114 
115   bool IsSVEReg(unsigned reg) const;
116   bool IsSVEZReg(unsigned reg) const;
117   bool IsSVEPReg(unsigned reg) const;
118   bool IsSVERegVG(unsigned reg) const;
119   bool IsPAuthReg(unsigned reg) const;
120   bool IsMTEReg(unsigned reg) const;
121 
122   uint32_t GetRegNumSVEZ0() const;
123   uint32_t GetRegNumSVEFFR() const;
124   uint32_t GetRegNumFPCR() const;
125   uint32_t GetRegNumFPSR() const;
126   uint32_t GetRegNumSVEVG() const;
127   uint32_t GetPAuthOffset() const;
128   uint32_t GetMTEOffset() const;
129 
130 private:
131   typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>>
132       per_vq_register_infos;
133 
134   per_vq_register_infos m_per_vq_reg_infos;
135 
136   uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
137 
138   const lldb_private::RegisterInfo *m_register_info_p;
139   uint32_t m_register_info_count;
140 
141   const lldb_private::RegisterSet *m_register_set_p;
142   uint32_t m_register_set_count;
143 
144   // Contains pair of [start, end] register numbers of a register set with start
145   // and end included.
146   std::map<uint32_t, std::pair<uint32_t, uint32_t>> m_per_regset_regnum_range;
147 
148   lldb_private::Flags m_opt_regsets;
149 
150   std::vector<lldb_private::RegisterInfo> m_dynamic_reg_infos;
151   std::vector<lldb_private::RegisterSet> m_dynamic_reg_sets;
152 
153   std::vector<uint32_t> pauth_regnum_collection;
154   std::vector<uint32_t> m_mte_regnum_collection;
155 };
156 
157 #endif
158