1 //===-- RegisterInfoPOSIX_arm64.h -------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H 10 #define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H 11 12 #include "RegisterInfoAndSetInterface.h" 13 #include "lldb/Target/RegisterContext.h" 14 #include "lldb/Utility/Flags.h" 15 #include "lldb/lldb-private.h" 16 #include <map> 17 18 enum class SVEState { Unknown, Disabled, FPSIMD, Full }; 19 20 class RegisterInfoPOSIX_arm64 21 : public lldb_private::RegisterInfoAndSetInterface { 22 public: 23 enum { GPRegSet = 0, FPRegSet }; 24 25 // AArch64 register set mask value 26 enum { 27 eRegsetMaskDefault = 0, 28 eRegsetMaskSVE = 1, 29 eRegsetMaskPAuth = 2, 30 eRegsetMaskMTE = 4, 31 eRegsetMaskTLS = 8, 32 eRegsetMaskDynamic = ~1, 33 }; 34 35 // AArch64 Register set FP/SIMD feature configuration 36 enum { 37 eVectorQuadwordAArch64, 38 eVectorQuadwordAArch64SVE, 39 eVectorQuadwordAArch64SVEMax = 256 40 }; 41 42 // based on RegisterContextDarwin_arm64.h 43 LLVM_PACKED_START 44 struct GPR { 45 uint64_t x[29]; // x0-x28 46 uint64_t fp; // x29 47 uint64_t lr; // x30 48 uint64_t sp; // x31 49 uint64_t pc; // pc 50 uint32_t cpsr; // cpsr 51 uint32_t pad; 52 }; 53 LLVM_PACKED_END 54 55 // based on RegisterContextDarwin_arm64.h 56 struct VReg { 57 uint8_t bytes[16]; 58 }; 59 60 // based on RegisterContextDarwin_arm64.h 61 struct FPU { 62 VReg v[32]; 63 uint32_t fpsr; 64 uint32_t fpcr; 65 }; 66 67 // based on RegisterContextDarwin_arm64.h 68 struct EXC { 69 uint64_t far; // Virtual Fault Address 70 uint32_t esr; // Exception syndrome 71 uint32_t exception; // number of arm exception token 72 }; 73 74 // based on RegisterContextDarwin_arm64.h 75 struct DBG { 76 uint64_t bvr[16]; 77 uint64_t bcr[16]; 78 uint64_t wvr[16]; 79 uint64_t wcr[16]; 80 uint64_t mdscr_el1; 81 }; 82 83 RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec &target_arch, 84 lldb_private::Flags opt_regsets); 85 86 static size_t GetGPRSizeStatic(); 87 size_t GetGPRSize() const override { return GetGPRSizeStatic(); } 88 89 size_t GetFPRSize() const override; 90 91 const lldb_private::RegisterInfo *GetRegisterInfo() const override; 92 93 uint32_t GetRegisterCount() const override; 94 95 const lldb_private::RegisterSet * 96 GetRegisterSet(size_t reg_set) const override; 97 98 size_t GetRegisterSetCount() const override; 99 100 size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override; 101 102 void AddRegSetPAuth(); 103 104 void AddRegSetMTE(); 105 106 void AddRegSetTLS(); 107 108 uint32_t ConfigureVectorLength(uint32_t sve_vq); 109 110 bool VectorSizeIsValid(uint32_t vq) { 111 // coverity[unsigned_compare] 112 if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax) 113 return true; 114 return false; 115 } 116 117 bool IsSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); } 118 bool IsPAuthEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); } 119 bool IsMTEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); } 120 bool IsTLSEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskTLS); } 121 122 bool IsSVEReg(unsigned reg) const; 123 bool IsSVEZReg(unsigned reg) const; 124 bool IsSVEPReg(unsigned reg) const; 125 bool IsSVERegVG(unsigned reg) const; 126 bool IsPAuthReg(unsigned reg) const; 127 bool IsMTEReg(unsigned reg) const; 128 bool IsTLSReg(unsigned reg) const; 129 130 uint32_t GetRegNumSVEZ0() const; 131 uint32_t GetRegNumSVEFFR() const; 132 uint32_t GetRegNumFPCR() const; 133 uint32_t GetRegNumFPSR() const; 134 uint32_t GetRegNumSVEVG() const; 135 uint32_t GetPAuthOffset() const; 136 uint32_t GetMTEOffset() const; 137 uint32_t GetTLSOffset() const; 138 139 private: 140 typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>> 141 per_vq_register_infos; 142 143 per_vq_register_infos m_per_vq_reg_infos; 144 145 uint32_t m_vector_reg_vq = eVectorQuadwordAArch64; 146 147 const lldb_private::RegisterInfo *m_register_info_p; 148 uint32_t m_register_info_count; 149 150 const lldb_private::RegisterSet *m_register_set_p; 151 uint32_t m_register_set_count; 152 153 // Contains pair of [start, end] register numbers of a register set with start 154 // and end included. 155 std::map<uint32_t, std::pair<uint32_t, uint32_t>> m_per_regset_regnum_range; 156 157 lldb_private::Flags m_opt_regsets; 158 159 std::vector<lldb_private::RegisterInfo> m_dynamic_reg_infos; 160 std::vector<lldb_private::RegisterSet> m_dynamic_reg_sets; 161 162 std::vector<uint32_t> pauth_regnum_collection; 163 std::vector<uint32_t> m_mte_regnum_collection; 164 std::vector<uint32_t> m_tls_regnum_collection; 165 }; 166 167 #endif 168