10b57cec5SDimitry Andric //===-- RegisterInfos_arm.h -------------------------------------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 90b57cec5SDimitry Andric #ifdef DECLARE_REGISTER_INFOS_ARM_STRUCT 100b57cec5SDimitry Andric 11fe6060f1SDimitry Andric #include <cstddef> 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #include "lldb/lldb-defines.h" 140b57cec5SDimitry Andric #include "lldb/lldb-enumerations.h" 150b57cec5SDimitry Andric #include "lldb/lldb-private.h" 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric #include "Utility/ARM_DWARF_Registers.h" 180b57cec5SDimitry Andric #include "Utility/ARM_ehframe_Registers.h" 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric using namespace lldb; 210b57cec5SDimitry Andric using namespace lldb_private; 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric #ifndef GPR_OFFSET 240b57cec5SDimitry Andric #error GPR_OFFSET must be defined before including this header file 250b57cec5SDimitry Andric #endif 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric #ifndef FPU_OFFSET 280b57cec5SDimitry Andric #error FPU_OFFSET must be defined before including this header file 290b57cec5SDimitry Andric #endif 300b57cec5SDimitry Andric 310b57cec5SDimitry Andric #ifndef FPSCR_OFFSET 320b57cec5SDimitry Andric #error FPSCR_OFFSET must be defined before including this header file 330b57cec5SDimitry Andric #endif 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric #ifndef EXC_OFFSET 360b57cec5SDimitry Andric #error EXC_OFFSET_NAME must be defined before including this header file 370b57cec5SDimitry Andric #endif 380b57cec5SDimitry Andric 390b57cec5SDimitry Andric #ifndef DEFINE_DBG 400b57cec5SDimitry Andric #error DEFINE_DBG must be defined before including this header file 410b57cec5SDimitry Andric #endif 420b57cec5SDimitry Andric 430b57cec5SDimitry Andric enum { 440b57cec5SDimitry Andric gpr_r0 = 0, 450b57cec5SDimitry Andric gpr_r1, 460b57cec5SDimitry Andric gpr_r2, 470b57cec5SDimitry Andric gpr_r3, 480b57cec5SDimitry Andric gpr_r4, 490b57cec5SDimitry Andric gpr_r5, 500b57cec5SDimitry Andric gpr_r6, 510b57cec5SDimitry Andric gpr_r7, 520b57cec5SDimitry Andric gpr_r8, 530b57cec5SDimitry Andric gpr_r9, 540b57cec5SDimitry Andric gpr_r10, 550b57cec5SDimitry Andric gpr_r11, 560b57cec5SDimitry Andric gpr_r12, 570b57cec5SDimitry Andric gpr_r13, 580b57cec5SDimitry Andric gpr_sp = gpr_r13, 590b57cec5SDimitry Andric gpr_r14, 600b57cec5SDimitry Andric gpr_lr = gpr_r14, 610b57cec5SDimitry Andric gpr_r15, 620b57cec5SDimitry Andric gpr_pc = gpr_r15, 630b57cec5SDimitry Andric gpr_cpsr, 640b57cec5SDimitry Andric 650b57cec5SDimitry Andric fpu_s0, 660b57cec5SDimitry Andric fpu_s1, 670b57cec5SDimitry Andric fpu_s2, 680b57cec5SDimitry Andric fpu_s3, 690b57cec5SDimitry Andric fpu_s4, 700b57cec5SDimitry Andric fpu_s5, 710b57cec5SDimitry Andric fpu_s6, 720b57cec5SDimitry Andric fpu_s7, 730b57cec5SDimitry Andric fpu_s8, 740b57cec5SDimitry Andric fpu_s9, 750b57cec5SDimitry Andric fpu_s10, 760b57cec5SDimitry Andric fpu_s11, 770b57cec5SDimitry Andric fpu_s12, 780b57cec5SDimitry Andric fpu_s13, 790b57cec5SDimitry Andric fpu_s14, 800b57cec5SDimitry Andric fpu_s15, 810b57cec5SDimitry Andric fpu_s16, 820b57cec5SDimitry Andric fpu_s17, 830b57cec5SDimitry Andric fpu_s18, 840b57cec5SDimitry Andric fpu_s19, 850b57cec5SDimitry Andric fpu_s20, 860b57cec5SDimitry Andric fpu_s21, 870b57cec5SDimitry Andric fpu_s22, 880b57cec5SDimitry Andric fpu_s23, 890b57cec5SDimitry Andric fpu_s24, 900b57cec5SDimitry Andric fpu_s25, 910b57cec5SDimitry Andric fpu_s26, 920b57cec5SDimitry Andric fpu_s27, 930b57cec5SDimitry Andric fpu_s28, 940b57cec5SDimitry Andric fpu_s29, 950b57cec5SDimitry Andric fpu_s30, 960b57cec5SDimitry Andric fpu_s31, 970b57cec5SDimitry Andric fpu_fpscr, 980b57cec5SDimitry Andric 990b57cec5SDimitry Andric fpu_d0, 1000b57cec5SDimitry Andric fpu_d1, 1010b57cec5SDimitry Andric fpu_d2, 1020b57cec5SDimitry Andric fpu_d3, 1030b57cec5SDimitry Andric fpu_d4, 1040b57cec5SDimitry Andric fpu_d5, 1050b57cec5SDimitry Andric fpu_d6, 1060b57cec5SDimitry Andric fpu_d7, 1070b57cec5SDimitry Andric fpu_d8, 1080b57cec5SDimitry Andric fpu_d9, 1090b57cec5SDimitry Andric fpu_d10, 1100b57cec5SDimitry Andric fpu_d11, 1110b57cec5SDimitry Andric fpu_d12, 1120b57cec5SDimitry Andric fpu_d13, 1130b57cec5SDimitry Andric fpu_d14, 1140b57cec5SDimitry Andric fpu_d15, 1150b57cec5SDimitry Andric fpu_d16, 1160b57cec5SDimitry Andric fpu_d17, 1170b57cec5SDimitry Andric fpu_d18, 1180b57cec5SDimitry Andric fpu_d19, 1190b57cec5SDimitry Andric fpu_d20, 1200b57cec5SDimitry Andric fpu_d21, 1210b57cec5SDimitry Andric fpu_d22, 1220b57cec5SDimitry Andric fpu_d23, 1230b57cec5SDimitry Andric fpu_d24, 1240b57cec5SDimitry Andric fpu_d25, 1250b57cec5SDimitry Andric fpu_d26, 1260b57cec5SDimitry Andric fpu_d27, 1270b57cec5SDimitry Andric fpu_d28, 1280b57cec5SDimitry Andric fpu_d29, 1290b57cec5SDimitry Andric fpu_d30, 1300b57cec5SDimitry Andric fpu_d31, 1310b57cec5SDimitry Andric 1320b57cec5SDimitry Andric fpu_q0, 1330b57cec5SDimitry Andric fpu_q1, 1340b57cec5SDimitry Andric fpu_q2, 1350b57cec5SDimitry Andric fpu_q3, 1360b57cec5SDimitry Andric fpu_q4, 1370b57cec5SDimitry Andric fpu_q5, 1380b57cec5SDimitry Andric fpu_q6, 1390b57cec5SDimitry Andric fpu_q7, 1400b57cec5SDimitry Andric fpu_q8, 1410b57cec5SDimitry Andric fpu_q9, 1420b57cec5SDimitry Andric fpu_q10, 1430b57cec5SDimitry Andric fpu_q11, 1440b57cec5SDimitry Andric fpu_q12, 1450b57cec5SDimitry Andric fpu_q13, 1460b57cec5SDimitry Andric fpu_q14, 1470b57cec5SDimitry Andric fpu_q15, 1480b57cec5SDimitry Andric 1490b57cec5SDimitry Andric exc_exception, 1500b57cec5SDimitry Andric exc_fsr, 1510b57cec5SDimitry Andric exc_far, 1520b57cec5SDimitry Andric 1530b57cec5SDimitry Andric dbg_bvr0, 1540b57cec5SDimitry Andric dbg_bvr1, 1550b57cec5SDimitry Andric dbg_bvr2, 1560b57cec5SDimitry Andric dbg_bvr3, 1570b57cec5SDimitry Andric dbg_bvr4, 1580b57cec5SDimitry Andric dbg_bvr5, 1590b57cec5SDimitry Andric dbg_bvr6, 1600b57cec5SDimitry Andric dbg_bvr7, 1610b57cec5SDimitry Andric dbg_bvr8, 1620b57cec5SDimitry Andric dbg_bvr9, 1630b57cec5SDimitry Andric dbg_bvr10, 1640b57cec5SDimitry Andric dbg_bvr11, 1650b57cec5SDimitry Andric dbg_bvr12, 1660b57cec5SDimitry Andric dbg_bvr13, 1670b57cec5SDimitry Andric dbg_bvr14, 1680b57cec5SDimitry Andric dbg_bvr15, 1690b57cec5SDimitry Andric 1700b57cec5SDimitry Andric dbg_bcr0, 1710b57cec5SDimitry Andric dbg_bcr1, 1720b57cec5SDimitry Andric dbg_bcr2, 1730b57cec5SDimitry Andric dbg_bcr3, 1740b57cec5SDimitry Andric dbg_bcr4, 1750b57cec5SDimitry Andric dbg_bcr5, 1760b57cec5SDimitry Andric dbg_bcr6, 1770b57cec5SDimitry Andric dbg_bcr7, 1780b57cec5SDimitry Andric dbg_bcr8, 1790b57cec5SDimitry Andric dbg_bcr9, 1800b57cec5SDimitry Andric dbg_bcr10, 1810b57cec5SDimitry Andric dbg_bcr11, 1820b57cec5SDimitry Andric dbg_bcr12, 1830b57cec5SDimitry Andric dbg_bcr13, 1840b57cec5SDimitry Andric dbg_bcr14, 1850b57cec5SDimitry Andric dbg_bcr15, 1860b57cec5SDimitry Andric 1870b57cec5SDimitry Andric dbg_wvr0, 1880b57cec5SDimitry Andric dbg_wvr1, 1890b57cec5SDimitry Andric dbg_wvr2, 1900b57cec5SDimitry Andric dbg_wvr3, 1910b57cec5SDimitry Andric dbg_wvr4, 1920b57cec5SDimitry Andric dbg_wvr5, 1930b57cec5SDimitry Andric dbg_wvr6, 1940b57cec5SDimitry Andric dbg_wvr7, 1950b57cec5SDimitry Andric dbg_wvr8, 1960b57cec5SDimitry Andric dbg_wvr9, 1970b57cec5SDimitry Andric dbg_wvr10, 1980b57cec5SDimitry Andric dbg_wvr11, 1990b57cec5SDimitry Andric dbg_wvr12, 2000b57cec5SDimitry Andric dbg_wvr13, 2010b57cec5SDimitry Andric dbg_wvr14, 2020b57cec5SDimitry Andric dbg_wvr15, 2030b57cec5SDimitry Andric 2040b57cec5SDimitry Andric dbg_wcr0, 2050b57cec5SDimitry Andric dbg_wcr1, 2060b57cec5SDimitry Andric dbg_wcr2, 2070b57cec5SDimitry Andric dbg_wcr3, 2080b57cec5SDimitry Andric dbg_wcr4, 2090b57cec5SDimitry Andric dbg_wcr5, 2100b57cec5SDimitry Andric dbg_wcr6, 2110b57cec5SDimitry Andric dbg_wcr7, 2120b57cec5SDimitry Andric dbg_wcr8, 2130b57cec5SDimitry Andric dbg_wcr9, 2140b57cec5SDimitry Andric dbg_wcr10, 2150b57cec5SDimitry Andric dbg_wcr11, 2160b57cec5SDimitry Andric dbg_wcr12, 2170b57cec5SDimitry Andric dbg_wcr13, 2180b57cec5SDimitry Andric dbg_wcr14, 2190b57cec5SDimitry Andric dbg_wcr15, 2200b57cec5SDimitry Andric 2210b57cec5SDimitry Andric k_num_registers 2220b57cec5SDimitry Andric }; 2230b57cec5SDimitry Andric 2240b57cec5SDimitry Andric static uint32_t g_s0_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM}; 2250b57cec5SDimitry Andric static uint32_t g_s1_invalidates[] = {fpu_d0, fpu_q0, LLDB_INVALID_REGNUM}; 2260b57cec5SDimitry Andric static uint32_t g_s2_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM}; 2270b57cec5SDimitry Andric static uint32_t g_s3_invalidates[] = {fpu_d1, fpu_q0, LLDB_INVALID_REGNUM}; 2280b57cec5SDimitry Andric static uint32_t g_s4_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM}; 2290b57cec5SDimitry Andric static uint32_t g_s5_invalidates[] = {fpu_d2, fpu_q1, LLDB_INVALID_REGNUM}; 2300b57cec5SDimitry Andric static uint32_t g_s6_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM}; 2310b57cec5SDimitry Andric static uint32_t g_s7_invalidates[] = {fpu_d3, fpu_q1, LLDB_INVALID_REGNUM}; 2320b57cec5SDimitry Andric static uint32_t g_s8_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM}; 2330b57cec5SDimitry Andric static uint32_t g_s9_invalidates[] = {fpu_d4, fpu_q2, LLDB_INVALID_REGNUM}; 2340b57cec5SDimitry Andric static uint32_t g_s10_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM}; 2350b57cec5SDimitry Andric static uint32_t g_s11_invalidates[] = {fpu_d5, fpu_q2, LLDB_INVALID_REGNUM}; 2360b57cec5SDimitry Andric static uint32_t g_s12_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM}; 2370b57cec5SDimitry Andric static uint32_t g_s13_invalidates[] = {fpu_d6, fpu_q3, LLDB_INVALID_REGNUM}; 2380b57cec5SDimitry Andric static uint32_t g_s14_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM}; 2390b57cec5SDimitry Andric static uint32_t g_s15_invalidates[] = {fpu_d7, fpu_q3, LLDB_INVALID_REGNUM}; 2400b57cec5SDimitry Andric static uint32_t g_s16_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM}; 2410b57cec5SDimitry Andric static uint32_t g_s17_invalidates[] = {fpu_d8, fpu_q4, LLDB_INVALID_REGNUM}; 2420b57cec5SDimitry Andric static uint32_t g_s18_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM}; 2430b57cec5SDimitry Andric static uint32_t g_s19_invalidates[] = {fpu_d9, fpu_q4, LLDB_INVALID_REGNUM}; 2440b57cec5SDimitry Andric static uint32_t g_s20_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM}; 2450b57cec5SDimitry Andric static uint32_t g_s21_invalidates[] = {fpu_d10, fpu_q5, LLDB_INVALID_REGNUM}; 2460b57cec5SDimitry Andric static uint32_t g_s22_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM}; 2470b57cec5SDimitry Andric static uint32_t g_s23_invalidates[] = {fpu_d11, fpu_q5, LLDB_INVALID_REGNUM}; 2480b57cec5SDimitry Andric static uint32_t g_s24_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM}; 2490b57cec5SDimitry Andric static uint32_t g_s25_invalidates[] = {fpu_d12, fpu_q6, LLDB_INVALID_REGNUM}; 2500b57cec5SDimitry Andric static uint32_t g_s26_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM}; 2510b57cec5SDimitry Andric static uint32_t g_s27_invalidates[] = {fpu_d13, fpu_q6, LLDB_INVALID_REGNUM}; 2520b57cec5SDimitry Andric static uint32_t g_s28_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM}; 2530b57cec5SDimitry Andric static uint32_t g_s29_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM}; 2540b57cec5SDimitry Andric static uint32_t g_s30_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM}; 2550b57cec5SDimitry Andric static uint32_t g_s31_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM}; 2560b57cec5SDimitry Andric 257349cc55cSDimitry Andric static uint32_t g_d0_invalidates[] = {fpu_q0, fpu_s0, fpu_s1, 258349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 259349cc55cSDimitry Andric static uint32_t g_d1_invalidates[] = {fpu_q0, fpu_s2, fpu_s3, 260349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 261349cc55cSDimitry Andric static uint32_t g_d2_invalidates[] = {fpu_q1, fpu_s4, fpu_s5, 262349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 263349cc55cSDimitry Andric static uint32_t g_d3_invalidates[] = {fpu_q1, fpu_s6, fpu_s7, 264349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 265349cc55cSDimitry Andric static uint32_t g_d4_invalidates[] = {fpu_q2, fpu_s8, fpu_s9, 266349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 267349cc55cSDimitry Andric static uint32_t g_d5_invalidates[] = {fpu_q2, fpu_s10, fpu_s11, 268349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 269349cc55cSDimitry Andric static uint32_t g_d6_invalidates[] = {fpu_q3, fpu_s12, fpu_s13, 270349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 271349cc55cSDimitry Andric static uint32_t g_d7_invalidates[] = {fpu_q3, fpu_s14, fpu_s15, 272349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 273349cc55cSDimitry Andric static uint32_t g_d8_invalidates[] = {fpu_q4, fpu_s16, fpu_s17, 274349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 275349cc55cSDimitry Andric static uint32_t g_d9_invalidates[] = {fpu_q4, fpu_s18, fpu_s19, 276349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 277349cc55cSDimitry Andric static uint32_t g_d10_invalidates[] = {fpu_q5, fpu_s20, fpu_s21, 278349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 279349cc55cSDimitry Andric static uint32_t g_d11_invalidates[] = {fpu_q5, fpu_s22, fpu_s23, 280349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 281349cc55cSDimitry Andric static uint32_t g_d12_invalidates[] = {fpu_q6, fpu_s24, fpu_s25, 282349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 283349cc55cSDimitry Andric static uint32_t g_d13_invalidates[] = {fpu_q6, fpu_s26, fpu_s27, 284349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 285349cc55cSDimitry Andric static uint32_t g_d14_invalidates[] = {fpu_q7, fpu_s28, fpu_s29, 286349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 287349cc55cSDimitry Andric static uint32_t g_d15_invalidates[] = {fpu_q7, fpu_s30, fpu_s31, 288349cc55cSDimitry Andric LLDB_INVALID_REGNUM}; 2890b57cec5SDimitry Andric static uint32_t g_d16_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM}; 2900b57cec5SDimitry Andric static uint32_t g_d17_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM}; 2910b57cec5SDimitry Andric static uint32_t g_d18_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM}; 2920b57cec5SDimitry Andric static uint32_t g_d19_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM}; 2930b57cec5SDimitry Andric static uint32_t g_d20_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM}; 2940b57cec5SDimitry Andric static uint32_t g_d21_invalidates[] = {fpu_q10, LLDB_INVALID_REGNUM}; 2950b57cec5SDimitry Andric static uint32_t g_d22_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM}; 2960b57cec5SDimitry Andric static uint32_t g_d23_invalidates[] = {fpu_q11, LLDB_INVALID_REGNUM}; 2970b57cec5SDimitry Andric static uint32_t g_d24_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM}; 2980b57cec5SDimitry Andric static uint32_t g_d25_invalidates[] = {fpu_q12, LLDB_INVALID_REGNUM}; 2990b57cec5SDimitry Andric static uint32_t g_d26_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM}; 3000b57cec5SDimitry Andric static uint32_t g_d27_invalidates[] = {fpu_q13, LLDB_INVALID_REGNUM}; 3010b57cec5SDimitry Andric static uint32_t g_d28_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM}; 3020b57cec5SDimitry Andric static uint32_t g_d29_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM}; 3030b57cec5SDimitry Andric static uint32_t g_d30_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM}; 3040b57cec5SDimitry Andric static uint32_t g_d31_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM}; 3050b57cec5SDimitry Andric 306349cc55cSDimitry Andric static uint32_t g_q0_invalidates[] = { 3070b57cec5SDimitry Andric fpu_d0, fpu_d1, fpu_s0, fpu_s1, fpu_s2, fpu_s3, LLDB_INVALID_REGNUM}; 308349cc55cSDimitry Andric static uint32_t g_q1_invalidates[] = { 3090b57cec5SDimitry Andric fpu_d2, fpu_d3, fpu_s4, fpu_s5, fpu_s6, fpu_s7, LLDB_INVALID_REGNUM}; 310349cc55cSDimitry Andric static uint32_t g_q2_invalidates[] = { 3110b57cec5SDimitry Andric fpu_d4, fpu_d5, fpu_s8, fpu_s9, fpu_s10, fpu_s11, LLDB_INVALID_REGNUM}; 312349cc55cSDimitry Andric static uint32_t g_q3_invalidates[] = { 3130b57cec5SDimitry Andric fpu_d6, fpu_d7, fpu_s12, fpu_s13, fpu_s14, fpu_s15, LLDB_INVALID_REGNUM}; 314349cc55cSDimitry Andric static uint32_t g_q4_invalidates[] = { 3150b57cec5SDimitry Andric fpu_d8, fpu_d9, fpu_s16, fpu_s17, fpu_s18, fpu_s19, LLDB_INVALID_REGNUM}; 316349cc55cSDimitry Andric static uint32_t g_q5_invalidates[] = { 3170b57cec5SDimitry Andric fpu_d10, fpu_d11, fpu_s20, fpu_s21, fpu_s22, fpu_s23, LLDB_INVALID_REGNUM}; 318349cc55cSDimitry Andric static uint32_t g_q6_invalidates[] = { 3190b57cec5SDimitry Andric fpu_d12, fpu_d13, fpu_s24, fpu_s25, fpu_s26, fpu_s27, LLDB_INVALID_REGNUM}; 320349cc55cSDimitry Andric static uint32_t g_q7_invalidates[] = { 3210b57cec5SDimitry Andric fpu_d14, fpu_d15, fpu_s28, fpu_s29, fpu_s30, fpu_s31, LLDB_INVALID_REGNUM}; 322349cc55cSDimitry Andric static uint32_t g_q8_invalidates[] = {fpu_d16, fpu_d17, LLDB_INVALID_REGNUM}; 323349cc55cSDimitry Andric static uint32_t g_q9_invalidates[] = {fpu_d18, fpu_d19, LLDB_INVALID_REGNUM}; 324349cc55cSDimitry Andric static uint32_t g_q10_invalidates[] = {fpu_d20, fpu_d21, LLDB_INVALID_REGNUM}; 325349cc55cSDimitry Andric static uint32_t g_q11_invalidates[] = {fpu_d22, fpu_d23, LLDB_INVALID_REGNUM}; 326349cc55cSDimitry Andric static uint32_t g_q12_invalidates[] = {fpu_d24, fpu_d25, LLDB_INVALID_REGNUM}; 327349cc55cSDimitry Andric static uint32_t g_q13_invalidates[] = {fpu_d26, fpu_d27, LLDB_INVALID_REGNUM}; 328349cc55cSDimitry Andric static uint32_t g_q14_invalidates[] = {fpu_d28, fpu_d29, LLDB_INVALID_REGNUM}; 329349cc55cSDimitry Andric static uint32_t g_q15_invalidates[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM}; 330349cc55cSDimitry Andric 331349cc55cSDimitry Andric static uint32_t g_q0_contained[] = {fpu_q0, LLDB_INVALID_REGNUM}; 332349cc55cSDimitry Andric static uint32_t g_q1_contained[] = {fpu_q1, LLDB_INVALID_REGNUM}; 333349cc55cSDimitry Andric static uint32_t g_q2_contained[] = {fpu_q2, LLDB_INVALID_REGNUM}; 334349cc55cSDimitry Andric static uint32_t g_q3_contained[] = {fpu_q3, LLDB_INVALID_REGNUM}; 335349cc55cSDimitry Andric static uint32_t g_q4_contained[] = {fpu_q4, LLDB_INVALID_REGNUM}; 336349cc55cSDimitry Andric static uint32_t g_q5_contained[] = {fpu_q5, LLDB_INVALID_REGNUM}; 337349cc55cSDimitry Andric static uint32_t g_q6_contained[] = {fpu_q6, LLDB_INVALID_REGNUM}; 338349cc55cSDimitry Andric static uint32_t g_q7_contained[] = {fpu_q7, LLDB_INVALID_REGNUM}; 339349cc55cSDimitry Andric static uint32_t g_q8_contained[] = {fpu_q8, LLDB_INVALID_REGNUM}; 340349cc55cSDimitry Andric static uint32_t g_q9_contained[] = {fpu_q9, LLDB_INVALID_REGNUM}; 341349cc55cSDimitry Andric static uint32_t g_q10_contained[] = {fpu_q10, LLDB_INVALID_REGNUM}; 342349cc55cSDimitry Andric static uint32_t g_q11_contained[] = {fpu_q11, LLDB_INVALID_REGNUM}; 343349cc55cSDimitry Andric static uint32_t g_q12_contained[] = {fpu_q12, LLDB_INVALID_REGNUM}; 344349cc55cSDimitry Andric static uint32_t g_q13_contained[] = {fpu_q13, LLDB_INVALID_REGNUM}; 345349cc55cSDimitry Andric static uint32_t g_q14_contained[] = {fpu_q14, LLDB_INVALID_REGNUM}; 346349cc55cSDimitry Andric static uint32_t g_q15_contained[] = {fpu_q15, LLDB_INVALID_REGNUM}; 347349cc55cSDimitry Andric 348349cc55cSDimitry Andric #define FPU_REG(name, size, offset, qreg) \ 349349cc55cSDimitry Andric { \ 350349cc55cSDimitry Andric #name, nullptr, size, FPU_OFFSET(offset), eEncodingIEEE754, eFormatFloat, \ 351349cc55cSDimitry Andric {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \ 352349cc55cSDimitry Andric LLDB_INVALID_REGNUM, fpu_##name }, \ 35306c3fb27SDimitry Andric g_##qreg##_contained, g_##name##_invalidates, nullptr, \ 354349cc55cSDimitry Andric } 355349cc55cSDimitry Andric 356349cc55cSDimitry Andric #define FPU_QREG(name, offset) \ 357349cc55cSDimitry Andric { \ 358349cc55cSDimitry Andric #name, nullptr, 16, FPU_OFFSET(offset), eEncodingVector, \ 359349cc55cSDimitry Andric eFormatVectorOfUInt8, \ 360349cc55cSDimitry Andric {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \ 361349cc55cSDimitry Andric LLDB_INVALID_REGNUM, fpu_##name }, \ 36206c3fb27SDimitry Andric nullptr, g_##name##_invalidates, nullptr, \ 363349cc55cSDimitry Andric } 3640b57cec5SDimitry Andric 3650b57cec5SDimitry Andric static RegisterInfo g_register_infos_arm[] = { 3660b57cec5SDimitry Andric // NAME ALT SZ OFFSET ENCODING FORMAT 3670b57cec5SDimitry Andric // EH_FRAME DWARF GENERIC 3680b57cec5SDimitry Andric // PROCESS PLUGIN LLDB NATIVE VALUE REGS INVALIDATE REGS 3690b57cec5SDimitry Andric // =========== ======= == ============== ================ 3700b57cec5SDimitry Andric // ==================== =================== =================== 3710b57cec5SDimitry Andric // ========================== =================== ============= 3720b57cec5SDimitry Andric // ============== ================= 373349cc55cSDimitry Andric { 374349cc55cSDimitry Andric "r0", 3750b57cec5SDimitry Andric nullptr, 3760b57cec5SDimitry Andric 4, 3770b57cec5SDimitry Andric GPR_OFFSET(0), 3780b57cec5SDimitry Andric eEncodingUint, 3790b57cec5SDimitry Andric eFormatHex, 3800b57cec5SDimitry Andric {ehframe_r0, dwarf_r0, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM, 3810b57cec5SDimitry Andric gpr_r0}, 3820b57cec5SDimitry Andric nullptr, 3830b57cec5SDimitry Andric nullptr, 38406c3fb27SDimitry Andric nullptr, 385349cc55cSDimitry Andric }, 386349cc55cSDimitry Andric { 387349cc55cSDimitry Andric "r1", 3880b57cec5SDimitry Andric nullptr, 3890b57cec5SDimitry Andric 4, 3900b57cec5SDimitry Andric GPR_OFFSET(1), 3910b57cec5SDimitry Andric eEncodingUint, 3920b57cec5SDimitry Andric eFormatHex, 3930b57cec5SDimitry Andric {ehframe_r1, dwarf_r1, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM, 3940b57cec5SDimitry Andric gpr_r1}, 3950b57cec5SDimitry Andric nullptr, 3960b57cec5SDimitry Andric nullptr, 39706c3fb27SDimitry Andric nullptr, 398349cc55cSDimitry Andric }, 399349cc55cSDimitry Andric { 400349cc55cSDimitry Andric "r2", 4010b57cec5SDimitry Andric nullptr, 4020b57cec5SDimitry Andric 4, 4030b57cec5SDimitry Andric GPR_OFFSET(2), 4040b57cec5SDimitry Andric eEncodingUint, 4050b57cec5SDimitry Andric eFormatHex, 4060b57cec5SDimitry Andric {ehframe_r2, dwarf_r2, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM, 4070b57cec5SDimitry Andric gpr_r2}, 4080b57cec5SDimitry Andric nullptr, 4090b57cec5SDimitry Andric nullptr, 41006c3fb27SDimitry Andric nullptr, 411349cc55cSDimitry Andric }, 412349cc55cSDimitry Andric { 413349cc55cSDimitry Andric "r3", 4140b57cec5SDimitry Andric nullptr, 4150b57cec5SDimitry Andric 4, 4160b57cec5SDimitry Andric GPR_OFFSET(3), 4170b57cec5SDimitry Andric eEncodingUint, 4180b57cec5SDimitry Andric eFormatHex, 4190b57cec5SDimitry Andric {ehframe_r3, dwarf_r3, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM, 4200b57cec5SDimitry Andric gpr_r3}, 4210b57cec5SDimitry Andric nullptr, 4220b57cec5SDimitry Andric nullptr, 42306c3fb27SDimitry Andric nullptr, 424349cc55cSDimitry Andric }, 425349cc55cSDimitry Andric { 426349cc55cSDimitry Andric "r4", 4270b57cec5SDimitry Andric nullptr, 4280b57cec5SDimitry Andric 4, 4290b57cec5SDimitry Andric GPR_OFFSET(4), 4300b57cec5SDimitry Andric eEncodingUint, 4310b57cec5SDimitry Andric eFormatHex, 432349cc55cSDimitry Andric {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 433349cc55cSDimitry Andric gpr_r4}, 4340b57cec5SDimitry Andric nullptr, 4350b57cec5SDimitry Andric nullptr, 43606c3fb27SDimitry Andric nullptr, 437349cc55cSDimitry Andric }, 438349cc55cSDimitry Andric { 439349cc55cSDimitry Andric "r5", 4400b57cec5SDimitry Andric nullptr, 4410b57cec5SDimitry Andric 4, 4420b57cec5SDimitry Andric GPR_OFFSET(5), 4430b57cec5SDimitry Andric eEncodingUint, 4440b57cec5SDimitry Andric eFormatHex, 445349cc55cSDimitry Andric {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 446349cc55cSDimitry Andric gpr_r5}, 4470b57cec5SDimitry Andric nullptr, 4480b57cec5SDimitry Andric nullptr, 44906c3fb27SDimitry Andric nullptr, 450349cc55cSDimitry Andric }, 451349cc55cSDimitry Andric { 452349cc55cSDimitry Andric "r6", 4530b57cec5SDimitry Andric nullptr, 4540b57cec5SDimitry Andric 4, 4550b57cec5SDimitry Andric GPR_OFFSET(6), 4560b57cec5SDimitry Andric eEncodingUint, 4570b57cec5SDimitry Andric eFormatHex, 458349cc55cSDimitry Andric {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 459349cc55cSDimitry Andric gpr_r6}, 4600b57cec5SDimitry Andric nullptr, 4610b57cec5SDimitry Andric nullptr, 46206c3fb27SDimitry Andric nullptr, 463349cc55cSDimitry Andric }, 464349cc55cSDimitry Andric { 465349cc55cSDimitry Andric "r7", 4660b57cec5SDimitry Andric nullptr, 4670b57cec5SDimitry Andric 4, 4680b57cec5SDimitry Andric GPR_OFFSET(7), 4690b57cec5SDimitry Andric eEncodingUint, 4700b57cec5SDimitry Andric eFormatHex, 471349cc55cSDimitry Andric {ehframe_r7, dwarf_r7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 472349cc55cSDimitry Andric gpr_r7}, 4730b57cec5SDimitry Andric nullptr, 4740b57cec5SDimitry Andric nullptr, 47506c3fb27SDimitry Andric nullptr, 476349cc55cSDimitry Andric }, 477349cc55cSDimitry Andric { 478349cc55cSDimitry Andric "r8", 4790b57cec5SDimitry Andric nullptr, 4800b57cec5SDimitry Andric 4, 4810b57cec5SDimitry Andric GPR_OFFSET(8), 4820b57cec5SDimitry Andric eEncodingUint, 4830b57cec5SDimitry Andric eFormatHex, 484349cc55cSDimitry Andric {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 485349cc55cSDimitry Andric gpr_r8}, 4860b57cec5SDimitry Andric nullptr, 4870b57cec5SDimitry Andric nullptr, 48806c3fb27SDimitry Andric nullptr, 489349cc55cSDimitry Andric }, 490349cc55cSDimitry Andric { 491349cc55cSDimitry Andric "r9", 4920b57cec5SDimitry Andric nullptr, 4930b57cec5SDimitry Andric 4, 4940b57cec5SDimitry Andric GPR_OFFSET(9), 4950b57cec5SDimitry Andric eEncodingUint, 4960b57cec5SDimitry Andric eFormatHex, 497349cc55cSDimitry Andric {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 498349cc55cSDimitry Andric gpr_r9}, 4990b57cec5SDimitry Andric nullptr, 5000b57cec5SDimitry Andric nullptr, 50106c3fb27SDimitry Andric nullptr, 502349cc55cSDimitry Andric }, 503349cc55cSDimitry Andric { 504349cc55cSDimitry Andric "r10", 5050b57cec5SDimitry Andric nullptr, 5060b57cec5SDimitry Andric 4, 5070b57cec5SDimitry Andric GPR_OFFSET(10), 5080b57cec5SDimitry Andric eEncodingUint, 5090b57cec5SDimitry Andric eFormatHex, 5100b57cec5SDimitry Andric {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 5110b57cec5SDimitry Andric gpr_r10}, 5120b57cec5SDimitry Andric nullptr, 5130b57cec5SDimitry Andric nullptr, 51406c3fb27SDimitry Andric nullptr, 515349cc55cSDimitry Andric }, 516349cc55cSDimitry Andric { 517349cc55cSDimitry Andric "r11", 5180b57cec5SDimitry Andric nullptr, 5190b57cec5SDimitry Andric 4, 5200b57cec5SDimitry Andric GPR_OFFSET(11), 5210b57cec5SDimitry Andric eEncodingUint, 5220b57cec5SDimitry Andric eFormatHex, 5230b57cec5SDimitry Andric {ehframe_r11, dwarf_r11, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, 5240b57cec5SDimitry Andric gpr_r11}, 5250b57cec5SDimitry Andric nullptr, 5260b57cec5SDimitry Andric nullptr, 52706c3fb27SDimitry Andric nullptr, 528349cc55cSDimitry Andric }, 529349cc55cSDimitry Andric { 530349cc55cSDimitry Andric "r12", 5310b57cec5SDimitry Andric nullptr, 5320b57cec5SDimitry Andric 4, 5330b57cec5SDimitry Andric GPR_OFFSET(12), 5340b57cec5SDimitry Andric eEncodingUint, 5350b57cec5SDimitry Andric eFormatHex, 5360b57cec5SDimitry Andric {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 5370b57cec5SDimitry Andric gpr_r12}, 5380b57cec5SDimitry Andric nullptr, 5390b57cec5SDimitry Andric nullptr, 54006c3fb27SDimitry Andric nullptr, 541349cc55cSDimitry Andric }, 542349cc55cSDimitry Andric { 543349cc55cSDimitry Andric "sp", 5440b57cec5SDimitry Andric "r13", 5450b57cec5SDimitry Andric 4, 5460b57cec5SDimitry Andric GPR_OFFSET(13), 5470b57cec5SDimitry Andric eEncodingUint, 5480b57cec5SDimitry Andric eFormatHex, 5490b57cec5SDimitry Andric {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, 5500b57cec5SDimitry Andric gpr_sp}, 5510b57cec5SDimitry Andric nullptr, 5520b57cec5SDimitry Andric nullptr, 55306c3fb27SDimitry Andric nullptr, 554349cc55cSDimitry Andric }, 555349cc55cSDimitry Andric { 556349cc55cSDimitry Andric "lr", 5570b57cec5SDimitry Andric "r14", 5580b57cec5SDimitry Andric 4, 5590b57cec5SDimitry Andric GPR_OFFSET(14), 5600b57cec5SDimitry Andric eEncodingUint, 5610b57cec5SDimitry Andric eFormatHex, 5620b57cec5SDimitry Andric {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, 5630b57cec5SDimitry Andric gpr_lr}, 5640b57cec5SDimitry Andric nullptr, 5650b57cec5SDimitry Andric nullptr, 56606c3fb27SDimitry Andric nullptr, 567349cc55cSDimitry Andric }, 568349cc55cSDimitry Andric { 569349cc55cSDimitry Andric "pc", 5700b57cec5SDimitry Andric "r15", 5710b57cec5SDimitry Andric 4, 5720b57cec5SDimitry Andric GPR_OFFSET(15), 5730b57cec5SDimitry Andric eEncodingUint, 5740b57cec5SDimitry Andric eFormatHex, 5750b57cec5SDimitry Andric {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, 5760b57cec5SDimitry Andric gpr_pc}, 5770b57cec5SDimitry Andric nullptr, 5780b57cec5SDimitry Andric nullptr, 57906c3fb27SDimitry Andric nullptr, 580349cc55cSDimitry Andric }, 581349cc55cSDimitry Andric { 582349cc55cSDimitry Andric "cpsr", 5830b57cec5SDimitry Andric "psr", 5840b57cec5SDimitry Andric 4, 5850b57cec5SDimitry Andric GPR_OFFSET(16), 5860b57cec5SDimitry Andric eEncodingUint, 5870b57cec5SDimitry Andric eFormatHex, 588349cc55cSDimitry Andric {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, 589349cc55cSDimitry Andric LLDB_INVALID_REGNUM, gpr_cpsr}, 5900b57cec5SDimitry Andric nullptr, 5910b57cec5SDimitry Andric nullptr, 59206c3fb27SDimitry Andric nullptr, 593349cc55cSDimitry Andric }, 5940b57cec5SDimitry Andric 595349cc55cSDimitry Andric FPU_REG(s0, 4, 0, q0), 596349cc55cSDimitry Andric FPU_REG(s1, 4, 1, q0), 597349cc55cSDimitry Andric FPU_REG(s2, 4, 2, q0), 598349cc55cSDimitry Andric FPU_REG(s3, 4, 3, q0), 599349cc55cSDimitry Andric FPU_REG(s4, 4, 4, q1), 600349cc55cSDimitry Andric FPU_REG(s5, 4, 5, q1), 601349cc55cSDimitry Andric FPU_REG(s6, 4, 6, q1), 602349cc55cSDimitry Andric FPU_REG(s7, 4, 7, q1), 603349cc55cSDimitry Andric FPU_REG(s8, 4, 8, q2), 604349cc55cSDimitry Andric FPU_REG(s9, 4, 9, q2), 605349cc55cSDimitry Andric FPU_REG(s10, 4, 10, q2), 606349cc55cSDimitry Andric FPU_REG(s11, 4, 11, q2), 607349cc55cSDimitry Andric FPU_REG(s12, 4, 12, q3), 608349cc55cSDimitry Andric FPU_REG(s13, 4, 13, q3), 609349cc55cSDimitry Andric FPU_REG(s14, 4, 14, q3), 610349cc55cSDimitry Andric FPU_REG(s15, 4, 15, q3), 611349cc55cSDimitry Andric FPU_REG(s16, 4, 16, q4), 612349cc55cSDimitry Andric FPU_REG(s17, 4, 17, q4), 613349cc55cSDimitry Andric FPU_REG(s18, 4, 18, q4), 614349cc55cSDimitry Andric FPU_REG(s19, 4, 19, q4), 615349cc55cSDimitry Andric FPU_REG(s20, 4, 20, q5), 616349cc55cSDimitry Andric FPU_REG(s21, 4, 21, q5), 617349cc55cSDimitry Andric FPU_REG(s22, 4, 22, q5), 618349cc55cSDimitry Andric FPU_REG(s23, 4, 23, q5), 619349cc55cSDimitry Andric FPU_REG(s24, 4, 24, q6), 620349cc55cSDimitry Andric FPU_REG(s25, 4, 25, q6), 621349cc55cSDimitry Andric FPU_REG(s26, 4, 26, q6), 622349cc55cSDimitry Andric FPU_REG(s27, 4, 27, q6), 623349cc55cSDimitry Andric FPU_REG(s28, 4, 28, q7), 624349cc55cSDimitry Andric FPU_REG(s29, 4, 29, q7), 625349cc55cSDimitry Andric FPU_REG(s30, 4, 30, q7), 626349cc55cSDimitry Andric FPU_REG(s31, 4, 31, q7), 627349cc55cSDimitry Andric 628349cc55cSDimitry Andric { 629349cc55cSDimitry Andric "fpscr", 6300b57cec5SDimitry Andric nullptr, 6310b57cec5SDimitry Andric 4, 6320b57cec5SDimitry Andric FPSCR_OFFSET, 6330b57cec5SDimitry Andric eEncodingUint, 6340b57cec5SDimitry Andric eFormatHex, 6350b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 6360b57cec5SDimitry Andric LLDB_INVALID_REGNUM, fpu_fpscr}, 6370b57cec5SDimitry Andric nullptr, 6380b57cec5SDimitry Andric nullptr, 63906c3fb27SDimitry Andric nullptr, 640349cc55cSDimitry Andric }, 6410b57cec5SDimitry Andric 642349cc55cSDimitry Andric FPU_REG(d0, 8, 0, q0), 643349cc55cSDimitry Andric FPU_REG(d1, 8, 2, q0), 644349cc55cSDimitry Andric FPU_REG(d2, 8, 4, q1), 645349cc55cSDimitry Andric FPU_REG(d3, 8, 6, q1), 646349cc55cSDimitry Andric FPU_REG(d4, 8, 8, q2), 647349cc55cSDimitry Andric FPU_REG(d5, 8, 10, q2), 648349cc55cSDimitry Andric FPU_REG(d6, 8, 12, q3), 649349cc55cSDimitry Andric FPU_REG(d7, 8, 14, q3), 650349cc55cSDimitry Andric FPU_REG(d8, 8, 16, q4), 651349cc55cSDimitry Andric FPU_REG(d9, 8, 18, q4), 652349cc55cSDimitry Andric FPU_REG(d10, 8, 20, q5), 653349cc55cSDimitry Andric FPU_REG(d11, 8, 22, q5), 654349cc55cSDimitry Andric FPU_REG(d12, 8, 24, q6), 655349cc55cSDimitry Andric FPU_REG(d13, 8, 26, q6), 656349cc55cSDimitry Andric FPU_REG(d14, 8, 28, q7), 657349cc55cSDimitry Andric FPU_REG(d15, 8, 30, q7), 658349cc55cSDimitry Andric FPU_REG(d16, 8, 32, q8), 659349cc55cSDimitry Andric FPU_REG(d17, 8, 34, q8), 660349cc55cSDimitry Andric FPU_REG(d18, 8, 36, q9), 661349cc55cSDimitry Andric FPU_REG(d19, 8, 38, q9), 662349cc55cSDimitry Andric FPU_REG(d20, 8, 40, q10), 663349cc55cSDimitry Andric FPU_REG(d21, 8, 42, q10), 664349cc55cSDimitry Andric FPU_REG(d22, 8, 44, q11), 665349cc55cSDimitry Andric FPU_REG(d23, 8, 46, q11), 666349cc55cSDimitry Andric FPU_REG(d24, 8, 48, q12), 667349cc55cSDimitry Andric FPU_REG(d25, 8, 50, q12), 668349cc55cSDimitry Andric FPU_REG(d26, 8, 52, q13), 669349cc55cSDimitry Andric FPU_REG(d27, 8, 54, q13), 670349cc55cSDimitry Andric FPU_REG(d28, 8, 56, q14), 671349cc55cSDimitry Andric FPU_REG(d29, 8, 58, q14), 672349cc55cSDimitry Andric FPU_REG(d30, 8, 60, q15), 673349cc55cSDimitry Andric FPU_REG(d31, 8, 62, q15), 6740b57cec5SDimitry Andric 675349cc55cSDimitry Andric FPU_QREG(q0, 0), 676349cc55cSDimitry Andric FPU_QREG(q1, 4), 677349cc55cSDimitry Andric FPU_QREG(q2, 8), 678349cc55cSDimitry Andric FPU_QREG(q3, 12), 679349cc55cSDimitry Andric FPU_QREG(q4, 16), 680349cc55cSDimitry Andric FPU_QREG(q5, 20), 681349cc55cSDimitry Andric FPU_QREG(q6, 24), 682349cc55cSDimitry Andric FPU_QREG(q7, 28), 683349cc55cSDimitry Andric FPU_QREG(q8, 32), 684349cc55cSDimitry Andric FPU_QREG(q9, 36), 685349cc55cSDimitry Andric FPU_QREG(q10, 40), 686349cc55cSDimitry Andric FPU_QREG(q11, 44), 687349cc55cSDimitry Andric FPU_QREG(q12, 48), 688349cc55cSDimitry Andric FPU_QREG(q13, 52), 689349cc55cSDimitry Andric FPU_QREG(q14, 56), 690349cc55cSDimitry Andric FPU_QREG(q15, 60), 6910b57cec5SDimitry Andric 692349cc55cSDimitry Andric { 693349cc55cSDimitry Andric "exception", 6940b57cec5SDimitry Andric nullptr, 6950b57cec5SDimitry Andric 4, 6960b57cec5SDimitry Andric EXC_OFFSET(0), 6970b57cec5SDimitry Andric eEncodingUint, 6980b57cec5SDimitry Andric eFormatHex, 6990b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 7000b57cec5SDimitry Andric LLDB_INVALID_REGNUM, exc_exception}, 7010b57cec5SDimitry Andric nullptr, 7020b57cec5SDimitry Andric nullptr, 70306c3fb27SDimitry Andric nullptr, 704349cc55cSDimitry Andric }, 705349cc55cSDimitry Andric { 706349cc55cSDimitry Andric "fsr", 7070b57cec5SDimitry Andric nullptr, 7080b57cec5SDimitry Andric 4, 7090b57cec5SDimitry Andric EXC_OFFSET(1), 7100b57cec5SDimitry Andric eEncodingUint, 7110b57cec5SDimitry Andric eFormatHex, 7120b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 7130b57cec5SDimitry Andric LLDB_INVALID_REGNUM, exc_fsr}, 7140b57cec5SDimitry Andric nullptr, 7150b57cec5SDimitry Andric nullptr, 71606c3fb27SDimitry Andric nullptr, 717349cc55cSDimitry Andric }, 718349cc55cSDimitry Andric { 719349cc55cSDimitry Andric "far", 7200b57cec5SDimitry Andric nullptr, 7210b57cec5SDimitry Andric 4, 7220b57cec5SDimitry Andric EXC_OFFSET(2), 7230b57cec5SDimitry Andric eEncodingUint, 7240b57cec5SDimitry Andric eFormatHex, 7250b57cec5SDimitry Andric {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, 7260b57cec5SDimitry Andric LLDB_INVALID_REGNUM, exc_far}, 7270b57cec5SDimitry Andric nullptr, 7280b57cec5SDimitry Andric nullptr, 72906c3fb27SDimitry Andric nullptr, 730349cc55cSDimitry Andric }, 7310b57cec5SDimitry Andric 7320b57cec5SDimitry Andric {DEFINE_DBG(bvr, 0)}, 7330b57cec5SDimitry Andric {DEFINE_DBG(bvr, 1)}, 7340b57cec5SDimitry Andric {DEFINE_DBG(bvr, 2)}, 7350b57cec5SDimitry Andric {DEFINE_DBG(bvr, 3)}, 7360b57cec5SDimitry Andric {DEFINE_DBG(bvr, 4)}, 7370b57cec5SDimitry Andric {DEFINE_DBG(bvr, 5)}, 7380b57cec5SDimitry Andric {DEFINE_DBG(bvr, 6)}, 7390b57cec5SDimitry Andric {DEFINE_DBG(bvr, 7)}, 7400b57cec5SDimitry Andric {DEFINE_DBG(bvr, 8)}, 7410b57cec5SDimitry Andric {DEFINE_DBG(bvr, 9)}, 7420b57cec5SDimitry Andric {DEFINE_DBG(bvr, 10)}, 7430b57cec5SDimitry Andric {DEFINE_DBG(bvr, 11)}, 7440b57cec5SDimitry Andric {DEFINE_DBG(bvr, 12)}, 7450b57cec5SDimitry Andric {DEFINE_DBG(bvr, 13)}, 7460b57cec5SDimitry Andric {DEFINE_DBG(bvr, 14)}, 7470b57cec5SDimitry Andric {DEFINE_DBG(bvr, 15)}, 7480b57cec5SDimitry Andric 7490b57cec5SDimitry Andric {DEFINE_DBG(bcr, 0)}, 7500b57cec5SDimitry Andric {DEFINE_DBG(bcr, 1)}, 7510b57cec5SDimitry Andric {DEFINE_DBG(bcr, 2)}, 7520b57cec5SDimitry Andric {DEFINE_DBG(bcr, 3)}, 7530b57cec5SDimitry Andric {DEFINE_DBG(bcr, 4)}, 7540b57cec5SDimitry Andric {DEFINE_DBG(bcr, 5)}, 7550b57cec5SDimitry Andric {DEFINE_DBG(bcr, 6)}, 7560b57cec5SDimitry Andric {DEFINE_DBG(bcr, 7)}, 7570b57cec5SDimitry Andric {DEFINE_DBG(bcr, 8)}, 7580b57cec5SDimitry Andric {DEFINE_DBG(bcr, 9)}, 7590b57cec5SDimitry Andric {DEFINE_DBG(bcr, 10)}, 7600b57cec5SDimitry Andric {DEFINE_DBG(bcr, 11)}, 7610b57cec5SDimitry Andric {DEFINE_DBG(bcr, 12)}, 7620b57cec5SDimitry Andric {DEFINE_DBG(bcr, 13)}, 7630b57cec5SDimitry Andric {DEFINE_DBG(bcr, 14)}, 7640b57cec5SDimitry Andric {DEFINE_DBG(bcr, 15)}, 7650b57cec5SDimitry Andric 7660b57cec5SDimitry Andric {DEFINE_DBG(wvr, 0)}, 7670b57cec5SDimitry Andric {DEFINE_DBG(wvr, 1)}, 7680b57cec5SDimitry Andric {DEFINE_DBG(wvr, 2)}, 7690b57cec5SDimitry Andric {DEFINE_DBG(wvr, 3)}, 7700b57cec5SDimitry Andric {DEFINE_DBG(wvr, 4)}, 7710b57cec5SDimitry Andric {DEFINE_DBG(wvr, 5)}, 7720b57cec5SDimitry Andric {DEFINE_DBG(wvr, 6)}, 7730b57cec5SDimitry Andric {DEFINE_DBG(wvr, 7)}, 7740b57cec5SDimitry Andric {DEFINE_DBG(wvr, 8)}, 7750b57cec5SDimitry Andric {DEFINE_DBG(wvr, 9)}, 7760b57cec5SDimitry Andric {DEFINE_DBG(wvr, 10)}, 7770b57cec5SDimitry Andric {DEFINE_DBG(wvr, 11)}, 7780b57cec5SDimitry Andric {DEFINE_DBG(wvr, 12)}, 7790b57cec5SDimitry Andric {DEFINE_DBG(wvr, 13)}, 7800b57cec5SDimitry Andric {DEFINE_DBG(wvr, 14)}, 7810b57cec5SDimitry Andric {DEFINE_DBG(wvr, 15)}, 7820b57cec5SDimitry Andric 7830b57cec5SDimitry Andric {DEFINE_DBG(wcr, 0)}, 7840b57cec5SDimitry Andric {DEFINE_DBG(wcr, 1)}, 7850b57cec5SDimitry Andric {DEFINE_DBG(wcr, 2)}, 7860b57cec5SDimitry Andric {DEFINE_DBG(wcr, 3)}, 7870b57cec5SDimitry Andric {DEFINE_DBG(wcr, 4)}, 7880b57cec5SDimitry Andric {DEFINE_DBG(wcr, 5)}, 7890b57cec5SDimitry Andric {DEFINE_DBG(wcr, 6)}, 7900b57cec5SDimitry Andric {DEFINE_DBG(wcr, 7)}, 7910b57cec5SDimitry Andric {DEFINE_DBG(wcr, 8)}, 7920b57cec5SDimitry Andric {DEFINE_DBG(wcr, 9)}, 7930b57cec5SDimitry Andric {DEFINE_DBG(wcr, 10)}, 7940b57cec5SDimitry Andric {DEFINE_DBG(wcr, 11)}, 7950b57cec5SDimitry Andric {DEFINE_DBG(wcr, 12)}, 7960b57cec5SDimitry Andric {DEFINE_DBG(wcr, 13)}, 7970b57cec5SDimitry Andric {DEFINE_DBG(wcr, 14)}, 7980b57cec5SDimitry Andric {DEFINE_DBG(wcr, 15)}}; 7990b57cec5SDimitry Andric 8000b57cec5SDimitry Andric #endif // DECLARE_REGISTER_INFOS_ARM_STRUCT 801