1 //===-- RegisterInfos_mips64.h ----------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include <cstddef> 10 11 #include "lldb/Core/dwarf.h" 12 #include "llvm/Support/Compiler.h" 13 14 15 #ifdef DECLARE_REGISTER_INFOS_MIPS64_STRUCT 16 17 // Computes the offset of the given GPR in the user data area. 18 #define GPR_OFFSET(regname) (LLVM_EXTENSION offsetof(GPR_freebsd_mips, regname)) 19 20 // RegisterKind: EHFrame, DWARF, Generic, Process Plugin, LLDB 21 22 // Note that the size and offset will be updated by platform-specific classes. 23 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \ 24 { \ 25 #reg, alt, sizeof(((GPR_freebsd_mips *) 0)->reg), \ 26 GPR_OFFSET(reg), eEncodingUint, eFormatHex, \ 27 {kind1, kind2, kind3, kind4, \ 28 gpr_##reg##_mips64 }, \ 29 NULL, NULL, NULL, 0 \ 30 } 31 32 static RegisterInfo g_register_infos_mips64[] = { 33 // General purpose registers. EH_Frame, DWARF, 34 // Generic, Process Plugin 35 DEFINE_GPR(zero, "r0", dwarf_zero_mips64, dwarf_zero_mips64, 36 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 37 DEFINE_GPR(r1, nullptr, dwarf_r1_mips64, dwarf_r1_mips64, 38 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 39 DEFINE_GPR(r2, nullptr, dwarf_r2_mips64, dwarf_r2_mips64, 40 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 41 DEFINE_GPR(r3, nullptr, dwarf_r3_mips64, dwarf_r3_mips64, 42 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 43 DEFINE_GPR(r4, nullptr, dwarf_r4_mips64, dwarf_r4_mips64, 44 LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM), 45 DEFINE_GPR(r5, nullptr, dwarf_r5_mips64, dwarf_r5_mips64, 46 LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM), 47 DEFINE_GPR(r6, nullptr, dwarf_r6_mips64, dwarf_r6_mips64, 48 LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM), 49 DEFINE_GPR(r7, nullptr, dwarf_r7_mips64, dwarf_r7_mips64, 50 LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM), 51 DEFINE_GPR(r8, nullptr, dwarf_r8_mips64, dwarf_r8_mips64, 52 LLDB_REGNUM_GENERIC_ARG5, LLDB_INVALID_REGNUM), 53 DEFINE_GPR(r9, nullptr, dwarf_r9_mips64, dwarf_r9_mips64, 54 LLDB_REGNUM_GENERIC_ARG6, LLDB_INVALID_REGNUM), 55 DEFINE_GPR(r10, nullptr, dwarf_r10_mips64, dwarf_r10_mips64, 56 LLDB_REGNUM_GENERIC_ARG7, LLDB_INVALID_REGNUM), 57 DEFINE_GPR(r11, nullptr, dwarf_r11_mips64, dwarf_r11_mips64, 58 LLDB_REGNUM_GENERIC_ARG8, LLDB_INVALID_REGNUM), 59 DEFINE_GPR(r12, nullptr, dwarf_r12_mips64, dwarf_r12_mips64, 60 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 61 DEFINE_GPR(r13, nullptr, dwarf_r13_mips64, dwarf_r13_mips64, 62 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 63 DEFINE_GPR(r14, nullptr, dwarf_r14_mips64, dwarf_r14_mips64, 64 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 65 DEFINE_GPR(r15, nullptr, dwarf_r15_mips64, dwarf_r15_mips64, 66 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 67 DEFINE_GPR(r16, nullptr, dwarf_r16_mips64, dwarf_r16_mips64, 68 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 69 DEFINE_GPR(r17, nullptr, dwarf_r17_mips64, dwarf_r17_mips64, 70 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 71 DEFINE_GPR(r18, nullptr, dwarf_r18_mips64, dwarf_r18_mips64, 72 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 73 DEFINE_GPR(r19, nullptr, dwarf_r19_mips64, dwarf_r19_mips64, 74 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 75 DEFINE_GPR(r20, nullptr, dwarf_r20_mips64, dwarf_r20_mips64, 76 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 77 DEFINE_GPR(r21, nullptr, dwarf_r21_mips64, dwarf_r21_mips64, 78 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 79 DEFINE_GPR(r22, nullptr, dwarf_r22_mips64, dwarf_r22_mips64, 80 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 81 DEFINE_GPR(r23, nullptr, dwarf_r23_mips64, dwarf_r23_mips64, 82 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 83 DEFINE_GPR(r24, nullptr, dwarf_r24_mips64, dwarf_r24_mips64, 84 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 85 DEFINE_GPR(r25, nullptr, dwarf_r25_mips64, dwarf_r25_mips64, 86 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 87 DEFINE_GPR(r26, nullptr, dwarf_r26_mips64, dwarf_r26_mips64, 88 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 89 DEFINE_GPR(r27, nullptr, dwarf_r27_mips64, dwarf_r27_mips64, 90 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 91 DEFINE_GPR(gp, "r28", dwarf_gp_mips64, dwarf_gp_mips64, LLDB_INVALID_REGNUM, 92 LLDB_INVALID_REGNUM), 93 DEFINE_GPR(sp, "r29", dwarf_sp_mips64, dwarf_sp_mips64, 94 LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM), 95 DEFINE_GPR(r30, nullptr, dwarf_r30_mips64, dwarf_r30_mips64, 96 LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM), 97 DEFINE_GPR(ra, "r31", dwarf_ra_mips64, dwarf_ra_mips64, 98 LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM), 99 DEFINE_GPR(sr, nullptr, dwarf_sr_mips64, dwarf_sr_mips64, 100 LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM), 101 DEFINE_GPR(mullo, nullptr, dwarf_lo_mips64, dwarf_lo_mips64, 102 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 103 DEFINE_GPR(mulhi, nullptr, dwarf_hi_mips64, dwarf_hi_mips64, 104 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 105 DEFINE_GPR(badvaddr, nullptr, dwarf_bad_mips64, dwarf_bad_mips64, 106 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 107 DEFINE_GPR(cause, nullptr, dwarf_cause_mips64, dwarf_cause_mips64, 108 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 109 DEFINE_GPR(pc, "pc", dwarf_pc_mips64, dwarf_pc_mips64, 110 LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM), 111 DEFINE_GPR(ic, nullptr, dwarf_ic_mips64, dwarf_ic_mips64, 112 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 113 DEFINE_GPR(dummy, nullptr, dwarf_dummy_mips64, dwarf_dummy_mips64, 114 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), 115 }; 116 117 static_assert((sizeof(g_register_infos_mips64) / 118 sizeof(g_register_infos_mips64[0])) == k_num_registers_mips64, 119 "g_register_infos_mips64 has wrong number of register infos"); 120 121 #undef DEFINE_GPR 122 #undef DEFINE_GPR_INFO 123 #undef DEFINE_FPR 124 #undef DEFINE_FPR_INFO 125 #undef DEFINE_MSA 126 #undef DEFINE_MSA_INFO 127 #undef GPR_OFFSET 128 #undef FPR_OFFSET 129 #undef MSA_OFFSET 130 131 #endif // DECLARE_REGISTER_INFOS_MIPS64_STRUCT 132