1 //===- Construction of codegen pass pipelines ------------------*- C++ -*--===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// 10 /// Interfaces for registering analysis passes, producing common pass manager 11 /// configurations, and parsing of pass pipelines. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_CODEGENPASSBUILDER_H 16 #define LLVM_CODEGEN_CODEGENPASSBUILDER_H 17 18 #include "llvm/ADT/FunctionExtras.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/ADT/StringRef.h" 21 #include "llvm/Analysis/AliasAnalysis.h" 22 #include "llvm/Analysis/BasicAliasAnalysis.h" 23 #include "llvm/Analysis/CFLAndersAliasAnalysis.h" 24 #include "llvm/Analysis/CFLSteensAliasAnalysis.h" 25 #include "llvm/Analysis/ScopedNoAliasAA.h" 26 #include "llvm/Analysis/TargetTransformInfo.h" 27 #include "llvm/Analysis/TypeBasedAliasAnalysis.h" 28 #include "llvm/CodeGen/ExpandReductions.h" 29 #include "llvm/CodeGen/MachineModuleInfo.h" 30 #include "llvm/CodeGen/MachinePassManager.h" 31 #include "llvm/CodeGen/PreISelIntrinsicLowering.h" 32 #include "llvm/CodeGen/UnreachableBlockElim.h" 33 #include "llvm/IR/IRPrintingPasses.h" 34 #include "llvm/IR/PassManager.h" 35 #include "llvm/IR/Verifier.h" 36 #include "llvm/MC/MCAsmInfo.h" 37 #include "llvm/MC/MCStreamer.h" 38 #include "llvm/MC/MCTargetOptions.h" 39 #include "llvm/Support/CodeGen.h" 40 #include "llvm/Support/Debug.h" 41 #include "llvm/Support/Error.h" 42 #include "llvm/Support/ErrorHandling.h" 43 #include "llvm/Target/CGPassBuilderOption.h" 44 #include "llvm/Target/TargetMachine.h" 45 #include "llvm/Transforms/Scalar.h" 46 #include "llvm/Transforms/Scalar/ConstantHoisting.h" 47 #include "llvm/Transforms/Scalar/LoopPassManager.h" 48 #include "llvm/Transforms/Scalar/LoopStrengthReduce.h" 49 #include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h" 50 #include "llvm/Transforms/Scalar/MergeICmps.h" 51 #include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h" 52 #include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h" 53 #include "llvm/Transforms/Utils.h" 54 #include "llvm/Transforms/Utils/EntryExitInstrumenter.h" 55 #include "llvm/Transforms/Utils/LowerInvoke.h" 56 #include <cassert> 57 #include <string> 58 #include <type_traits> 59 #include <utility> 60 61 namespace llvm { 62 63 // FIXME: Dummy target independent passes definitions that have not yet been 64 // ported to new pass manager. Once they do, remove these. 65 #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 66 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \ 67 template <typename... Ts> PASS_NAME(Ts &&...) {} \ 68 PreservedAnalyses run(Function &, FunctionAnalysisManager &) { \ 69 return PreservedAnalyses::all(); \ 70 } \ 71 }; 72 #define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 73 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \ 74 template <typename... Ts> PASS_NAME(Ts &&...) {} \ 75 PreservedAnalyses run(Module &, ModuleAnalysisManager &) { \ 76 return PreservedAnalyses::all(); \ 77 } \ 78 }; 79 #define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 80 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \ 81 template <typename... Ts> PASS_NAME(Ts &&...) {} \ 82 Error run(Module &, MachineFunctionAnalysisManager &) { \ 83 return Error::success(); \ 84 } \ 85 PreservedAnalyses run(MachineFunction &, \ 86 MachineFunctionAnalysisManager &) { \ 87 llvm_unreachable("this api is to make new PM api happy"); \ 88 } \ 89 static AnalysisKey Key; \ 90 }; 91 #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 92 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \ 93 template <typename... Ts> PASS_NAME(Ts &&...) {} \ 94 PreservedAnalyses run(MachineFunction &, \ 95 MachineFunctionAnalysisManager &) { \ 96 return PreservedAnalyses::all(); \ 97 } \ 98 static AnalysisKey Key; \ 99 }; 100 #include "MachinePassRegistry.def" 101 102 /// This class provides access to building LLVM's passes. 103 /// 104 /// Its members provide the baseline state available to passes during their 105 /// construction. The \c MachinePassRegistry.def file specifies how to construct 106 /// all of the built-in passes, and those may reference these members during 107 /// construction. 108 template <typename DerivedT> class CodeGenPassBuilder { 109 public: 110 explicit CodeGenPassBuilder(LLVMTargetMachine &TM, CGPassBuilderOption Opts, 111 PassInstrumentationCallbacks *PIC) 112 : TM(TM), Opt(Opts), PIC(PIC) { 113 // Target could set CGPassBuilderOption::MISchedPostRA to true to achieve 114 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID) 115 116 // Target should override TM.Options.EnableIPRA in their target-specific 117 // LLVMTM ctor. See TargetMachine::setGlobalISel for example. 118 if (Opt.EnableIPRA) 119 TM.Options.EnableIPRA = *Opt.EnableIPRA; 120 121 if (Opt.EnableGlobalISelAbort) 122 TM.Options.GlobalISelAbort = *Opt.EnableGlobalISelAbort; 123 124 if (!Opt.OptimizeRegAlloc) 125 Opt.OptimizeRegAlloc = getOptLevel() != CodeGenOpt::None; 126 } 127 128 Error buildPipeline(ModulePassManager &MPM, MachineFunctionPassManager &MFPM, 129 raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, 130 CodeGenFileType FileType) const; 131 132 void registerModuleAnalyses(ModuleAnalysisManager &) const; 133 void registerFunctionAnalyses(FunctionAnalysisManager &) const; 134 void registerMachineFunctionAnalyses(MachineFunctionAnalysisManager &) const; 135 std::pair<StringRef, bool> getPassNameFromLegacyName(StringRef) const; 136 137 void registerAnalyses(MachineFunctionAnalysisManager &MFAM) const { 138 registerModuleAnalyses(*MFAM.MAM); 139 registerFunctionAnalyses(*MFAM.FAM); 140 registerMachineFunctionAnalyses(MFAM); 141 } 142 143 PassInstrumentationCallbacks *getPassInstrumentationCallbacks() const { 144 return PIC; 145 } 146 147 protected: 148 template <typename PassT> using has_key_t = decltype(PassT::Key); 149 150 template <typename PassT> 151 using is_module_pass_t = decltype(std::declval<PassT &>().run( 152 std::declval<Module &>(), std::declval<ModuleAnalysisManager &>())); 153 154 template <typename PassT> 155 using is_function_pass_t = decltype(std::declval<PassT &>().run( 156 std::declval<Function &>(), std::declval<FunctionAnalysisManager &>())); 157 158 // Function object to maintain state while adding codegen IR passes. 159 class AddIRPass { 160 public: 161 AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check = true) 162 : MPM(MPM), FPM(DebugPM) { 163 if (Check) 164 AddingFunctionPasses = false; 165 } 166 ~AddIRPass() { 167 MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM))); 168 } 169 170 // Add Function Pass 171 template <typename PassT> 172 std::enable_if_t<is_detected<is_function_pass_t, PassT>::value> 173 operator()(PassT &&Pass) { 174 if (AddingFunctionPasses && !*AddingFunctionPasses) 175 AddingFunctionPasses = true; 176 FPM.addPass(std::forward<PassT>(Pass)); 177 } 178 179 // Add Module Pass 180 template <typename PassT> 181 std::enable_if_t<is_detected<is_module_pass_t, PassT>::value && 182 !is_detected<is_function_pass_t, PassT>::value> 183 operator()(PassT &&Pass) { 184 assert((!AddingFunctionPasses || !*AddingFunctionPasses) && 185 "could not add module pass after adding function pass"); 186 MPM.addPass(std::forward<PassT>(Pass)); 187 } 188 189 private: 190 ModulePassManager &MPM; 191 FunctionPassManager FPM; 192 // The codegen IR pipeline are mostly function passes with the exceptions of 193 // a few loop and module passes. `AddingFunctionPasses` make sures that 194 // we could only add module passes at the beginning of the pipeline. Once 195 // we begin adding function passes, we could no longer add module passes. 196 // This special-casing introduces less adaptor passes. If we have the need 197 // of adding module passes after function passes, we could change the 198 // implementation to accommodate that. 199 Optional<bool> AddingFunctionPasses; 200 }; 201 202 // Function object to maintain state while adding codegen machine passes. 203 class AddMachinePass { 204 public: 205 AddMachinePass(MachineFunctionPassManager &PM) : PM(PM) {} 206 207 template <typename PassT> void operator()(PassT &&Pass) { 208 static_assert( 209 is_detected<has_key_t, PassT>::value, 210 "Machine function pass must define a static member variable `Key`."); 211 for (auto &C : BeforeCallbacks) 212 if (!C(&PassT::Key)) 213 return; 214 PM.addPass(std::forward<PassT>(Pass)); 215 for (auto &C : AfterCallbacks) 216 C(&PassT::Key); 217 } 218 219 template <typename PassT> void insertPass(AnalysisKey *ID, PassT Pass) { 220 AfterCallbacks.emplace_back( 221 [this, ID, Pass = std::move(Pass)](AnalysisKey *PassID) { 222 if (PassID == ID) 223 this->PM.addPass(std::move(Pass)); 224 }); 225 } 226 227 void disablePass(AnalysisKey *ID) { 228 BeforeCallbacks.emplace_back( 229 [ID](AnalysisKey *PassID) { return PassID != ID; }); 230 } 231 232 MachineFunctionPassManager releasePM() { return std::move(PM); } 233 234 private: 235 MachineFunctionPassManager &PM; 236 SmallVector<llvm::unique_function<bool(AnalysisKey *)>, 4> BeforeCallbacks; 237 SmallVector<llvm::unique_function<void(AnalysisKey *)>, 4> AfterCallbacks; 238 }; 239 240 LLVMTargetMachine &TM; 241 CGPassBuilderOption Opt; 242 PassInstrumentationCallbacks *PIC; 243 244 /// Target override these hooks to parse target-specific analyses. 245 void registerTargetAnalysis(ModuleAnalysisManager &) const {} 246 void registerTargetAnalysis(FunctionAnalysisManager &) const {} 247 void registerTargetAnalysis(MachineFunctionAnalysisManager &) const {} 248 std::pair<StringRef, bool> getTargetPassNameFromLegacyName(StringRef) const { 249 return {"", false}; 250 } 251 252 template <typename TMC> TMC &getTM() const { return static_cast<TMC &>(TM); } 253 CodeGenOpt::Level getOptLevel() const { return TM.getOptLevel(); } 254 255 /// Check whether or not GlobalISel should abort on error. 256 /// When this is disabled, GlobalISel will fall back on SDISel instead of 257 /// erroring out. 258 bool isGlobalISelAbortEnabled() const { 259 return TM.Options.GlobalISelAbort == GlobalISelAbortMode::Enable; 260 } 261 262 /// Check whether or not a diagnostic should be emitted when GlobalISel 263 /// uses the fallback path. In other words, it will emit a diagnostic 264 /// when GlobalISel failed and isGlobalISelAbortEnabled is false. 265 bool reportDiagnosticWhenGlobalISelFallback() const { 266 return TM.Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag; 267 } 268 269 /// addInstSelector - This method should install an instruction selector pass, 270 /// which converts from LLVM code to machine instructions. 271 Error addInstSelector(AddMachinePass &) const { 272 return make_error<StringError>("addInstSelector is not overridden", 273 inconvertibleErrorCode()); 274 } 275 276 /// Add passes that optimize instruction level parallelism for out-of-order 277 /// targets. These passes are run while the machine code is still in SSA 278 /// form, so they can use MachineTraceMetrics to control their heuristics. 279 /// 280 /// All passes added here should preserve the MachineDominatorTree, 281 /// MachineLoopInfo, and MachineTraceMetrics analyses. 282 void addILPOpts(AddMachinePass &) const {} 283 284 /// This method may be implemented by targets that want to run passes 285 /// immediately before register allocation. 286 void addPreRegAlloc(AddMachinePass &) const {} 287 288 /// addPreRewrite - Add passes to the optimized register allocation pipeline 289 /// after register allocation is complete, but before virtual registers are 290 /// rewritten to physical registers. 291 /// 292 /// These passes must preserve VirtRegMap and LiveIntervals, and when running 293 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. 294 /// When these passes run, VirtRegMap contains legal physreg assignments for 295 /// all virtual registers. 296 /// 297 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not 298 /// be honored. This is also not generally used for the the fast variant, 299 /// where the allocation and rewriting are done in one pass. 300 void addPreRewrite(AddMachinePass &) const {} 301 302 /// Add passes to be run immediately after virtual registers are rewritten 303 /// to physical registers. 304 void addPostRewrite(AddMachinePass &) const {} 305 306 /// This method may be implemented by targets that want to run passes after 307 /// register allocation pass pipeline but before prolog-epilog insertion. 308 void addPostRegAlloc(AddMachinePass &) const {} 309 310 /// This method may be implemented by targets that want to run passes after 311 /// prolog-epilog insertion and before the second instruction scheduling pass. 312 void addPreSched2(AddMachinePass &) const {} 313 314 /// This pass may be implemented by targets that want to run passes 315 /// immediately before machine code is emitted. 316 void addPreEmitPass(AddMachinePass &) const {} 317 318 /// Targets may add passes immediately before machine code is emitted in this 319 /// callback. This is called even later than `addPreEmitPass`. 320 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual 321 // position and remove the `2` suffix here as this callback is what 322 // `addPreEmitPass` *should* be but in reality isn't. 323 void addPreEmitPass2(AddMachinePass &) const {} 324 325 /// {{@ For GlobalISel 326 /// 327 328 /// addPreISel - This method should add any "last minute" LLVM->LLVM 329 /// passes (which are run just before instruction selector). 330 void addPreISel(AddIRPass &) const { 331 llvm_unreachable("addPreISel is not overridden"); 332 } 333 334 /// This method should install an IR translator pass, which converts from 335 /// LLVM code to machine instructions with possibly generic opcodes. 336 Error addIRTranslator(AddMachinePass &) const { 337 return make_error<StringError>("addIRTranslator is not overridden", 338 inconvertibleErrorCode()); 339 } 340 341 /// This method may be implemented by targets that want to run passes 342 /// immediately before legalization. 343 void addPreLegalizeMachineIR(AddMachinePass &) const {} 344 345 /// This method should install a legalize pass, which converts the instruction 346 /// sequence into one that can be selected by the target. 347 Error addLegalizeMachineIR(AddMachinePass &) const { 348 return make_error<StringError>("addLegalizeMachineIR is not overridden", 349 inconvertibleErrorCode()); 350 } 351 352 /// This method may be implemented by targets that want to run passes 353 /// immediately before the register bank selection. 354 void addPreRegBankSelect(AddMachinePass &) const {} 355 356 /// This method should install a register bank selector pass, which 357 /// assigns register banks to virtual registers without a register 358 /// class or register banks. 359 Error addRegBankSelect(AddMachinePass &) const { 360 return make_error<StringError>("addRegBankSelect is not overridden", 361 inconvertibleErrorCode()); 362 } 363 364 /// This method may be implemented by targets that want to run passes 365 /// immediately before the (global) instruction selection. 366 void addPreGlobalInstructionSelect(AddMachinePass &) const {} 367 368 /// This method should install a (global) instruction selector pass, which 369 /// converts possibly generic instructions to fully target-specific 370 /// instructions, thereby constraining all generic virtual registers to 371 /// register classes. 372 Error addGlobalInstructionSelect(AddMachinePass &) const { 373 return make_error<StringError>( 374 "addGlobalInstructionSelect is not overridden", 375 inconvertibleErrorCode()); 376 } 377 /// @}} 378 379 /// High level function that adds all passes necessary to go from llvm IR 380 /// representation to the MI representation. 381 /// Adds IR based lowering and target specific optimization passes and finally 382 /// the core instruction selection passes. 383 /// \returns true if an error occurred, false otherwise. 384 void addISelPasses(AddIRPass &) const; 385 386 /// Add the actual instruction selection passes. This does not include 387 /// preparation passes on IR. 388 Error addCoreISelPasses(AddMachinePass &) const; 389 390 /// Add the complete, standard set of LLVM CodeGen passes. 391 /// Fully developed targets will not generally override this. 392 Error addMachinePasses(AddMachinePass &) const; 393 394 /// Add passes to lower exception handling for the code generator. 395 void addPassesToHandleExceptions(AddIRPass &) const; 396 397 /// Add common target configurable passes that perform LLVM IR to IR 398 /// transforms following machine independent optimization. 399 void addIRPasses(AddIRPass &) const; 400 401 /// Add pass to prepare the LLVM IR for code generation. This should be done 402 /// before exception handling preparation passes. 403 void addCodeGenPrepare(AddIRPass &) const; 404 405 /// Add common passes that perform LLVM IR to IR transforms in preparation for 406 /// instruction selection. 407 void addISelPrepare(AddIRPass &) const; 408 409 /// Methods with trivial inline returns are convenient points in the common 410 /// codegen pass pipeline where targets may insert passes. Methods with 411 /// out-of-line standard implementations are major CodeGen stages called by 412 /// addMachinePasses. Some targets may override major stages when inserting 413 /// passes is insufficient, but maintaining overriden stages is more work. 414 /// 415 416 /// addMachineSSAOptimization - Add standard passes that optimize machine 417 /// instructions in SSA form. 418 void addMachineSSAOptimization(AddMachinePass &) const; 419 420 /// addFastRegAlloc - Add the minimum set of target-independent passes that 421 /// are required for fast register allocation. 422 Error addFastRegAlloc(AddMachinePass &) const; 423 424 /// addOptimizedRegAlloc - Add passes related to register allocation. 425 /// LLVMTargetMachine provides standard regalloc passes for most targets. 426 void addOptimizedRegAlloc(AddMachinePass &) const; 427 428 /// Add passes that optimize machine instructions after register allocation. 429 void addMachineLateOptimization(AddMachinePass &) const; 430 431 /// addGCPasses - Add late codegen passes that analyze code for garbage 432 /// collection. This should return true if GC info should be printed after 433 /// these passes. 434 void addGCPasses(AddMachinePass &) const {} 435 436 /// Add standard basic block placement passes. 437 void addBlockPlacement(AddMachinePass &) const; 438 439 using CreateMCStreamer = 440 std::function<Expected<std::unique_ptr<MCStreamer>>(MCContext &)>; 441 void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const { 442 llvm_unreachable("addAsmPrinter is not overridden"); 443 } 444 445 /// Utilities for targets to add passes to the pass manager. 446 /// 447 448 /// createTargetRegisterAllocator - Create the register allocator pass for 449 /// this target at the current optimization level. 450 void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const; 451 452 /// addMachinePasses helper to create the target-selected or overriden 453 /// regalloc pass. 454 void addRegAllocPass(AddMachinePass &, bool Optimized) const; 455 456 /// Add core register alloator passes which do the actual register assignment 457 /// and rewriting. \returns true if any passes were added. 458 Error addRegAssignmentFast(AddMachinePass &) const; 459 Error addRegAssignmentOptimized(AddMachinePass &) const; 460 461 private: 462 DerivedT &derived() { return static_cast<DerivedT &>(*this); } 463 const DerivedT &derived() const { 464 return static_cast<const DerivedT &>(*this); 465 } 466 }; 467 468 template <typename Derived> 469 Error CodeGenPassBuilder<Derived>::buildPipeline( 470 ModulePassManager &MPM, MachineFunctionPassManager &MFPM, 471 raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, 472 CodeGenFileType FileType) const { 473 AddIRPass addIRPass(MPM, Opt.DebugPM); 474 addISelPasses(addIRPass); 475 476 AddMachinePass addPass(MFPM); 477 if (auto Err = addCoreISelPasses(addPass)) 478 return std::move(Err); 479 480 if (auto Err = derived().addMachinePasses(addPass)) 481 return std::move(Err); 482 483 derived().addAsmPrinter( 484 addPass, [this, &Out, DwoOut, FileType](MCContext &Ctx) { 485 return this->TM.createMCStreamer(Out, DwoOut, FileType, Ctx); 486 }); 487 488 addPass(FreeMachineFunctionPass()); 489 return Error::success(); 490 } 491 492 static inline AAManager registerAAAnalyses(CFLAAType UseCFLAA) { 493 AAManager AA; 494 495 // The order in which these are registered determines their priority when 496 // being queried. 497 498 switch (UseCFLAA) { 499 case CFLAAType::Steensgaard: 500 AA.registerFunctionAnalysis<CFLSteensAA>(); 501 break; 502 case CFLAAType::Andersen: 503 AA.registerFunctionAnalysis<CFLAndersAA>(); 504 break; 505 case CFLAAType::Both: 506 AA.registerFunctionAnalysis<CFLAndersAA>(); 507 AA.registerFunctionAnalysis<CFLSteensAA>(); 508 break; 509 default: 510 break; 511 } 512 513 // Basic AliasAnalysis support. 514 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that 515 // BasicAliasAnalysis wins if they disagree. This is intended to help 516 // support "obvious" type-punning idioms. 517 AA.registerFunctionAnalysis<TypeBasedAA>(); 518 AA.registerFunctionAnalysis<ScopedNoAliasAA>(); 519 AA.registerFunctionAnalysis<BasicAA>(); 520 521 return AA; 522 } 523 524 template <typename Derived> 525 void CodeGenPassBuilder<Derived>::registerModuleAnalyses( 526 ModuleAnalysisManager &MAM) const { 527 #define MODULE_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ 528 MAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); 529 #include "MachinePassRegistry.def" 530 derived().registerTargetAnalysis(MAM); 531 } 532 533 template <typename Derived> 534 void CodeGenPassBuilder<Derived>::registerFunctionAnalyses( 535 FunctionAnalysisManager &FAM) const { 536 FAM.registerPass([this] { return registerAAAnalyses(this->Opt.UseCFLAA); }); 537 538 #define FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ 539 FAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); 540 #include "MachinePassRegistry.def" 541 derived().registerTargetAnalysis(FAM); 542 } 543 544 template <typename Derived> 545 void CodeGenPassBuilder<Derived>::registerMachineFunctionAnalyses( 546 MachineFunctionAnalysisManager &MFAM) const { 547 #define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ 548 MFAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); 549 #include "MachinePassRegistry.def" 550 derived().registerTargetAnalysis(MFAM); 551 } 552 553 // FIXME: For new PM, use pass name directly in commandline seems good. 554 // Translate stringfied pass name to its old commandline name. Returns the 555 // matching legacy name and a boolean value indicating if the pass is a machine 556 // pass. 557 template <typename Derived> 558 std::pair<StringRef, bool> 559 CodeGenPassBuilder<Derived>::getPassNameFromLegacyName(StringRef Name) const { 560 std::pair<StringRef, bool> Ret; 561 if (Name.empty()) 562 return Ret; 563 564 #define FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 565 if (Name == NAME) \ 566 Ret = {#PASS_NAME, false}; 567 #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 568 if (Name == NAME) \ 569 Ret = {#PASS_NAME, false}; 570 #define MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 571 if (Name == NAME) \ 572 Ret = {#PASS_NAME, false}; 573 #define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 574 if (Name == NAME) \ 575 Ret = {#PASS_NAME, false}; 576 #define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 577 if (Name == NAME) \ 578 Ret = {#PASS_NAME, true}; 579 #define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 580 if (Name == NAME) \ 581 Ret = {#PASS_NAME, true}; 582 #define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 583 if (Name == NAME) \ 584 Ret = {#PASS_NAME, true}; 585 #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 586 if (Name == NAME) \ 587 Ret = {#PASS_NAME, true}; 588 #include "llvm/CodeGen/MachinePassRegistry.def" 589 590 if (Ret.first.empty()) 591 Ret = derived().getTargetPassNameFromLegacyName(Name); 592 593 if (Ret.first.empty()) 594 report_fatal_error(Twine('\"') + Twine(Name) + 595 Twine("\" pass could not be found.")); 596 597 return Ret; 598 } 599 600 template <typename Derived> 601 void CodeGenPassBuilder<Derived>::addISelPasses(AddIRPass &addPass) const { 602 if (TM.useEmulatedTLS()) 603 addPass(LowerEmuTLSPass()); 604 605 addPass(PreISelIntrinsicLoweringPass()); 606 607 derived().addIRPasses(addPass); 608 derived().addCodeGenPrepare(addPass); 609 addPassesToHandleExceptions(addPass); 610 derived().addISelPrepare(addPass); 611 } 612 613 /// Add common target configurable passes that perform LLVM IR to IR transforms 614 /// following machine independent optimization. 615 template <typename Derived> 616 void CodeGenPassBuilder<Derived>::addIRPasses(AddIRPass &addPass) const { 617 // Before running any passes, run the verifier to determine if the input 618 // coming from the front-end and/or optimizer is valid. 619 if (!Opt.DisableVerify) 620 addPass(VerifierPass()); 621 622 // Run loop strength reduction before anything else. 623 if (getOptLevel() != CodeGenOpt::None && !Opt.DisableLSR) { 624 addPass(createFunctionToLoopPassAdaptor( 625 LoopStrengthReducePass(), /*UseMemorySSA*/ true, Opt.DebugPM)); 626 // FIXME: use -stop-after so we could remove PrintLSR 627 if (Opt.PrintLSR) 628 addPass(PrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n")); 629 } 630 631 if (getOptLevel() != CodeGenOpt::None) { 632 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of 633 // loads and compares. ExpandMemCmpPass then tries to expand those calls 634 // into optimally-sized loads and compares. The transforms are enabled by a 635 // target lowering hook. 636 if (!Opt.DisableMergeICmps) 637 addPass(MergeICmpsPass()); 638 addPass(ExpandMemCmpPass()); 639 } 640 641 // Run GC lowering passes for builtin collectors 642 // TODO: add a pass insertion point here 643 addPass(GCLoweringPass()); 644 addPass(ShadowStackGCLoweringPass()); 645 addPass(LowerConstantIntrinsicsPass()); 646 647 // Make sure that no unreachable blocks are instruction selected. 648 addPass(UnreachableBlockElimPass()); 649 650 // Prepare expensive constants for SelectionDAG. 651 if (getOptLevel() != CodeGenOpt::None && !Opt.DisableConstantHoisting) 652 addPass(ConstantHoistingPass()); 653 654 if (getOptLevel() != CodeGenOpt::None && !Opt.DisablePartialLibcallInlining) 655 addPass(PartiallyInlineLibCallsPass()); 656 657 // Instrument function entry and exit, e.g. with calls to mcount(). 658 addPass(EntryExitInstrumenterPass(/*PostInlining=*/true)); 659 660 // Add scalarization of target's unsupported masked memory intrinsics pass. 661 // the unsupported intrinsic will be replaced with a chain of basic blocks, 662 // that stores/loads element one-by-one if the appropriate mask bit is set. 663 addPass(ScalarizeMaskedMemIntrinPass()); 664 665 // Expand reduction intrinsics into shuffle sequences if the target wants to. 666 addPass(ExpandReductionsPass()); 667 } 668 669 /// Turn exception handling constructs into something the code generators can 670 /// handle. 671 template <typename Derived> 672 void CodeGenPassBuilder<Derived>::addPassesToHandleExceptions( 673 AddIRPass &addPass) const { 674 const MCAsmInfo *MCAI = TM.getMCAsmInfo(); 675 assert(MCAI && "No MCAsmInfo"); 676 switch (MCAI->getExceptionHandlingType()) { 677 case ExceptionHandling::SjLj: 678 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both 679 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise, 680 // catch info can get misplaced when a selector ends up more than one block 681 // removed from the parent invoke(s). This could happen when a landing 682 // pad is shared by multiple invokes and is also a target of a normal 683 // edge from elsewhere. 684 addPass(SjLjEHPreparePass()); 685 LLVM_FALLTHROUGH; 686 case ExceptionHandling::DwarfCFI: 687 case ExceptionHandling::ARM: 688 case ExceptionHandling::AIX: 689 addPass(DwarfEHPass(getOptLevel())); 690 break; 691 case ExceptionHandling::WinEH: 692 // We support using both GCC-style and MSVC-style exceptions on Windows, so 693 // add both preparation passes. Each pass will only actually run if it 694 // recognizes the personality function. 695 addPass(WinEHPass()); 696 addPass(DwarfEHPass(getOptLevel())); 697 break; 698 case ExceptionHandling::Wasm: 699 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs 700 // on catchpads and cleanuppads because it does not outline them into 701 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we 702 // should remove PHIs there. 703 addPass(WinEHPass(/*DemoteCatchSwitchPHIOnly=*/false)); 704 addPass(WasmEHPass()); 705 break; 706 case ExceptionHandling::None: 707 addPass(LowerInvokePass()); 708 709 // The lower invoke pass may create unreachable code. Remove it. 710 addPass(UnreachableBlockElimPass()); 711 break; 712 } 713 } 714 715 /// Add pass to prepare the LLVM IR for code generation. This should be done 716 /// before exception handling preparation passes. 717 template <typename Derived> 718 void CodeGenPassBuilder<Derived>::addCodeGenPrepare(AddIRPass &addPass) const { 719 if (getOptLevel() != CodeGenOpt::None && !Opt.DisableCGP) 720 addPass(CodeGenPreparePass()); 721 // TODO: Default ctor'd RewriteSymbolPass is no-op. 722 // addPass(RewriteSymbolPass()); 723 } 724 725 /// Add common passes that perform LLVM IR to IR transforms in preparation for 726 /// instruction selection. 727 template <typename Derived> 728 void CodeGenPassBuilder<Derived>::addISelPrepare(AddIRPass &addPass) const { 729 derived().addPreISel(addPass); 730 731 // Add both the safe stack and the stack protection passes: each of them will 732 // only protect functions that have corresponding attributes. 733 addPass(SafeStackPass()); 734 addPass(StackProtectorPass()); 735 736 if (Opt.PrintISelInput) 737 addPass(PrintFunctionPass(dbgs(), 738 "\n\n*** Final LLVM Code input to ISel ***\n")); 739 740 // All passes which modify the LLVM IR are now complete; run the verifier 741 // to ensure that the IR is valid. 742 if (!Opt.DisableVerify) 743 addPass(VerifierPass()); 744 } 745 746 template <typename Derived> 747 Error CodeGenPassBuilder<Derived>::addCoreISelPasses( 748 AddMachinePass &addPass) const { 749 // Enable FastISel with -fast-isel, but allow that to be overridden. 750 TM.setO0WantsFastISel(Opt.EnableFastISelOption.getValueOr(true)); 751 752 // Determine an instruction selector. 753 enum class SelectorType { SelectionDAG, FastISel, GlobalISel }; 754 SelectorType Selector; 755 756 if (Opt.EnableFastISelOption && *Opt.EnableFastISelOption == true) 757 Selector = SelectorType::FastISel; 758 else if ((Opt.EnableGlobalISelOption && 759 *Opt.EnableGlobalISelOption == true) || 760 (TM.Options.EnableGlobalISel && 761 (!Opt.EnableGlobalISelOption || 762 *Opt.EnableGlobalISelOption == false))) 763 Selector = SelectorType::GlobalISel; 764 else if (TM.getOptLevel() == CodeGenOpt::None && TM.getO0WantsFastISel()) 765 Selector = SelectorType::FastISel; 766 else 767 Selector = SelectorType::SelectionDAG; 768 769 // Set consistently TM.Options.EnableFastISel and EnableGlobalISel. 770 if (Selector == SelectorType::FastISel) { 771 TM.setFastISel(true); 772 TM.setGlobalISel(false); 773 } else if (Selector == SelectorType::GlobalISel) { 774 TM.setFastISel(false); 775 TM.setGlobalISel(true); 776 } 777 778 // Add instruction selector passes. 779 if (Selector == SelectorType::GlobalISel) { 780 if (auto Err = derived().addIRTranslator(addPass)) 781 return std::move(Err); 782 783 derived().addPreLegalizeMachineIR(addPass); 784 785 if (auto Err = derived().addLegalizeMachineIR(addPass)) 786 return std::move(Err); 787 788 // Before running the register bank selector, ask the target if it 789 // wants to run some passes. 790 derived().addPreRegBankSelect(addPass); 791 792 if (auto Err = derived().addRegBankSelect(addPass)) 793 return std::move(Err); 794 795 derived().addPreGlobalInstructionSelect(addPass); 796 797 if (auto Err = derived().addGlobalInstructionSelect(addPass)) 798 return std::move(Err); 799 800 // Pass to reset the MachineFunction if the ISel failed. 801 addPass(ResetMachineFunctionPass(reportDiagnosticWhenGlobalISelFallback(), 802 isGlobalISelAbortEnabled())); 803 804 // Provide a fallback path when we do not want to abort on 805 // not-yet-supported input. 806 if (!isGlobalISelAbortEnabled()) 807 if (auto Err = derived().addInstSelector(addPass)) 808 return std::move(Err); 809 810 } else if (auto Err = derived().addInstSelector(addPass)) 811 return std::move(Err); 812 813 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before 814 // FinalizeISel. 815 addPass(FinalizeISelPass()); 816 817 // // Print the instruction selected machine code... 818 // printAndVerify("After Instruction Selection"); 819 820 return Error::success(); 821 } 822 823 /// Add the complete set of target-independent postISel code generator passes. 824 /// 825 /// This can be read as the standard order of major LLVM CodeGen stages. Stages 826 /// with nontrivial configuration or multiple passes are broken out below in 827 /// add%Stage routines. 828 /// 829 /// Any CodeGenPassBuilder<Derived>::addXX routine may be overriden by the 830 /// Target. The addPre/Post methods with empty header implementations allow 831 /// injecting target-specific fixups just before or after major stages. 832 /// Additionally, targets have the flexibility to change pass order within a 833 /// stage by overriding default implementation of add%Stage routines below. Each 834 /// technique has maintainability tradeoffs because alternate pass orders are 835 /// not well supported. addPre/Post works better if the target pass is easily 836 /// tied to a common pass. But if it has subtle dependencies on multiple passes, 837 /// the target should override the stage instead. 838 template <typename Derived> 839 Error CodeGenPassBuilder<Derived>::addMachinePasses( 840 AddMachinePass &addPass) const { 841 // Add passes that optimize machine instructions in SSA form. 842 if (getOptLevel() != CodeGenOpt::None) { 843 derived().addMachineSSAOptimization(addPass); 844 } else { 845 // If the target requests it, assign local variables to stack slots relative 846 // to one another and simplify frame index references where possible. 847 addPass(LocalStackSlotPass()); 848 } 849 850 if (TM.Options.EnableIPRA) 851 addPass(RegUsageInfoPropagationPass()); 852 853 // Run pre-ra passes. 854 derived().addPreRegAlloc(addPass); 855 856 // Run register allocation and passes that are tightly coupled with it, 857 // including phi elimination and scheduling. 858 if (*Opt.OptimizeRegAlloc) { 859 derived().addOptimizedRegAlloc(addPass); 860 } else { 861 if (auto Err = derived().addFastRegAlloc(addPass)) 862 return Err; 863 } 864 865 // Run post-ra passes. 866 derived().addPostRegAlloc(addPass); 867 868 // Insert prolog/epilog code. Eliminate abstract frame index references... 869 if (getOptLevel() != CodeGenOpt::None) { 870 addPass(PostRAMachineSinkingPass()); 871 addPass(ShrinkWrapPass()); 872 } 873 874 addPass(PrologEpilogInserterPass()); 875 876 /// Add passes that optimize machine instructions after register allocation. 877 if (getOptLevel() != CodeGenOpt::None) 878 derived().addMachineLateOptimization(addPass); 879 880 // Expand pseudo instructions before second scheduling pass. 881 addPass(ExpandPostRAPseudosPass()); 882 883 // Run pre-sched2 passes. 884 derived().addPreSched2(addPass); 885 886 if (Opt.EnableImplicitNullChecks) 887 addPass(ImplicitNullChecksPass()); 888 889 // Second pass scheduler. 890 // Let Target optionally insert this pass by itself at some other 891 // point. 892 if (getOptLevel() != CodeGenOpt::None && 893 !TM.targetSchedulesPostRAScheduling()) { 894 if (Opt.MISchedPostRA) 895 addPass(PostMachineSchedulerPass()); 896 else 897 addPass(PostRASchedulerPass()); 898 } 899 900 // GC 901 derived().addGCPasses(addPass); 902 903 // Basic block placement. 904 if (getOptLevel() != CodeGenOpt::None) 905 derived().addBlockPlacement(addPass); 906 907 // Insert before XRay Instrumentation. 908 addPass(FEntryInserterPass()); 909 910 addPass(XRayInstrumentationPass()); 911 addPass(PatchableFunctionPass()); 912 913 derived().addPreEmitPass(addPass); 914 915 if (TM.Options.EnableIPRA) 916 // Collect register usage information and produce a register mask of 917 // clobbered registers, to be used to optimize call sites. 918 addPass(RegUsageInfoCollectorPass()); 919 920 addPass(FuncletLayoutPass()); 921 922 addPass(StackMapLivenessPass()); 923 addPass(LiveDebugValuesPass()); 924 925 if (TM.Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None && 926 Opt.EnableMachineOutliner != RunOutliner::NeverOutline) { 927 bool RunOnAllFunctions = 928 (Opt.EnableMachineOutliner == RunOutliner::AlwaysOutline); 929 bool AddOutliner = RunOnAllFunctions || TM.Options.SupportsDefaultOutlining; 930 if (AddOutliner) 931 addPass(MachineOutlinerPass(RunOnAllFunctions)); 932 } 933 934 // Add passes that directly emit MI after all other MI passes. 935 derived().addPreEmitPass2(addPass); 936 937 return Error::success(); 938 } 939 940 /// Add passes that optimize machine instructions in SSA form. 941 template <typename Derived> 942 void CodeGenPassBuilder<Derived>::addMachineSSAOptimization( 943 AddMachinePass &addPass) const { 944 // Pre-ra tail duplication. 945 addPass(EarlyTailDuplicatePass()); 946 947 // Optimize PHIs before DCE: removing dead PHI cycles may make more 948 // instructions dead. 949 addPass(OptimizePHIsPass()); 950 951 // This pass merges large allocas. StackSlotColoring is a different pass 952 // which merges spill slots. 953 addPass(StackColoringPass()); 954 955 // If the target requests it, assign local variables to stack slots relative 956 // to one another and simplify frame index references where possible. 957 addPass(LocalStackSlotPass()); 958 959 // With optimization, dead code should already be eliminated. However 960 // there is one known exception: lowered code for arguments that are only 961 // used by tail calls, where the tail calls reuse the incoming stack 962 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). 963 addPass(DeadMachineInstructionElimPass()); 964 965 // Allow targets to insert passes that improve instruction level parallelism, 966 // like if-conversion. Such passes will typically need dominator trees and 967 // loop info, just like LICM and CSE below. 968 derived().addILPOpts(addPass); 969 970 addPass(EarlyMachineLICMPass()); 971 addPass(MachineCSEPass()); 972 973 addPass(MachineSinkingPass()); 974 975 addPass(PeepholeOptimizerPass()); 976 // Clean-up the dead code that may have been generated by peephole 977 // rewriting. 978 addPass(DeadMachineInstructionElimPass()); 979 } 980 981 //===---------------------------------------------------------------------===// 982 /// Register Allocation Pass Configuration 983 //===---------------------------------------------------------------------===// 984 985 /// Instantiate the default register allocator pass for this target for either 986 /// the optimized or unoptimized allocation path. This will be added to the pass 987 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc 988 /// in the optimized case. 989 /// 990 /// A target that uses the standard regalloc pass order for fast or optimized 991 /// allocation may still override this for per-target regalloc 992 /// selection. But -regalloc=... always takes precedence. 993 template <typename Derived> 994 void CodeGenPassBuilder<Derived>::addTargetRegisterAllocator( 995 AddMachinePass &addPass, bool Optimized) const { 996 if (Optimized) 997 addPass(RAGreedyPass()); 998 else 999 addPass(RAFastPass()); 1000 } 1001 1002 /// Find and instantiate the register allocation pass requested by this target 1003 /// at the current optimization level. Different register allocators are 1004 /// defined as separate passes because they may require different analysis. 1005 template <typename Derived> 1006 void CodeGenPassBuilder<Derived>::addRegAllocPass(AddMachinePass &addPass, 1007 bool Optimized) const { 1008 if (Opt.RegAlloc == RegAllocType::Default) 1009 // With no -regalloc= override, ask the target for a regalloc pass. 1010 derived().addTargetRegisterAllocator(addPass, Optimized); 1011 else if (Opt.RegAlloc == RegAllocType::Basic) 1012 addPass(RABasicPass()); 1013 else if (Opt.RegAlloc == RegAllocType::Fast) 1014 addPass(RAFastPass()); 1015 else if (Opt.RegAlloc == RegAllocType::Greedy) 1016 addPass(RAGreedyPass()); 1017 else if (Opt.RegAlloc == RegAllocType::PBQP) 1018 addPass(RAPBQPPass()); 1019 else 1020 llvm_unreachable("unknonwn register allocator type"); 1021 } 1022 1023 template <typename Derived> 1024 Error CodeGenPassBuilder<Derived>::addRegAssignmentFast( 1025 AddMachinePass &addPass) const { 1026 if (Opt.RegAlloc != RegAllocType::Default && 1027 Opt.RegAlloc != RegAllocType::Fast) 1028 return make_error<StringError>( 1029 "Must use fast (default) register allocator for unoptimized regalloc.", 1030 inconvertibleErrorCode()); 1031 1032 addRegAllocPass(addPass, false); 1033 return Error::success(); 1034 } 1035 1036 template <typename Derived> 1037 Error CodeGenPassBuilder<Derived>::addRegAssignmentOptimized( 1038 AddMachinePass &addPass) const { 1039 // Add the selected register allocation pass. 1040 addRegAllocPass(addPass, true); 1041 1042 // Allow targets to change the register assignments before rewriting. 1043 derived().addPreRewrite(addPass); 1044 1045 // Finally rewrite virtual registers. 1046 addPass(VirtRegRewriterPass()); 1047 // Perform stack slot coloring and post-ra machine LICM. 1048 // 1049 // FIXME: Re-enable coloring with register when it's capable of adding 1050 // kill markers. 1051 addPass(StackSlotColoringPass()); 1052 1053 return Error::success(); 1054 } 1055 1056 /// Add the minimum set of target-independent passes that are required for 1057 /// register allocation. No coalescing or scheduling. 1058 template <typename Derived> 1059 Error CodeGenPassBuilder<Derived>::addFastRegAlloc( 1060 AddMachinePass &addPass) const { 1061 addPass(PHIEliminationPass()); 1062 addPass(TwoAddressInstructionPass()); 1063 return derived().addRegAssignmentFast(addPass); 1064 } 1065 1066 /// Add standard target-independent passes that are tightly coupled with 1067 /// optimized register allocation, including coalescing, machine instruction 1068 /// scheduling, and register allocation itself. 1069 template <typename Derived> 1070 void CodeGenPassBuilder<Derived>::addOptimizedRegAlloc( 1071 AddMachinePass &addPass) const { 1072 addPass(DetectDeadLanesPass()); 1073 1074 addPass(ProcessImplicitDefsPass()); 1075 1076 // Edge splitting is smarter with machine loop info. 1077 addPass(PHIEliminationPass()); 1078 1079 // Eventually, we want to run LiveIntervals before PHI elimination. 1080 if (Opt.EarlyLiveIntervals) 1081 addPass(LiveIntervalsPass()); 1082 1083 addPass(TwoAddressInstructionPass()); 1084 addPass(RegisterCoalescerPass()); 1085 1086 // The machine scheduler may accidentally create disconnected components 1087 // when moving subregister definitions around, avoid this by splitting them to 1088 // separate vregs before. Splitting can also improve reg. allocation quality. 1089 addPass(RenameIndependentSubregsPass()); 1090 1091 // PreRA instruction scheduling. 1092 addPass(MachineSchedulerPass()); 1093 1094 if (derived().addRegAssignmentOptimized(addPass)) { 1095 // Allow targets to expand pseudo instructions depending on the choice of 1096 // registers before MachineCopyPropagation. 1097 derived().addPostRewrite(addPass); 1098 1099 // Copy propagate to forward register uses and try to eliminate COPYs that 1100 // were not coalesced. 1101 addPass(MachineCopyPropagationPass()); 1102 1103 // Run post-ra machine LICM to hoist reloads / remats. 1104 // 1105 // FIXME: can this move into MachineLateOptimization? 1106 addPass(MachineLICMPass()); 1107 } 1108 } 1109 1110 //===---------------------------------------------------------------------===// 1111 /// Post RegAlloc Pass Configuration 1112 //===---------------------------------------------------------------------===// 1113 1114 /// Add passes that optimize machine instructions after register allocation. 1115 template <typename Derived> 1116 void CodeGenPassBuilder<Derived>::addMachineLateOptimization( 1117 AddMachinePass &addPass) const { 1118 // Branch folding must be run after regalloc and prolog/epilog insertion. 1119 addPass(BranchFolderPass()); 1120 1121 // Tail duplication. 1122 // Note that duplicating tail just increases code size and degrades 1123 // performance for targets that require Structured Control Flow. 1124 // In addition it can also make CFG irreducible. Thus we disable it. 1125 if (!TM.requiresStructuredCFG()) 1126 addPass(TailDuplicatePass()); 1127 1128 // Copy propagation. 1129 addPass(MachineCopyPropagationPass()); 1130 } 1131 1132 /// Add standard basic block placement passes. 1133 template <typename Derived> 1134 void CodeGenPassBuilder<Derived>::addBlockPlacement( 1135 AddMachinePass &addPass) const { 1136 addPass(MachineBlockPlacementPass()); 1137 // Run a separate pass to collect block placement statistics. 1138 if (Opt.EnableBlockPlacementStats) 1139 addPass(MachineBlockPlacementStatsPass()); 1140 } 1141 1142 } // namespace llvm 1143 1144 #endif // LLVM_CODEGEN_CODEGENPASSBUILDER_H 1145