1 //===- Construction of codegen pass pipelines ------------------*- C++ -*--===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// 10 /// Interfaces for registering analysis passes, producing common pass manager 11 /// configurations, and parsing of pass pipelines. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_CODEGENPASSBUILDER_H 16 #define LLVM_CODEGEN_CODEGENPASSBUILDER_H 17 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/Analysis/AliasAnalysis.h" 21 #include "llvm/Analysis/BasicAliasAnalysis.h" 22 #include "llvm/Analysis/CFLAndersAliasAnalysis.h" 23 #include "llvm/Analysis/CFLSteensAliasAnalysis.h" 24 #include "llvm/Analysis/ScopedNoAliasAA.h" 25 #include "llvm/Analysis/TargetTransformInfo.h" 26 #include "llvm/Analysis/TypeBasedAliasAnalysis.h" 27 #include "llvm/CodeGen/ExpandReductions.h" 28 #include "llvm/CodeGen/MachinePassManager.h" 29 #include "llvm/CodeGen/PreISelIntrinsicLowering.h" 30 #include "llvm/CodeGen/ReplaceWithVeclib.h" 31 #include "llvm/CodeGen/UnreachableBlockElim.h" 32 #include "llvm/IR/IRPrintingPasses.h" 33 #include "llvm/IR/PassManager.h" 34 #include "llvm/IR/Verifier.h" 35 #include "llvm/MC/MCAsmInfo.h" 36 #include "llvm/MC/MCTargetOptions.h" 37 #include "llvm/Support/CodeGen.h" 38 #include "llvm/Support/Debug.h" 39 #include "llvm/Support/Error.h" 40 #include "llvm/Support/ErrorHandling.h" 41 #include "llvm/Target/CGPassBuilderOption.h" 42 #include "llvm/Target/TargetMachine.h" 43 #include "llvm/Transforms/Scalar/ConstantHoisting.h" 44 #include "llvm/Transforms/Scalar/LoopPassManager.h" 45 #include "llvm/Transforms/Scalar/LoopStrengthReduce.h" 46 #include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h" 47 #include "llvm/Transforms/Scalar/MergeICmps.h" 48 #include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h" 49 #include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h" 50 #include "llvm/Transforms/Utils/EntryExitInstrumenter.h" 51 #include "llvm/Transforms/Utils/LowerInvoke.h" 52 #include <cassert> 53 #include <type_traits> 54 #include <utility> 55 56 namespace llvm { 57 58 // FIXME: Dummy target independent passes definitions that have not yet been 59 // ported to new pass manager. Once they do, remove these. 60 #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 61 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \ 62 template <typename... Ts> PASS_NAME(Ts &&...) {} \ 63 PreservedAnalyses run(Function &, FunctionAnalysisManager &) { \ 64 return PreservedAnalyses::all(); \ 65 } \ 66 }; 67 #define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 68 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \ 69 template <typename... Ts> PASS_NAME(Ts &&...) {} \ 70 PreservedAnalyses run(Module &, ModuleAnalysisManager &) { \ 71 return PreservedAnalyses::all(); \ 72 } \ 73 }; 74 #define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 75 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \ 76 template <typename... Ts> PASS_NAME(Ts &&...) {} \ 77 Error run(Module &, MachineFunctionAnalysisManager &) { \ 78 return Error::success(); \ 79 } \ 80 PreservedAnalyses run(MachineFunction &, \ 81 MachineFunctionAnalysisManager &) { \ 82 llvm_unreachable("this api is to make new PM api happy"); \ 83 } \ 84 static AnalysisKey Key; \ 85 }; 86 #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 87 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \ 88 template <typename... Ts> PASS_NAME(Ts &&...) {} \ 89 PreservedAnalyses run(MachineFunction &, \ 90 MachineFunctionAnalysisManager &) { \ 91 return PreservedAnalyses::all(); \ 92 } \ 93 static AnalysisKey Key; \ 94 }; 95 #include "MachinePassRegistry.def" 96 97 /// This class provides access to building LLVM's passes. 98 /// 99 /// Its members provide the baseline state available to passes during their 100 /// construction. The \c MachinePassRegistry.def file specifies how to construct 101 /// all of the built-in passes, and those may reference these members during 102 /// construction. 103 template <typename DerivedT> class CodeGenPassBuilder { 104 public: 105 explicit CodeGenPassBuilder(LLVMTargetMachine &TM, CGPassBuilderOption Opts, 106 PassInstrumentationCallbacks *PIC) 107 : TM(TM), Opt(Opts), PIC(PIC) { 108 // Target could set CGPassBuilderOption::MISchedPostRA to true to achieve 109 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID) 110 111 // Target should override TM.Options.EnableIPRA in their target-specific 112 // LLVMTM ctor. See TargetMachine::setGlobalISel for example. 113 if (Opt.EnableIPRA) 114 TM.Options.EnableIPRA = *Opt.EnableIPRA; 115 116 if (Opt.EnableGlobalISelAbort) 117 TM.Options.GlobalISelAbort = *Opt.EnableGlobalISelAbort; 118 119 if (!Opt.OptimizeRegAlloc) 120 Opt.OptimizeRegAlloc = getOptLevel() != CodeGenOpt::None; 121 } 122 123 Error buildPipeline(ModulePassManager &MPM, MachineFunctionPassManager &MFPM, 124 raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, 125 CodeGenFileType FileType) const; 126 127 void registerModuleAnalyses(ModuleAnalysisManager &) const; 128 void registerFunctionAnalyses(FunctionAnalysisManager &) const; 129 void registerMachineFunctionAnalyses(MachineFunctionAnalysisManager &) const; 130 std::pair<StringRef, bool> getPassNameFromLegacyName(StringRef) const; 131 132 void registerAnalyses(MachineFunctionAnalysisManager &MFAM) const { 133 registerModuleAnalyses(*MFAM.MAM); 134 registerFunctionAnalyses(*MFAM.FAM); 135 registerMachineFunctionAnalyses(MFAM); 136 } 137 138 PassInstrumentationCallbacks *getPassInstrumentationCallbacks() const { 139 return PIC; 140 } 141 142 protected: 143 template <typename PassT> using has_key_t = decltype(PassT::Key); 144 145 template <typename PassT> 146 using is_module_pass_t = decltype(std::declval<PassT &>().run( 147 std::declval<Module &>(), std::declval<ModuleAnalysisManager &>())); 148 149 template <typename PassT> 150 using is_function_pass_t = decltype(std::declval<PassT &>().run( 151 std::declval<Function &>(), std::declval<FunctionAnalysisManager &>())); 152 153 // Function object to maintain state while adding codegen IR passes. 154 class AddIRPass { 155 public: 156 AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check = true) 157 : MPM(MPM) { 158 if (Check) 159 AddingFunctionPasses = false; 160 } 161 ~AddIRPass() { 162 MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM))); 163 } 164 165 // Add Function Pass 166 template <typename PassT> 167 std::enable_if_t<is_detected<is_function_pass_t, PassT>::value> 168 operator()(PassT &&Pass) { 169 if (AddingFunctionPasses && !*AddingFunctionPasses) 170 AddingFunctionPasses = true; 171 FPM.addPass(std::forward<PassT>(Pass)); 172 } 173 174 // Add Module Pass 175 template <typename PassT> 176 std::enable_if_t<is_detected<is_module_pass_t, PassT>::value && 177 !is_detected<is_function_pass_t, PassT>::value> 178 operator()(PassT &&Pass) { 179 assert((!AddingFunctionPasses || !*AddingFunctionPasses) && 180 "could not add module pass after adding function pass"); 181 MPM.addPass(std::forward<PassT>(Pass)); 182 } 183 184 private: 185 ModulePassManager &MPM; 186 FunctionPassManager FPM; 187 // The codegen IR pipeline are mostly function passes with the exceptions of 188 // a few loop and module passes. `AddingFunctionPasses` make sures that 189 // we could only add module passes at the beginning of the pipeline. Once 190 // we begin adding function passes, we could no longer add module passes. 191 // This special-casing introduces less adaptor passes. If we have the need 192 // of adding module passes after function passes, we could change the 193 // implementation to accommodate that. 194 Optional<bool> AddingFunctionPasses; 195 }; 196 197 // Function object to maintain state while adding codegen machine passes. 198 class AddMachinePass { 199 public: 200 AddMachinePass(MachineFunctionPassManager &PM) : PM(PM) {} 201 202 template <typename PassT> void operator()(PassT &&Pass) { 203 static_assert( 204 is_detected<has_key_t, PassT>::value, 205 "Machine function pass must define a static member variable `Key`."); 206 for (auto &C : BeforeCallbacks) 207 if (!C(&PassT::Key)) 208 return; 209 PM.addPass(std::forward<PassT>(Pass)); 210 for (auto &C : AfterCallbacks) 211 C(&PassT::Key); 212 } 213 214 template <typename PassT> void insertPass(AnalysisKey *ID, PassT Pass) { 215 AfterCallbacks.emplace_back( 216 [this, ID, Pass = std::move(Pass)](AnalysisKey *PassID) { 217 if (PassID == ID) 218 this->PM.addPass(std::move(Pass)); 219 }); 220 } 221 222 void disablePass(AnalysisKey *ID) { 223 BeforeCallbacks.emplace_back( 224 [ID](AnalysisKey *PassID) { return PassID != ID; }); 225 } 226 227 MachineFunctionPassManager releasePM() { return std::move(PM); } 228 229 private: 230 MachineFunctionPassManager &PM; 231 SmallVector<llvm::unique_function<bool(AnalysisKey *)>, 4> BeforeCallbacks; 232 SmallVector<llvm::unique_function<void(AnalysisKey *)>, 4> AfterCallbacks; 233 }; 234 235 LLVMTargetMachine &TM; 236 CGPassBuilderOption Opt; 237 PassInstrumentationCallbacks *PIC; 238 239 /// Target override these hooks to parse target-specific analyses. 240 void registerTargetAnalysis(ModuleAnalysisManager &) const {} 241 void registerTargetAnalysis(FunctionAnalysisManager &) const {} 242 void registerTargetAnalysis(MachineFunctionAnalysisManager &) const {} 243 std::pair<StringRef, bool> getTargetPassNameFromLegacyName(StringRef) const { 244 return {"", false}; 245 } 246 247 template <typename TMC> TMC &getTM() const { return static_cast<TMC &>(TM); } 248 CodeGenOpt::Level getOptLevel() const { return TM.getOptLevel(); } 249 250 /// Check whether or not GlobalISel should abort on error. 251 /// When this is disabled, GlobalISel will fall back on SDISel instead of 252 /// erroring out. 253 bool isGlobalISelAbortEnabled() const { 254 return TM.Options.GlobalISelAbort == GlobalISelAbortMode::Enable; 255 } 256 257 /// Check whether or not a diagnostic should be emitted when GlobalISel 258 /// uses the fallback path. In other words, it will emit a diagnostic 259 /// when GlobalISel failed and isGlobalISelAbortEnabled is false. 260 bool reportDiagnosticWhenGlobalISelFallback() const { 261 return TM.Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag; 262 } 263 264 /// addInstSelector - This method should install an instruction selector pass, 265 /// which converts from LLVM code to machine instructions. 266 Error addInstSelector(AddMachinePass &) const { 267 return make_error<StringError>("addInstSelector is not overridden", 268 inconvertibleErrorCode()); 269 } 270 271 /// Add passes that optimize instruction level parallelism for out-of-order 272 /// targets. These passes are run while the machine code is still in SSA 273 /// form, so they can use MachineTraceMetrics to control their heuristics. 274 /// 275 /// All passes added here should preserve the MachineDominatorTree, 276 /// MachineLoopInfo, and MachineTraceMetrics analyses. 277 void addILPOpts(AddMachinePass &) const {} 278 279 /// This method may be implemented by targets that want to run passes 280 /// immediately before register allocation. 281 void addPreRegAlloc(AddMachinePass &) const {} 282 283 /// addPreRewrite - Add passes to the optimized register allocation pipeline 284 /// after register allocation is complete, but before virtual registers are 285 /// rewritten to physical registers. 286 /// 287 /// These passes must preserve VirtRegMap and LiveIntervals, and when running 288 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. 289 /// When these passes run, VirtRegMap contains legal physreg assignments for 290 /// all virtual registers. 291 /// 292 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not 293 /// be honored. This is also not generally used for the the fast variant, 294 /// where the allocation and rewriting are done in one pass. 295 void addPreRewrite(AddMachinePass &) const {} 296 297 /// Add passes to be run immediately after virtual registers are rewritten 298 /// to physical registers. 299 void addPostRewrite(AddMachinePass &) const {} 300 301 /// This method may be implemented by targets that want to run passes after 302 /// register allocation pass pipeline but before prolog-epilog insertion. 303 void addPostRegAlloc(AddMachinePass &) const {} 304 305 /// This method may be implemented by targets that want to run passes after 306 /// prolog-epilog insertion and before the second instruction scheduling pass. 307 void addPreSched2(AddMachinePass &) const {} 308 309 /// This pass may be implemented by targets that want to run passes 310 /// immediately before machine code is emitted. 311 void addPreEmitPass(AddMachinePass &) const {} 312 313 /// Targets may add passes immediately before machine code is emitted in this 314 /// callback. This is called even later than `addPreEmitPass`. 315 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual 316 // position and remove the `2` suffix here as this callback is what 317 // `addPreEmitPass` *should* be but in reality isn't. 318 void addPreEmitPass2(AddMachinePass &) const {} 319 320 /// {{@ For GlobalISel 321 /// 322 323 /// addPreISel - This method should add any "last minute" LLVM->LLVM 324 /// passes (which are run just before instruction selector). 325 void addPreISel(AddIRPass &) const { 326 llvm_unreachable("addPreISel is not overridden"); 327 } 328 329 /// This method should install an IR translator pass, which converts from 330 /// LLVM code to machine instructions with possibly generic opcodes. 331 Error addIRTranslator(AddMachinePass &) const { 332 return make_error<StringError>("addIRTranslator is not overridden", 333 inconvertibleErrorCode()); 334 } 335 336 /// This method may be implemented by targets that want to run passes 337 /// immediately before legalization. 338 void addPreLegalizeMachineIR(AddMachinePass &) const {} 339 340 /// This method should install a legalize pass, which converts the instruction 341 /// sequence into one that can be selected by the target. 342 Error addLegalizeMachineIR(AddMachinePass &) const { 343 return make_error<StringError>("addLegalizeMachineIR is not overridden", 344 inconvertibleErrorCode()); 345 } 346 347 /// This method may be implemented by targets that want to run passes 348 /// immediately before the register bank selection. 349 void addPreRegBankSelect(AddMachinePass &) const {} 350 351 /// This method should install a register bank selector pass, which 352 /// assigns register banks to virtual registers without a register 353 /// class or register banks. 354 Error addRegBankSelect(AddMachinePass &) const { 355 return make_error<StringError>("addRegBankSelect is not overridden", 356 inconvertibleErrorCode()); 357 } 358 359 /// This method may be implemented by targets that want to run passes 360 /// immediately before the (global) instruction selection. 361 void addPreGlobalInstructionSelect(AddMachinePass &) const {} 362 363 /// This method should install a (global) instruction selector pass, which 364 /// converts possibly generic instructions to fully target-specific 365 /// instructions, thereby constraining all generic virtual registers to 366 /// register classes. 367 Error addGlobalInstructionSelect(AddMachinePass &) const { 368 return make_error<StringError>( 369 "addGlobalInstructionSelect is not overridden", 370 inconvertibleErrorCode()); 371 } 372 /// @}} 373 374 /// High level function that adds all passes necessary to go from llvm IR 375 /// representation to the MI representation. 376 /// Adds IR based lowering and target specific optimization passes and finally 377 /// the core instruction selection passes. 378 void addISelPasses(AddIRPass &) const; 379 380 /// Add the actual instruction selection passes. This does not include 381 /// preparation passes on IR. 382 Error addCoreISelPasses(AddMachinePass &) const; 383 384 /// Add the complete, standard set of LLVM CodeGen passes. 385 /// Fully developed targets will not generally override this. 386 Error addMachinePasses(AddMachinePass &) const; 387 388 /// Add passes to lower exception handling for the code generator. 389 void addPassesToHandleExceptions(AddIRPass &) const; 390 391 /// Add common target configurable passes that perform LLVM IR to IR 392 /// transforms following machine independent optimization. 393 void addIRPasses(AddIRPass &) const; 394 395 /// Add pass to prepare the LLVM IR for code generation. This should be done 396 /// before exception handling preparation passes. 397 void addCodeGenPrepare(AddIRPass &) const; 398 399 /// Add common passes that perform LLVM IR to IR transforms in preparation for 400 /// instruction selection. 401 void addISelPrepare(AddIRPass &) const; 402 403 /// Methods with trivial inline returns are convenient points in the common 404 /// codegen pass pipeline where targets may insert passes. Methods with 405 /// out-of-line standard implementations are major CodeGen stages called by 406 /// addMachinePasses. Some targets may override major stages when inserting 407 /// passes is insufficient, but maintaining overriden stages is more work. 408 /// 409 410 /// addMachineSSAOptimization - Add standard passes that optimize machine 411 /// instructions in SSA form. 412 void addMachineSSAOptimization(AddMachinePass &) const; 413 414 /// addFastRegAlloc - Add the minimum set of target-independent passes that 415 /// are required for fast register allocation. 416 Error addFastRegAlloc(AddMachinePass &) const; 417 418 /// addOptimizedRegAlloc - Add passes related to register allocation. 419 /// LLVMTargetMachine provides standard regalloc passes for most targets. 420 void addOptimizedRegAlloc(AddMachinePass &) const; 421 422 /// Add passes that optimize machine instructions after register allocation. 423 void addMachineLateOptimization(AddMachinePass &) const; 424 425 /// addGCPasses - Add late codegen passes that analyze code for garbage 426 /// collection. This should return true if GC info should be printed after 427 /// these passes. 428 void addGCPasses(AddMachinePass &) const {} 429 430 /// Add standard basic block placement passes. 431 void addBlockPlacement(AddMachinePass &) const; 432 433 using CreateMCStreamer = 434 std::function<Expected<std::unique_ptr<MCStreamer>>(MCContext &)>; 435 void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const { 436 llvm_unreachable("addAsmPrinter is not overridden"); 437 } 438 439 /// Utilities for targets to add passes to the pass manager. 440 /// 441 442 /// createTargetRegisterAllocator - Create the register allocator pass for 443 /// this target at the current optimization level. 444 void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const; 445 446 /// addMachinePasses helper to create the target-selected or overriden 447 /// regalloc pass. 448 void addRegAllocPass(AddMachinePass &, bool Optimized) const; 449 450 /// Add core register alloator passes which do the actual register assignment 451 /// and rewriting. \returns true if any passes were added. 452 Error addRegAssignmentFast(AddMachinePass &) const; 453 Error addRegAssignmentOptimized(AddMachinePass &) const; 454 455 private: 456 DerivedT &derived() { return static_cast<DerivedT &>(*this); } 457 const DerivedT &derived() const { 458 return static_cast<const DerivedT &>(*this); 459 } 460 }; 461 462 template <typename Derived> 463 Error CodeGenPassBuilder<Derived>::buildPipeline( 464 ModulePassManager &MPM, MachineFunctionPassManager &MFPM, 465 raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, 466 CodeGenFileType FileType) const { 467 AddIRPass addIRPass(MPM, Opt.DebugPM); 468 addISelPasses(addIRPass); 469 470 AddMachinePass addPass(MFPM); 471 if (auto Err = addCoreISelPasses(addPass)) 472 return std::move(Err); 473 474 if (auto Err = derived().addMachinePasses(addPass)) 475 return std::move(Err); 476 477 derived().addAsmPrinter( 478 addPass, [this, &Out, DwoOut, FileType](MCContext &Ctx) { 479 return this->TM.createMCStreamer(Out, DwoOut, FileType, Ctx); 480 }); 481 482 addPass(FreeMachineFunctionPass()); 483 return Error::success(); 484 } 485 486 static inline AAManager registerAAAnalyses(CFLAAType UseCFLAA) { 487 AAManager AA; 488 489 // The order in which these are registered determines their priority when 490 // being queried. 491 492 switch (UseCFLAA) { 493 case CFLAAType::Steensgaard: 494 AA.registerFunctionAnalysis<CFLSteensAA>(); 495 break; 496 case CFLAAType::Andersen: 497 AA.registerFunctionAnalysis<CFLAndersAA>(); 498 break; 499 case CFLAAType::Both: 500 AA.registerFunctionAnalysis<CFLAndersAA>(); 501 AA.registerFunctionAnalysis<CFLSteensAA>(); 502 break; 503 default: 504 break; 505 } 506 507 // Basic AliasAnalysis support. 508 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that 509 // BasicAliasAnalysis wins if they disagree. This is intended to help 510 // support "obvious" type-punning idioms. 511 AA.registerFunctionAnalysis<TypeBasedAA>(); 512 AA.registerFunctionAnalysis<ScopedNoAliasAA>(); 513 AA.registerFunctionAnalysis<BasicAA>(); 514 515 return AA; 516 } 517 518 template <typename Derived> 519 void CodeGenPassBuilder<Derived>::registerModuleAnalyses( 520 ModuleAnalysisManager &MAM) const { 521 #define MODULE_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ 522 MAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); 523 #include "MachinePassRegistry.def" 524 derived().registerTargetAnalysis(MAM); 525 } 526 527 template <typename Derived> 528 void CodeGenPassBuilder<Derived>::registerFunctionAnalyses( 529 FunctionAnalysisManager &FAM) const { 530 FAM.registerPass([this] { return registerAAAnalyses(this->Opt.UseCFLAA); }); 531 532 #define FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ 533 FAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); 534 #include "MachinePassRegistry.def" 535 derived().registerTargetAnalysis(FAM); 536 } 537 538 template <typename Derived> 539 void CodeGenPassBuilder<Derived>::registerMachineFunctionAnalyses( 540 MachineFunctionAnalysisManager &MFAM) const { 541 #define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ 542 MFAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); 543 #include "MachinePassRegistry.def" 544 derived().registerTargetAnalysis(MFAM); 545 } 546 547 // FIXME: For new PM, use pass name directly in commandline seems good. 548 // Translate stringfied pass name to its old commandline name. Returns the 549 // matching legacy name and a boolean value indicating if the pass is a machine 550 // pass. 551 template <typename Derived> 552 std::pair<StringRef, bool> 553 CodeGenPassBuilder<Derived>::getPassNameFromLegacyName(StringRef Name) const { 554 std::pair<StringRef, bool> Ret; 555 if (Name.empty()) 556 return Ret; 557 558 #define FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 559 if (Name == NAME) \ 560 Ret = {#PASS_NAME, false}; 561 #define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 562 if (Name == NAME) \ 563 Ret = {#PASS_NAME, false}; 564 #define MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 565 if (Name == NAME) \ 566 Ret = {#PASS_NAME, false}; 567 #define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 568 if (Name == NAME) \ 569 Ret = {#PASS_NAME, false}; 570 #define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 571 if (Name == NAME) \ 572 Ret = {#PASS_NAME, true}; 573 #define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 574 if (Name == NAME) \ 575 Ret = {#PASS_NAME, true}; 576 #define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 577 if (Name == NAME) \ 578 Ret = {#PASS_NAME, true}; 579 #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ 580 if (Name == NAME) \ 581 Ret = {#PASS_NAME, true}; 582 #include "llvm/CodeGen/MachinePassRegistry.def" 583 584 if (Ret.first.empty()) 585 Ret = derived().getTargetPassNameFromLegacyName(Name); 586 587 if (Ret.first.empty()) 588 report_fatal_error(Twine('\"') + Twine(Name) + 589 Twine("\" pass could not be found.")); 590 591 return Ret; 592 } 593 594 template <typename Derived> 595 void CodeGenPassBuilder<Derived>::addISelPasses(AddIRPass &addPass) const { 596 if (TM.useEmulatedTLS()) 597 addPass(LowerEmuTLSPass()); 598 599 addPass(PreISelIntrinsicLoweringPass()); 600 601 derived().addIRPasses(addPass); 602 derived().addCodeGenPrepare(addPass); 603 addPassesToHandleExceptions(addPass); 604 derived().addISelPrepare(addPass); 605 } 606 607 /// Add common target configurable passes that perform LLVM IR to IR transforms 608 /// following machine independent optimization. 609 template <typename Derived> 610 void CodeGenPassBuilder<Derived>::addIRPasses(AddIRPass &addPass) const { 611 // Before running any passes, run the verifier to determine if the input 612 // coming from the front-end and/or optimizer is valid. 613 if (!Opt.DisableVerify) 614 addPass(VerifierPass()); 615 616 // Run loop strength reduction before anything else. 617 if (getOptLevel() != CodeGenOpt::None && !Opt.DisableLSR) { 618 addPass(createFunctionToLoopPassAdaptor( 619 LoopStrengthReducePass(), /*UseMemorySSA*/ true, Opt.DebugPM)); 620 // FIXME: use -stop-after so we could remove PrintLSR 621 if (Opt.PrintLSR) 622 addPass(PrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n")); 623 } 624 625 if (getOptLevel() != CodeGenOpt::None) { 626 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of 627 // loads and compares. ExpandMemCmpPass then tries to expand those calls 628 // into optimally-sized loads and compares. The transforms are enabled by a 629 // target lowering hook. 630 if (!Opt.DisableMergeICmps) 631 addPass(MergeICmpsPass()); 632 addPass(ExpandMemCmpPass()); 633 } 634 635 // Run GC lowering passes for builtin collectors 636 // TODO: add a pass insertion point here 637 addPass(GCLoweringPass()); 638 addPass(ShadowStackGCLoweringPass()); 639 addPass(LowerConstantIntrinsicsPass()); 640 641 // Make sure that no unreachable blocks are instruction selected. 642 addPass(UnreachableBlockElimPass()); 643 644 // Prepare expensive constants for SelectionDAG. 645 if (getOptLevel() != CodeGenOpt::None && !Opt.DisableConstantHoisting) 646 addPass(ConstantHoistingPass()); 647 648 // Replace calls to LLVM intrinsics (e.g., exp, log) operating on vector 649 // operands with calls to the corresponding functions in a vector library. 650 if (getOptLevel() != CodeGenOpt::None) 651 addPass(ReplaceWithVeclib()); 652 653 if (getOptLevel() != CodeGenOpt::None && !Opt.DisablePartialLibcallInlining) 654 addPass(PartiallyInlineLibCallsPass()); 655 656 // Instrument function entry and exit, e.g. with calls to mcount(). 657 addPass(EntryExitInstrumenterPass(/*PostInlining=*/true)); 658 659 // Add scalarization of target's unsupported masked memory intrinsics pass. 660 // the unsupported intrinsic will be replaced with a chain of basic blocks, 661 // that stores/loads element one-by-one if the appropriate mask bit is set. 662 addPass(ScalarizeMaskedMemIntrinPass()); 663 664 // Expand reduction intrinsics into shuffle sequences if the target wants to. 665 addPass(ExpandReductionsPass()); 666 667 // Convert conditional moves to conditional jumps when profitable. 668 if (getOptLevel() != CodeGenOpt::None && !Opt.DisableSelectOptimize) 669 addPass(SelectOptimizePass()); 670 } 671 672 /// Turn exception handling constructs into something the code generators can 673 /// handle. 674 template <typename Derived> 675 void CodeGenPassBuilder<Derived>::addPassesToHandleExceptions( 676 AddIRPass &addPass) const { 677 const MCAsmInfo *MCAI = TM.getMCAsmInfo(); 678 assert(MCAI && "No MCAsmInfo"); 679 switch (MCAI->getExceptionHandlingType()) { 680 case ExceptionHandling::SjLj: 681 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both 682 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise, 683 // catch info can get misplaced when a selector ends up more than one block 684 // removed from the parent invoke(s). This could happen when a landing 685 // pad is shared by multiple invokes and is also a target of a normal 686 // edge from elsewhere. 687 addPass(SjLjEHPreparePass()); 688 LLVM_FALLTHROUGH; 689 case ExceptionHandling::DwarfCFI: 690 case ExceptionHandling::ARM: 691 case ExceptionHandling::AIX: 692 addPass(DwarfEHPass(getOptLevel())); 693 break; 694 case ExceptionHandling::WinEH: 695 // We support using both GCC-style and MSVC-style exceptions on Windows, so 696 // add both preparation passes. Each pass will only actually run if it 697 // recognizes the personality function. 698 addPass(WinEHPass()); 699 addPass(DwarfEHPass(getOptLevel())); 700 break; 701 case ExceptionHandling::Wasm: 702 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs 703 // on catchpads and cleanuppads because it does not outline them into 704 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we 705 // should remove PHIs there. 706 addPass(WinEHPass(/*DemoteCatchSwitchPHIOnly=*/false)); 707 addPass(WasmEHPass()); 708 break; 709 case ExceptionHandling::None: 710 addPass(LowerInvokePass()); 711 712 // The lower invoke pass may create unreachable code. Remove it. 713 addPass(UnreachableBlockElimPass()); 714 break; 715 } 716 } 717 718 /// Add pass to prepare the LLVM IR for code generation. This should be done 719 /// before exception handling preparation passes. 720 template <typename Derived> 721 void CodeGenPassBuilder<Derived>::addCodeGenPrepare(AddIRPass &addPass) const { 722 if (getOptLevel() != CodeGenOpt::None && !Opt.DisableCGP) 723 addPass(CodeGenPreparePass()); 724 // TODO: Default ctor'd RewriteSymbolPass is no-op. 725 // addPass(RewriteSymbolPass()); 726 } 727 728 /// Add common passes that perform LLVM IR to IR transforms in preparation for 729 /// instruction selection. 730 template <typename Derived> 731 void CodeGenPassBuilder<Derived>::addISelPrepare(AddIRPass &addPass) const { 732 derived().addPreISel(addPass); 733 734 // Add both the safe stack and the stack protection passes: each of them will 735 // only protect functions that have corresponding attributes. 736 addPass(SafeStackPass()); 737 addPass(StackProtectorPass()); 738 739 if (Opt.PrintISelInput) 740 addPass(PrintFunctionPass(dbgs(), 741 "\n\n*** Final LLVM Code input to ISel ***\n")); 742 743 // All passes which modify the LLVM IR are now complete; run the verifier 744 // to ensure that the IR is valid. 745 if (!Opt.DisableVerify) 746 addPass(VerifierPass()); 747 } 748 749 template <typename Derived> 750 Error CodeGenPassBuilder<Derived>::addCoreISelPasses( 751 AddMachinePass &addPass) const { 752 // Enable FastISel with -fast-isel, but allow that to be overridden. 753 TM.setO0WantsFastISel(Opt.EnableFastISelOption.value_or(true)); 754 755 // Determine an instruction selector. 756 enum class SelectorType { SelectionDAG, FastISel, GlobalISel }; 757 SelectorType Selector; 758 759 if (Opt.EnableFastISelOption && *Opt.EnableFastISelOption == true) 760 Selector = SelectorType::FastISel; 761 else if ((Opt.EnableGlobalISelOption && 762 *Opt.EnableGlobalISelOption == true) || 763 (TM.Options.EnableGlobalISel && 764 (!Opt.EnableGlobalISelOption || 765 *Opt.EnableGlobalISelOption == false))) 766 Selector = SelectorType::GlobalISel; 767 else if (TM.getOptLevel() == CodeGenOpt::None && TM.getO0WantsFastISel()) 768 Selector = SelectorType::FastISel; 769 else 770 Selector = SelectorType::SelectionDAG; 771 772 // Set consistently TM.Options.EnableFastISel and EnableGlobalISel. 773 if (Selector == SelectorType::FastISel) { 774 TM.setFastISel(true); 775 TM.setGlobalISel(false); 776 } else if (Selector == SelectorType::GlobalISel) { 777 TM.setFastISel(false); 778 TM.setGlobalISel(true); 779 } 780 781 // Add instruction selector passes. 782 if (Selector == SelectorType::GlobalISel) { 783 if (auto Err = derived().addIRTranslator(addPass)) 784 return std::move(Err); 785 786 derived().addPreLegalizeMachineIR(addPass); 787 788 if (auto Err = derived().addLegalizeMachineIR(addPass)) 789 return std::move(Err); 790 791 // Before running the register bank selector, ask the target if it 792 // wants to run some passes. 793 derived().addPreRegBankSelect(addPass); 794 795 if (auto Err = derived().addRegBankSelect(addPass)) 796 return std::move(Err); 797 798 derived().addPreGlobalInstructionSelect(addPass); 799 800 if (auto Err = derived().addGlobalInstructionSelect(addPass)) 801 return std::move(Err); 802 803 // Pass to reset the MachineFunction if the ISel failed. 804 addPass(ResetMachineFunctionPass(reportDiagnosticWhenGlobalISelFallback(), 805 isGlobalISelAbortEnabled())); 806 807 // Provide a fallback path when we do not want to abort on 808 // not-yet-supported input. 809 if (!isGlobalISelAbortEnabled()) 810 if (auto Err = derived().addInstSelector(addPass)) 811 return std::move(Err); 812 813 } else if (auto Err = derived().addInstSelector(addPass)) 814 return std::move(Err); 815 816 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before 817 // FinalizeISel. 818 addPass(FinalizeISelPass()); 819 820 // // Print the instruction selected machine code... 821 // printAndVerify("After Instruction Selection"); 822 823 return Error::success(); 824 } 825 826 /// Add the complete set of target-independent postISel code generator passes. 827 /// 828 /// This can be read as the standard order of major LLVM CodeGen stages. Stages 829 /// with nontrivial configuration or multiple passes are broken out below in 830 /// add%Stage routines. 831 /// 832 /// Any CodeGenPassBuilder<Derived>::addXX routine may be overriden by the 833 /// Target. The addPre/Post methods with empty header implementations allow 834 /// injecting target-specific fixups just before or after major stages. 835 /// Additionally, targets have the flexibility to change pass order within a 836 /// stage by overriding default implementation of add%Stage routines below. Each 837 /// technique has maintainability tradeoffs because alternate pass orders are 838 /// not well supported. addPre/Post works better if the target pass is easily 839 /// tied to a common pass. But if it has subtle dependencies on multiple passes, 840 /// the target should override the stage instead. 841 template <typename Derived> 842 Error CodeGenPassBuilder<Derived>::addMachinePasses( 843 AddMachinePass &addPass) const { 844 // Add passes that optimize machine instructions in SSA form. 845 if (getOptLevel() != CodeGenOpt::None) { 846 derived().addMachineSSAOptimization(addPass); 847 } else { 848 // If the target requests it, assign local variables to stack slots relative 849 // to one another and simplify frame index references where possible. 850 addPass(LocalStackSlotPass()); 851 } 852 853 if (TM.Options.EnableIPRA) 854 addPass(RegUsageInfoPropagationPass()); 855 856 // Run pre-ra passes. 857 derived().addPreRegAlloc(addPass); 858 859 // Run register allocation and passes that are tightly coupled with it, 860 // including phi elimination and scheduling. 861 if (*Opt.OptimizeRegAlloc) { 862 derived().addOptimizedRegAlloc(addPass); 863 } else { 864 if (auto Err = derived().addFastRegAlloc(addPass)) 865 return Err; 866 } 867 868 // Run post-ra passes. 869 derived().addPostRegAlloc(addPass); 870 871 addPass(RemoveRedundantDebugValuesPass()); 872 873 // Insert prolog/epilog code. Eliminate abstract frame index references... 874 if (getOptLevel() != CodeGenOpt::None) { 875 addPass(PostRAMachineSinkingPass()); 876 addPass(ShrinkWrapPass()); 877 } 878 879 addPass(PrologEpilogInserterPass()); 880 881 /// Add passes that optimize machine instructions after register allocation. 882 if (getOptLevel() != CodeGenOpt::None) 883 derived().addMachineLateOptimization(addPass); 884 885 // Expand pseudo instructions before second scheduling pass. 886 addPass(ExpandPostRAPseudosPass()); 887 888 // Run pre-sched2 passes. 889 derived().addPreSched2(addPass); 890 891 if (Opt.EnableImplicitNullChecks) 892 addPass(ImplicitNullChecksPass()); 893 894 // Second pass scheduler. 895 // Let Target optionally insert this pass by itself at some other 896 // point. 897 if (getOptLevel() != CodeGenOpt::None && 898 !TM.targetSchedulesPostRAScheduling()) { 899 if (Opt.MISchedPostRA) 900 addPass(PostMachineSchedulerPass()); 901 else 902 addPass(PostRASchedulerPass()); 903 } 904 905 // GC 906 derived().addGCPasses(addPass); 907 908 // Basic block placement. 909 if (getOptLevel() != CodeGenOpt::None) 910 derived().addBlockPlacement(addPass); 911 912 // Insert before XRay Instrumentation. 913 addPass(FEntryInserterPass()); 914 915 addPass(XRayInstrumentationPass()); 916 addPass(PatchableFunctionPass()); 917 918 derived().addPreEmitPass(addPass); 919 920 if (TM.Options.EnableIPRA) 921 // Collect register usage information and produce a register mask of 922 // clobbered registers, to be used to optimize call sites. 923 addPass(RegUsageInfoCollectorPass()); 924 925 addPass(FuncletLayoutPass()); 926 927 addPass(StackMapLivenessPass()); 928 addPass(LiveDebugValuesPass()); 929 930 if (TM.Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None && 931 Opt.EnableMachineOutliner != RunOutliner::NeverOutline) { 932 bool RunOnAllFunctions = 933 (Opt.EnableMachineOutliner == RunOutliner::AlwaysOutline); 934 bool AddOutliner = RunOnAllFunctions || TM.Options.SupportsDefaultOutlining; 935 if (AddOutliner) 936 addPass(MachineOutlinerPass(RunOnAllFunctions)); 937 } 938 939 // Add passes that directly emit MI after all other MI passes. 940 derived().addPreEmitPass2(addPass); 941 942 return Error::success(); 943 } 944 945 /// Add passes that optimize machine instructions in SSA form. 946 template <typename Derived> 947 void CodeGenPassBuilder<Derived>::addMachineSSAOptimization( 948 AddMachinePass &addPass) const { 949 // Pre-ra tail duplication. 950 addPass(EarlyTailDuplicatePass()); 951 952 // Optimize PHIs before DCE: removing dead PHI cycles may make more 953 // instructions dead. 954 addPass(OptimizePHIsPass()); 955 956 // This pass merges large allocas. StackSlotColoring is a different pass 957 // which merges spill slots. 958 addPass(StackColoringPass()); 959 960 // If the target requests it, assign local variables to stack slots relative 961 // to one another and simplify frame index references where possible. 962 addPass(LocalStackSlotPass()); 963 964 // With optimization, dead code should already be eliminated. However 965 // there is one known exception: lowered code for arguments that are only 966 // used by tail calls, where the tail calls reuse the incoming stack 967 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). 968 addPass(DeadMachineInstructionElimPass()); 969 970 // Allow targets to insert passes that improve instruction level parallelism, 971 // like if-conversion. Such passes will typically need dominator trees and 972 // loop info, just like LICM and CSE below. 973 derived().addILPOpts(addPass); 974 975 addPass(EarlyMachineLICMPass()); 976 addPass(MachineCSEPass()); 977 978 addPass(MachineSinkingPass()); 979 980 addPass(PeepholeOptimizerPass()); 981 // Clean-up the dead code that may have been generated by peephole 982 // rewriting. 983 addPass(DeadMachineInstructionElimPass()); 984 } 985 986 //===---------------------------------------------------------------------===// 987 /// Register Allocation Pass Configuration 988 //===---------------------------------------------------------------------===// 989 990 /// Instantiate the default register allocator pass for this target for either 991 /// the optimized or unoptimized allocation path. This will be added to the pass 992 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc 993 /// in the optimized case. 994 /// 995 /// A target that uses the standard regalloc pass order for fast or optimized 996 /// allocation may still override this for per-target regalloc 997 /// selection. But -regalloc=... always takes precedence. 998 template <typename Derived> 999 void CodeGenPassBuilder<Derived>::addTargetRegisterAllocator( 1000 AddMachinePass &addPass, bool Optimized) const { 1001 if (Optimized) 1002 addPass(RAGreedyPass()); 1003 else 1004 addPass(RAFastPass()); 1005 } 1006 1007 /// Find and instantiate the register allocation pass requested by this target 1008 /// at the current optimization level. Different register allocators are 1009 /// defined as separate passes because they may require different analysis. 1010 template <typename Derived> 1011 void CodeGenPassBuilder<Derived>::addRegAllocPass(AddMachinePass &addPass, 1012 bool Optimized) const { 1013 if (Opt.RegAlloc == RegAllocType::Default) 1014 // With no -regalloc= override, ask the target for a regalloc pass. 1015 derived().addTargetRegisterAllocator(addPass, Optimized); 1016 else if (Opt.RegAlloc == RegAllocType::Basic) 1017 addPass(RABasicPass()); 1018 else if (Opt.RegAlloc == RegAllocType::Fast) 1019 addPass(RAFastPass()); 1020 else if (Opt.RegAlloc == RegAllocType::Greedy) 1021 addPass(RAGreedyPass()); 1022 else if (Opt.RegAlloc == RegAllocType::PBQP) 1023 addPass(RAPBQPPass()); 1024 else 1025 llvm_unreachable("unknonwn register allocator type"); 1026 } 1027 1028 template <typename Derived> 1029 Error CodeGenPassBuilder<Derived>::addRegAssignmentFast( 1030 AddMachinePass &addPass) const { 1031 if (Opt.RegAlloc != RegAllocType::Default && 1032 Opt.RegAlloc != RegAllocType::Fast) 1033 return make_error<StringError>( 1034 "Must use fast (default) register allocator for unoptimized regalloc.", 1035 inconvertibleErrorCode()); 1036 1037 addRegAllocPass(addPass, false); 1038 return Error::success(); 1039 } 1040 1041 template <typename Derived> 1042 Error CodeGenPassBuilder<Derived>::addRegAssignmentOptimized( 1043 AddMachinePass &addPass) const { 1044 // Add the selected register allocation pass. 1045 addRegAllocPass(addPass, true); 1046 1047 // Allow targets to change the register assignments before rewriting. 1048 derived().addPreRewrite(addPass); 1049 1050 // Finally rewrite virtual registers. 1051 addPass(VirtRegRewriterPass()); 1052 // Perform stack slot coloring and post-ra machine LICM. 1053 // 1054 // FIXME: Re-enable coloring with register when it's capable of adding 1055 // kill markers. 1056 addPass(StackSlotColoringPass()); 1057 1058 return Error::success(); 1059 } 1060 1061 /// Add the minimum set of target-independent passes that are required for 1062 /// register allocation. No coalescing or scheduling. 1063 template <typename Derived> 1064 Error CodeGenPassBuilder<Derived>::addFastRegAlloc( 1065 AddMachinePass &addPass) const { 1066 addPass(PHIEliminationPass()); 1067 addPass(TwoAddressInstructionPass()); 1068 return derived().addRegAssignmentFast(addPass); 1069 } 1070 1071 /// Add standard target-independent passes that are tightly coupled with 1072 /// optimized register allocation, including coalescing, machine instruction 1073 /// scheduling, and register allocation itself. 1074 template <typename Derived> 1075 void CodeGenPassBuilder<Derived>::addOptimizedRegAlloc( 1076 AddMachinePass &addPass) const { 1077 addPass(DetectDeadLanesPass()); 1078 1079 addPass(ProcessImplicitDefsPass()); 1080 1081 // Edge splitting is smarter with machine loop info. 1082 addPass(PHIEliminationPass()); 1083 1084 // Eventually, we want to run LiveIntervals before PHI elimination. 1085 if (Opt.EarlyLiveIntervals) 1086 addPass(LiveIntervalsPass()); 1087 1088 addPass(TwoAddressInstructionPass()); 1089 addPass(RegisterCoalescerPass()); 1090 1091 // The machine scheduler may accidentally create disconnected components 1092 // when moving subregister definitions around, avoid this by splitting them to 1093 // separate vregs before. Splitting can also improve reg. allocation quality. 1094 addPass(RenameIndependentSubregsPass()); 1095 1096 // PreRA instruction scheduling. 1097 addPass(MachineSchedulerPass()); 1098 1099 if (derived().addRegAssignmentOptimized(addPass)) { 1100 // Allow targets to expand pseudo instructions depending on the choice of 1101 // registers before MachineCopyPropagation. 1102 derived().addPostRewrite(addPass); 1103 1104 // Copy propagate to forward register uses and try to eliminate COPYs that 1105 // were not coalesced. 1106 addPass(MachineCopyPropagationPass()); 1107 1108 // Run post-ra machine LICM to hoist reloads / remats. 1109 // 1110 // FIXME: can this move into MachineLateOptimization? 1111 addPass(MachineLICMPass()); 1112 } 1113 } 1114 1115 //===---------------------------------------------------------------------===// 1116 /// Post RegAlloc Pass Configuration 1117 //===---------------------------------------------------------------------===// 1118 1119 /// Add passes that optimize machine instructions after register allocation. 1120 template <typename Derived> 1121 void CodeGenPassBuilder<Derived>::addMachineLateOptimization( 1122 AddMachinePass &addPass) const { 1123 // Branch folding must be run after regalloc and prolog/epilog insertion. 1124 addPass(BranchFolderPass()); 1125 1126 // Tail duplication. 1127 // Note that duplicating tail just increases code size and degrades 1128 // performance for targets that require Structured Control Flow. 1129 // In addition it can also make CFG irreducible. Thus we disable it. 1130 if (!TM.requiresStructuredCFG()) 1131 addPass(TailDuplicatePass()); 1132 1133 // Copy propagation. 1134 addPass(MachineCopyPropagationPass()); 1135 } 1136 1137 /// Add standard basic block placement passes. 1138 template <typename Derived> 1139 void CodeGenPassBuilder<Derived>::addBlockPlacement( 1140 AddMachinePass &addPass) const { 1141 addPass(MachineBlockPlacementPass()); 1142 // Run a separate pass to collect block placement statistics. 1143 if (Opt.EnableBlockPlacementStats) 1144 addPass(MachineBlockPlacementStatsPass()); 1145 } 1146 1147 } // namespace llvm 1148 1149 #endif // LLVM_CODEGEN_CODEGENPASSBUILDER_H 1150